阅读说明：本技术 基于基板管理控制器的服务器网口芯片管理方法、装置、设备 (Server network port chip management method, device and equipment based on substrate management controller ) 是由 秦珍彬 于 2021-09-03 设计创作，主要内容包括：本发明公开了一种基于基板管理控制器的服务器网口芯片管理方法、装置、设备。其中,所述方法包括：将计算机芯片的高速串行计算机扩展总线标准通道分别连接到不同的物理网口芯片,和通过通用输入/输出口对该物理网口芯片所关联的每个包编码配置为不同值,以及基于基板管理控制器只通过一路简化媒体独立接口通道,对该配置为不同值的每个包编码进行最大化管理。通过上述方式,能够实现只通过一路简化媒体独立接口通道就能够完成对8个不同的包编码的控制访问。(The invention discloses a server network port chip management method, device and equipment based on a baseboard management controller. Wherein the method comprises the following steps: the method comprises the steps of respectively connecting high-speed serial computer expansion bus standard channels of a computer chip to different physical network port chips, configuring each packet code associated with the physical network port chips into different values through a universal input/output port, and performing maximum management on each packet code configured into different values through only one path of simplified media independent interface channel based on a substrate management controller. By the method, the control access to 8 different packet codes can be completed only by one path of simplified media independent interface channel.)

1. A server network port chip management method based on a baseboard management controller is characterized by comprising the following steps:

connecting standard channels of a high-speed serial computer expansion bus of a computer chip to different physical network port chips respectively;

configuring each packet code associated with the physical network port chip into different values through a general input/output port;

and based on that the baseboard management controller carries out maximum management on each packet code configured to different values through only one path of simplified media independent interface channel.

2. The baseboard management controller-based server portal chip management method of claim 1, wherein configuring each packet code associated with the physical portal chip to a different value via a general purpose input/output port comprises:

and configuring each packet code associated with the physical network port chip into different values through a universal input/output port by adopting a mode of configuring the packet code by an input/output interface of a complex programmable logic device.

3. The baseboard management controller based server portal chip management method of claim 1, wherein the baseboard management controller performs maximum management on each packet code configured to have different values only through one simplified media independent interface channel, comprising:

and performing maximum management on each packet code configured to different values by adopting a mode of serially connecting 8 network ports from the first network port, the second network port, the third network port to the eighth network port and only one path of simplified media independent interface channel based on a baseboard management controller.

4. The baseboard management controller based server portal chip management method of claim 1, wherein after the baseboard management controller maximally manages each packet code configured to a different value by only one simplified media independent interface channel, further comprising:

and maintaining each packet code subjected to the maximum management according to a preset time frequency.

5. The utility model provides a server net gape chip management device based on base plate management controller which characterized in that includes:

the system comprises a connection module, a configuration module and a management module;

the connection module is used for connecting the high-speed serial computer expansion bus standard channels of the computer chip to different physical network port chips respectively;

the configuration module is used for configuring each packet code associated with the physical network port chip into different values through a general input/output port;

the management module is used for performing maximum management on each packet code configured to different values only through one simplified media independent interface channel based on the baseboard management controller.

6. The baseboard management controller-based server portal chip management apparatus of claim 5, wherein the configuration module is specifically configured to:

and configuring each packet code associated with the physical network port chip into different values through a universal input/output port by adopting a mode of configuring the packet code by an input/output interface of a complex programmable logic device.

7. The baseboard management controller-based server portal chip management apparatus of claim 5, wherein the management module is specifically configured to:

and performing maximum management on each packet code configured to different values by adopting a mode of serially connecting 8 network ports from the first network port, the second network port, the third network port to the eighth network port and only one path of simplified media independent interface channel based on a baseboard management controller.

8. The baseboard management controller based server portal chip management apparatus of claim 5, further comprising:

a maintenance module;

and the maintenance module is used for maintaining each packet code subjected to the maximum management according to a preset time frequency.

9. A computer device, comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the baseboard management controller-based server portal chip management method of any of claims 1-4.

10. A computer-readable storage medium, storing a computer program which, when executed by a processor, implements the baseboard management controller-based server portal chip management method according to any one of claims 1 to 4.

Technical Field

The invention relates to the technical field of computers, in particular to a server network port chip management method, device and equipment based on a baseboard management controller.

Background

In the related art, in order to manage a server portal, in addition to performing effective portal resource management on HOST Operating System (HOST Operating System), the BMC (Baseboard management Controller) may perform out-of-band management, and the BMC mainly manages the server portal through NCSI (Network Connectivity Status Indicator) protocol technology; the NCSI protocol technology management is realized, and besides the support of the network port firmware, the effective management of the server network port can be realized only by docking the user interface technology of the BMC.

Most of the existing single boards are only used for network ports carried on the single boards; the Package (Package) of the internet access is usually fixed and defaulted to 0 and the maximum channel (channel) is 8, that is, one network card can support the management of 8 server internet accesses at most. In addition, the NCSI protocol can be transmitted to the network port chip through the RMII channel, so that the management of the network port chip is realized. Meanwhile, the PackageID (packet code) may be fixedly configured to be 0, message stream data of RMII (Reduced Media Independent Interface) may be transmitted through the first network port, the second network port and the user by using GPIO (General-purpose input/output).

According to the protocol, a RMII connected line can control at most 8 different PackageIDs, and each PackageID has at most 32 channels. In order to allow the BMC to control more portal chips, the BMC needs to provide more RMII channels to control the portal chips, which consumes more BMC physical resources, while the existing portal chips only have 2-way portal resources, one way is already used for the management portal of the BMC, and only one way can be provided.

However, due to the limitation of the portal package id, the package id is 0, and is already allocated to the on-board portal chip, if the management of the portal chip on one RMII channel is to be continued; the PCIE card must be assigned with different package ids, which cannot be implemented for the same PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) card interface chip without external control, and cannot implement control access to 8 different packet codes only through one simplified media independent interface channel.

Disclosure of Invention

In view of this, the present invention provides a method, an apparatus, and a device for managing a server network interface chip based on a baseboard management controller, which can achieve control access to 8 different packet codes only through one simplified media independent interface channel.

According to one aspect of the invention, a server network port chip management method based on a baseboard management controller is provided, which comprises the following steps: connecting standard channels of a high-speed serial computer expansion bus of a computer chip to different physical network port chips respectively; configuring each packet code associated with the physical network port chip into different values through a general input/output port; and based on that the baseboard management controller carries out maximum management on each packet code configured to different values through only one path of simplified media independent interface channel.

Wherein configuring each packet code associated with the physical network interface chip to a different value via a general purpose input/output port comprises: and configuring each packet code associated with the physical network port chip into different values through a universal input/output port by adopting a mode of configuring the packet code by an input/output interface of a complex programmable logic device.

Wherein, the baseboard management controller performs maximum management on each packet code configured to different values only through one simplified media independent interface channel, and the maximum management includes: and performing maximum management on each packet code configured to different values by adopting a mode of serially connecting 8 network ports from the first network port, the second network port, the third network port to the eighth network port and only one path of simplified media independent interface channel based on a baseboard management controller.

Wherein, after the baseboard management controller performs maximum management on each packet code configured to different values only through one simplified media independent interface channel, the method further comprises: and maintaining each packet code subjected to the maximum management according to a preset time frequency.

According to another aspect of the present invention, there is provided a baseboard management controller-based server portal chip management apparatus, including: the system comprises a connection module, a configuration module and a management module; the connection module is used for connecting the high-speed serial computer expansion bus standard channels of the computer chip to different physical network port chips respectively; the configuration module is used for configuring each packet code associated with the physical network port chip into different values through a general input/output port; the management module is used for performing maximum management on each packet code configured to different values only through one simplified media independent interface channel based on the baseboard management controller.

Wherein the configuration module is specifically configured to: and configuring each packet code associated with the physical network port chip into different values through a universal input/output port by adopting a mode of configuring the packet code by an input/output interface of a complex programmable logic device.

The management module is specifically configured to: and performing maximum management on each packet code configured to different values by adopting a mode of serially connecting 8 network ports from the first network port, the second network port, the third network port to the eighth network port and only one path of simplified media independent interface channel based on a baseboard management controller.

Wherein, the server net gape chip management device based on the baseboard management controller further comprises: a maintenance module; and the maintenance module is used for maintaining each packet code subjected to the maximum management according to a preset time frequency.

According to yet another aspect of the present invention, there is provided a computer apparatus comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any of the baseboard management controller-based server portal chip management methods described above.

According to still another aspect of the present invention, there is provided a computer readable storage medium storing a computer program which, when executed by a processor, implements the baseboard management controller-based server portal chip management method according to any one of the above.

It can be found that, with the above scheme, the PCIE lanes of the high-speed serial computer expansion bus standard of the computer chip may be respectively connected to different physical network interface chips, and each packet coding packet id associated with the physical network interface chip may be configured to have different values through the general input/output port GPIO, and each packet coding packet id configured to have different values may be maximally managed through only one simplified media independent interface RMII lane based on the baseboard management controller BMC, so that control access to 8 different packet codes can be completed through only one simplified media independent interface lane.

Furthermore, in the above scheme, a mode of configuring the packet coding packegeids by using an input/output IO interface of the complex programmable logic device may be adopted, and each packet coding packegeid associated with the physical network port chip is configured to have a different value through a general input/output port GPIO.

Further, in the above scheme, a mode of connecting 8 ports, namely the first port, the second port, the third port to the eighth port, in series may be adopted, and based on that the BMC performs maximum management on each packet code packet id configured to have different values only through one simplified media independent interface RMII channel, such an advantage is that control access to 8 different packet codes can be completed only through one simplified media independent interface channel.

Furthermore, the scheme can maintain each packet code packageID which is maximally managed according to the preset time frequency, and the advantage is that the control access to 8 different packet codes can be continuously and stably completed only through one simplified media independent interface channel.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic flowchart illustrating an embodiment of a method for managing a server socket chip based on a baseboard management controller according to the present invention;

FIG. 2 is a schematic flow chart illustrating a server portal chip management method based on a baseboard management controller according to another embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an embodiment of a baseboard management controller-based server socket chip management apparatus according to the present invention;

FIG. 4 is a schematic structural diagram of another embodiment of a baseboard management controller-based server portal chip management apparatus according to the present invention;

FIG. 5 is a schematic structural diagram of an embodiment of the computer apparatus of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.

The invention provides a server network port chip management method based on a baseboard management controller, which can realize that 8 different packet codes can be controlled and accessed only through a simplified media independent interface channel.

Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a server socket chip management method based on a baseboard management controller according to an embodiment of the present invention. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 1 if the results are substantially the same. As shown in fig. 1, the method comprises the steps of:

s101: and respectively connecting the PCIE channels of the high-speed serial computer expansion bus standard of the computer chip to different physical network port chips.

In this embodiment, the physical network interface chip may support a network connection status indicator NCSI protocol, a simplified media independent interface RMII channel, and the like, which is not limited in the present invention.

In this embodiment, the physical network port chip may determine the number of the outgoing network ports according to a chip type, a service scenario, and the like, where the number of the outgoing network ports may be not greater than 32 network ports, may also be greater than 32 network ports, and the like, and the present invention is not limited thereto.

S102: and configuring each packet coding package ID associated with the physical network port chip into different values through a general input/output port GPIO.

The configuring, by the GPIO, each packet coding packet id associated with the physical socket chip into different values may include:

the method adopts an input/output (IO) interface of a Complex Programmable Logic Device (CPLD) to configure the packet coding packageID, and configures each packet coding packageID associated with the physical network port chip into different values through a general purpose input/output (GPIO), so that the method has the advantages of realizing high-speed serial computer expansion bus standard plug-in card compatible with different chips and ensuring that the packet coding does not conflict.

In this embodiment, as the PackageID can be configured by the IO of the CPLD, the number of GPIOs required by each chip may not exceed 3, may also be 3, may also exceed 3, and the like, which is not limited in the present invention.

S103: and based on the fact that the BMC carries out maximum management on each packet coding package ID configured to different values through only one simplified media independent interface RMII channel.

The BMC performs maximum management on each packet code package id configured to have different values only through one simplified media independent interface RMII channel, and may include:

the method is characterized in that a mode that 8 network ports from the first network port, the second network port, the third network port to the eighth network port are connected in series is adopted, and each packet code package ID configured to different values is managed to the maximum extent only through one simplified media independent interface RMII channel based on the baseboard management controller BMC, so that the advantage that the control access to 8 different packet codes can be completed only through one simplified media independent interface channel can be realized.

After the BMC performs maximum management on each packet code package id configured to have different values through only one simplified media independent interface RMII channel, the method may further include:

and maintaining each packet code packageID subjected to maximum management according to the preset time frequency, so that the advantage that the control access to 8 different packet codes can be continuously and stably finished only by one path of simplified media independent interface channel can be realized.

It can be found that, in this embodiment, the PCIE lanes of the high-speed serial computer expansion bus standard of the computer chip may be respectively connected to different physical network interface chips, and each packet coding packet id associated with the physical network interface chip may be configured to have different values through the general input/output port GPIO, and each packet coding packet id configured to have different values may be maximally managed through one simplified media independent interface RMII lane based on the baseboard management controller BMC, so that control access to 8 different packet codes can be completed through only one simplified media independent interface lane.

Further, in this embodiment, a mode of configuring the packet coding packegeids by using an input/output IO interface of the complex programmable logic device may be adopted, and each packet coding packegeid associated with the physical network port chip is configured to have a different value by using a general purpose input/output port GPIO.

Further, in this embodiment, a mode of connecting 8 ports, including the first port, the second port, the third port, and the eighth port, in series may be adopted, and based on that the BMC performs maximum management on each packet code packageID configured to have different values only through one simplified media independent interface RMII channel, such an advantage is that it is possible to complete control access to 8 different packet codes only through one simplified media independent interface channel.

Referring to fig. 2, fig. 2 is a schematic flowchart illustrating a server portal chip management method based on a bmc according to another embodiment of the present invention. In this embodiment, the method includes the steps of:

s201: and respectively connecting the PCIE channels of the high-speed serial computer expansion bus standard of the computer chip to different physical network port chips.

As described above in S101, further description is omitted here.

S202: and configuring each packet coding package ID associated with the physical network port chip into different values through a general input/output port GPIO.

As described above in S102, further description is omitted here.

S203: and based on the fact that the BMC carries out maximum management on each packet coding package ID configured to different values through only one simplified media independent interface RMII channel.

As described above in S103, which is not described herein.

S204: and maintaining each package code packageID subjected to maximum management according to a preset time frequency.

It can be found that, in this embodiment, each packet code packageID that is maximally managed may be maintained according to a preset time frequency, which has the advantage of being able to continuously and stably complete control access to 8 different packet codes only through one simplified media independent interface channel.

The invention also provides a server network port chip management device based on the baseboard management controller, which can realize that the control access to 8 different packet codes can be completed only by one path of simplified media independent interface channel.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a server network port chip management device based on a baseboard management controller according to an embodiment of the present invention. In this embodiment, the baseboard management controller-based server portal chip management apparatus 30 includes a connection module 31, a configuration module 32, and a management module 33.

The connection module 31 is configured to connect the PCIE channels of the high-speed serial computer expansion bus standard of the computer chip to different physical network interface chips respectively.

The configuration module 32 is configured to configure each packet encoding packageID associated with the physical network interface chip into a different value through a general purpose input/output (GPIO) port.

The management module 33 is configured to perform maximum management on each packet code package id configured to have different values through only one simplified media independent interface RMII channel based on the BMC.

Optionally, the configuration module 32 may be specifically configured to:

and configuring each packet coding package ID associated with the physical network port chip into different values through a general input/output (GPIO) port by adopting a mode of configuring the packet coding package IDs through an input/output (IO) interface of the complex programmable logic device.

Optionally, the management module 33 may be specifically configured to:

the method is characterized in that a mode that 8 network ports from the first network port, the second network port, the third network port to the eighth network port are connected in series is adopted, and the maximum management is carried out on each packet coding package ID configured to be different values through only one simplified media independent interface RMII channel based on a baseboard management controller BMC.

Referring to fig. 4, fig. 4 is a schematic structural diagram of another embodiment of a server portal chip management apparatus based on a baseboard management controller according to the present invention. Different from the previous embodiment, the server portal chip management apparatus 40 based on a bmc according to this embodiment further includes a maintenance module 41.

The maintenance module 41 is configured to maintain each package code packageID subjected to the maximum management according to a preset time frequency.

Each unit module of the server network port chip management device 30/40 based on the bmc can respectively execute the corresponding steps in the above method embodiments, so that the description of each unit module is not repeated herein, and please refer to the description of the corresponding steps above in detail.

The present invention further provides a computer device, as shown in fig. 5, comprising: at least one processor 51; and a memory 52 communicatively coupled to the at least one processor 51; the memory 52 stores instructions executable by the at least one processor 51, and the instructions are executed by the at least one processor 51, so that the at least one processor 51 can execute the above-mentioned server socket chip management method based on the bmc.

Wherein the memory 52 and the processor 51 are coupled in a bus, which may comprise any number of interconnected buses and bridges, which couple one or more of the various circuits of the processor 51 and the memory 52 together. The bus may also connect various other circuits such as peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further herein. A bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor 51 is transmitted over a wireless medium via an antenna, which further receives the data and transmits the data to the processor 51.

The processor 51 is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And the memory 52 may be used to store data used by the processor 51 in performing operations.

The present invention further provides a computer-readable storage medium storing a computer program. The computer program realizes the above-described method embodiments when executed by a processor.

It can be found that, with the above scheme, the PCIE lanes of the high-speed serial computer expansion bus standard of the computer chip may be respectively connected to different physical network interface chips, and each packet coding packet id associated with the physical network interface chip may be configured to have different values through the general input/output port GPIO, and each packet coding packet id configured to have different values may be maximally managed through only one simplified media independent interface RMII lane based on the baseboard management controller BMC, so that control access to 8 different packet codes can be completed through only one simplified media independent interface lane.

Furthermore, in the above scheme, a mode of configuring the packet coding packegeids by using an input/output IO interface of the complex programmable logic device may be adopted, and each packet coding packegeid associated with the physical network port chip is configured to have a different value through a general input/output port GPIO.

Further, in the above scheme, a mode of connecting 8 ports, namely the first port, the second port, the third port to the eighth port, in series may be adopted, and based on that the BMC performs maximum management on each packet code packet id configured to have different values only through one simplified media independent interface RMII channel, such an advantage is that control access to 8 different packet codes can be completed only through one simplified media independent interface channel.

Furthermore, the scheme can maintain each packet code packageID which is maximally managed according to the preset time frequency, and the advantage is that the control access to 8 different packet codes can be continuously and stably completed only through one simplified media independent interface channel.

In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.