Semiconductor device for battery protection

文档序号：1955615 发布日期：2021-12-10 浏览：32次中文

阅读说明：本技术 用于电池保护的半导体器件 (Semiconductor device for battery protection ) 是由不公告发明人于 2021-09-09 设计创作，主要内容包括：本公开提供一种用于电池保护的半导体器件,包括：第一元胞区,第一元胞区形成有第一场效应晶体管；第二元胞区,第二元胞区形成有第二场效应晶体管,第二场效应晶体管作为第一开关,第一开关用于控制第一场效应晶体管的源极与衬底之间的连通与断开；以及第三元胞区,第三元胞区形成有第二开关,第二开关用于控制第一场效应晶体管的栅极与漏极之间的连通与断开；其中,第二元胞区以及第三元胞区形成在所述第一元胞区上,且第二元胞区与第三元胞区相邻地形成。(The present disclosure provides a semiconductor device for battery protection, including: a first cell region having a first field effect transistor formed therein; the second cell area is provided with a second field effect transistor which is used as a first switch, and the first switch is used for controlling the connection and disconnection between the source electrode of the first field effect transistor and the substrate; the third cell area is provided with a second switch, and the second switch is used for controlling the connection and disconnection between the grid electrode and the drain electrode of the first field effect transistor; the second cell area and the third cell area are formed on the first cell area, and the second cell area and the third cell area are formed adjacent to each other.)

1. A semiconductor device, comprising:

a first cell region formed with a first field effect transistor;

the second cell area is provided with a second field effect transistor which is used as a first switch, and the first switch is used for controlling the connection and disconnection between the source electrode of the first field effect transistor and the substrate; and

a third cell region, wherein a second switch is formed in the third cell region, and the second switch is used for controlling connection and disconnection between a grid electrode and a drain electrode of the first field effect transistor;

wherein a second cell region and a third cell region are formed on the first cell region, and the second cell region is formed adjacent to the third cell region.

2. The semiconductor device according to claim 1, wherein the first cell region comprises a source region, a substrate electrode region, a gate region, and a drain region, wherein a first parasitic diode and a second parasitic diode are formed in the first cell region, the first parasitic diode and the second parasitic diode are formed in an anti-series structure, the first parasitic diode and the second parasitic diode are formed between the source region and the drain region, and a junction region of the first parasitic diode and the second parasitic diode formed in the first cell region is formed at least on the substrate electrode region.

3. The semiconductor device of claim 2, wherein the second cell region comprises a source region, a substrate electrode region, a gate region, and a drain region, and wherein the second cell region forms the second field effect transistor having a fourth parasitic diode formed between the source region and the substrate electrode region of the second field effect transistor.

4. The semiconductor device as claimed in claim 3, wherein the gate region of the second cell region is disposed corresponding to the gate region of the first cell region, the source region of the second cell region is disposed corresponding to the source region of the first cell region, the substrate electrode region of the second cell region is disposed corresponding to the substrate electrode region of the first cell region, and the drain region of the second cell region is disposed corresponding to the drain region of the first cell region.

5. The semiconductor device of claim 2, wherein the third cell region comprises a gate region and a drain region, and wherein a third parasitic diode and a resistor are formed between the drain region and the gate region of the third cell region, the third parasitic diode and the resistor forming a series structure.

6. The semiconductor device as claimed in claim 5, wherein the gate region of the third cell region is disposed corresponding to the gate region of the first cell region, and the drain region of the third cell region is disposed corresponding to the drain region of the first cell region.

7. The semiconductor device according to claim 1 or 2, wherein the first field effect transistor is an NMOS transistor;

the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type highly doped region, a P-type well region, an N-type well region and a second N-type highly doped region are formed in the N-type drift region, the P-type well region is formed with a P-type highly doped region, the N-type well region is formed between the P-type well region and the second N-type highly doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high-doping region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doped region, a first isolation medium is formed between at least one part of the gate region and at least one part of the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doped region, a second isolation medium is formed between the P-type high-doping area and the second N-type high-doping area;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doped region, a second isolation medium is formed between the P-type high-doping area and the second N-type high-doping area, and a first isolation medium is formed between at least one part of the gate area and at least one part of the second N-type high-doping area;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the third medium region and is isolated from the second N-type high-doped region, the N-type well region, the P-type well region and the N-type drift region at least through the third medium region, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the third medium region and is isolated from the second N-type high-doped region, the N-type well region, the P-type well region and the N-type drift region at least through the third medium region, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region, and a second isolation dielectric is formed between the P-type high-doping region and the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, one part of the gate region is formed in the medium layer, the other part of the gate region is formed in the third medium region, and at least passes through the third medium region, and the other part of the gate region and the second N-type high-doped region, The N-type well region, the P-type well region and the N-type drift region are isolated, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, one part of the gate region is formed in the medium layer, the other part of the gate region is formed in the third medium region, and at least passes through the third medium region, and the other part of the gate region and the second N-type high-doped region, The N-type well region, the P-type well region and the N-type drift region are isolated, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region, and a second isolation medium is formed between the P-type high-doping region and the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor;

the first unit cell region comprises a source region, a substrate electrode region, a gate region and a pole region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is of a separated structure, the gate region is formed in the third medium region, at least through the third medium region, the gate region and the second N-type high-doped region, The N-type well region, the P-type well region and the N-type drift region are isolated, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region;

optionally, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is of a separated structure, the gate region is formed in the third medium region at least through the third medium region, the gate region and the second N-type high-doped region, The N-type well region, the P-type well region and the N-type drift region are isolated, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region, and a second isolation medium is formed between the P-type high-doping region and the second N-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high doping region is formed on the drain region, a P-type drift region is formed on the first P-type highly doped region, an N-type well region, a P-type well region and a second P-type highly doped region are formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type highly doped region, a dielectric layer is formed on the P-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the N-type high-doping region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doped region is formed on the drain region, a P-type drift region is formed on the first P-type high-doped region, an N-type well region, a P-type well region and a second P-type high-doped region are formed in the P-type drift region, an N-type high-doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doped region, a dielectric layer is formed on the P-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the N-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doped region, a first isolation medium is formed between at least one part of the gate region and at least one part of the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doped region is formed on the drain region, a P-type drift region is formed on the first P-type high-doped region, an N-type well region, a P-type well region and a second P-type high-doped region are formed in the P-type drift region, an N-type high-doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doped region, a dielectric layer is formed on the P-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the N-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doped region, a second isolation medium is formed between the N-type high-doping area and the second P-type high-doping area;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doped region is formed on the drain region, a P-type drift region is formed on the first P-type high-doped region, an N-type well region, a P-type well region and a second P-type high-doped region are formed in the P-type drift region, an N-type high-doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doped region, a dielectric layer is formed on the P-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the N-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doped region, a second isolation medium is formed between the N-type high-doping area and the second P-type high-doping area, and a first isolation medium is formed between at least one part of the gate area and at least one part of the second P-type high-doping area;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doped region is formed on the drain region, a P-type drift region is formed on the first P-type high-doped region, an N-type well region, a P-type well region, a third medium region and a second P-type high-doped region are formed in the P-type drift region, an N-type high-doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doped region, a medium layer is formed on the P-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the N-type high-doped region, the gate region is formed in the third medium region and is isolated from the second P-type high-doped region, the P-type well region, the N-type well region and the P-type drift region at least through the third medium region, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doped region is formed on the drain region, a P-type drift region is formed on the first P-type high-doped region, an N-type well region, a P-type well region, a third medium region and a second P-type high-doped region are formed in the P-type drift region, an N-type high-doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doped region, a medium layer is formed on the P-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the N-type high-doped region, the gate region is formed in the third medium region and is isolated from the second P-type high-doped region, the P-type well region, the N-type well region and the P-type drift region at least through the third medium region, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region, and a second isolation dielectric is formed between the N-type high-doping region and the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type highly doped region is formed on the drain region, a P-type drift region is formed on the first P-type highly doped region, an N-type well region, a P-type well region, a third medium region and a second P-type highly doped region are formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type highly doped region, a medium layer is formed on the P-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the N-type highly doped region, one part of the gate region is formed in the medium layer, the other part of the gate region is formed in the third medium region, at least through the third medium region, the other part of the gate region and the second P-type highly doped region, The P-type well region, the N-type well region and the P-type drift region are isolated, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type highly doped region is formed on the drain region, a P-type drift region is formed on the first P-type highly doped region, an N-type well region, a P-type well region, a third medium region and a second P-type highly doped region are formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type highly doped region, a medium layer is formed on the P-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the N-type highly doped region, one part of the gate region is formed in the medium layer, the other part of the gate region is formed in the third medium region, at least through the third medium region, the other part of the gate region and the second P-type highly doped region, The P-type well region, the N-type well region and the P-type drift region are isolated, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region, and a second isolation medium is formed between the N-type high-doping region and the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doping region is formed on the drain region, a P-type drift region is formed on the first P-type high-doping region, an N-type well region, a P-type well region, a third medium region and a second P-type high-doping region are formed in the P-type drift region, an N-type high-doping region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doping region, a medium layer is formed on the P-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the N-type high-doping region, the gate region is of a separated structure, the gate region is formed in the third medium region, at least through the third medium region, the gate region and the second P-type high-doping region, The P-type well region, the N-type well region and the P-type drift region are isolated, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region;

optionally, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type high-doping region is formed on the drain region, a P-type drift region is formed on the first P-type high-doping region, an N-type well region, a P-type well region, a third medium region and a second P-type high-doping region are formed in the P-type drift region, an N-type high-doping region is formed in the N-type well region, the P-type well region is formed between the N-type well region and the second P-type high-doping region, a medium layer is formed on the P-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the N-type high-doping region, the gate region is of a separated structure, the gate region is formed in the third medium region, at least through the third medium region, the gate region and the second P-type high-doping region, The P-type well region, the N-type well region and the P-type drift region are isolated, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region, and a second isolation medium is formed between the N-type high-doping region and the second P-type high-doping region;

optionally, the second field effect transistor is an NMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a first P-type well region, a second P-type well region, an N-type well region, a P-type high-doped region, a second N-type high-doped region and a third N-type high-doped region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the second N-type high-doped region is formed in the N-type well region, the third N-type high-doped region and the P-type high-doped region are formed in the second P-type well region and are adjacent to each other, and the second N-type high-doped region and the third N-type high-doped region are isolated through PN junctions; the second cell area also comprises a dielectric layer, the substrate electrode area is formed in the dielectric layer, and the substrate electrode area is contacted with the third N-type high-doping area and the P-type high-doping area; the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region; the second cell region further comprises an isolation medium, and the isolation medium is formed between the medium layer and the first P-type well region;

optionally, the second field effect transistor is an NMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type highly doped region is formed on the drain region, an N-type drift region is formed on the first N-type highly doped region, a first P-type well region, a second P-type well region, an N-type well region, a first P-type highly doped region, a second N-type highly doped region, a third N-type highly doped region and a fourth N-type highly doped region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the second N-type highly doped region is formed in the N-type well region, the third N-type highly doped region, the fourth N-type highly doped region, the first P-type highly doped region and the second P-type highly doped region are formed in the second P-type well region, and the first P-type highly doped region and the third N-type highly doped region are adjacently arranged, the second P-type high-doping area and the fourth N-type high-doping area are adjacently arranged, a medium area is formed between the third N-type high-doping area and the fourth N-type high-doping area, the gate area is formed in the medium area, a medium area is formed between the second N-type high-doping area and the first P-type high-doping area, a metal floating area is formed in the medium area, a medium area is formed on one side, opposite to the fourth N-type high-doping area, of the second P-type high-doping area, and a metal floating area is formed in the medium area; the second cell region further comprises a dielectric layer, the substrate electrode region is formed in the dielectric layer, one end region of the substrate electrode region is in contact with the third N-type high-doping region and the first P-type high-doping region, and the other end region of the substrate electrode region is in contact with the fourth N-type high-doping region and the second P-type high-doping region; the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region;

8. The semiconductor device according to claim 7, wherein the second field effect transistor is a PMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first P-type high-doping region is formed on the drain region, a P-type drift region is formed on the first P-type high-doping region, a first N-type well region, a second N-type well region, a P-type well region, an N-type high-doping region, a second P-type high-doping region and a third P-type high-doping region are formed in the P-type drift region, the P-type well region is formed between the first N-type well region and the second N-type well region, the second P-type high-doping region is formed in the P-type well region, the third P-type high-doping region and the N-type high-doping region are formed in the second N-type well region and are adjacent to each other, and the second P-type high-doping region and the third P-type high-doping region are isolated through a PN junction; the second cell area also comprises a dielectric layer, the substrate electrode area is formed in the dielectric layer, and the substrate electrode area is contacted with the third P-type high-doping area and the N-type high-doping area; the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region; the second cell region further comprises an isolation medium, and the isolation medium is formed between the medium layer and the first N-type well region;

optionally, the second field effect transistor is a PMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first P-type highly doped region is formed on the drain region, a P-type drift region is formed on the first P-type highly doped region, a first N-type well region, a second N-type well region, a P-type well region, a first N-type highly doped region, a second P-type highly doped region, a third P-type highly doped region and a fourth P-type highly doped region are formed in the P-type drift region, the P-type well region is formed between the first N-type well region and the second N-type well region, the second P-type highly doped region is formed in the P-type well region, the third P-type highly doped region, the fourth P-type highly doped region, the first N-type highly doped region and the second N-type highly doped region are formed in the second N-type well region, the first N-type highly doped region and the third P-type highly doped region are adjacently arranged, the second N-type high-doping area and the fourth P-type high-doping area are adjacently arranged, a medium area is formed between the third P-type high-doping area and the fourth P-type high-doping area, the gate area is formed in the medium area, a medium area is formed between the second P-type high-doping area and the first N-type high-doping area, a metal floating area is formed in the medium area, a medium area is formed on one side, opposite to the fourth P-type high-doping area, of the second N-type high-doping area, and a metal floating area is formed in the medium area; the second cell region further comprises a dielectric layer, the substrate electrode region is formed in the dielectric layer, one end region of the substrate electrode region is in contact with the third P-type high-doping region and the first N-type high-doping region, and the other end region of the substrate electrode region is in contact with the fourth P-type high-doping region and the second N-type high-doping region; the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second P-type high-doping region;

optionally, the third cell region includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, a dielectric layer is formed on the N-type drift region, the gate region is formed in the dielectric layer, and the gate region is formed on the P-type highly doped region;

optionally, the third cell region includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, a dielectric layer is formed on the N-type drift region, the gate region is formed in the dielectric layer, the gate region is formed on the P-type highly doped region, the third cell region further includes an isolation dielectric, and the isolation dielectric is formed in the N-type drift region and on two sides of the P-type well region;

optionally, the third cell region includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the N-type well region and the second P-type well region, the gate region is formed in the dielectric layer, the gate region is formed on the P-type highly doped region, the second P-type well region is located between the first P-type well region and the dielectric layer, and a lateral extension size of the first P-type well region is smaller than a lateral extension size of the N-type drift region;

optionally, the third cell region includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed at least on the N-type well region and the second P-type well region, the gate region is formed in the dielectric layer, the gate region is formed on the P-type highly doped region, the second P-type well region is located between the first P-type well region and the dielectric layer, a lateral extension size of the first P-type well region is smaller than a lateral extension size of the N-type drift region, the third cell region further includes an isolation medium, the isolation medium is arranged on one common side of the first P-type well region, the N-type well region and the second P-type well region;

optionally, the third cell region includes a gate region and a drain region, a P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a dielectric layer is formed on the P-type drift region, the gate region is formed in the dielectric layer, and the gate region is formed on the N-type highly doped region;

optionally, the third cell region includes a gate region and a drain region, a P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, an N-type well region is formed in the P-type drift region, an N-type highly doped region is formed in the N-type well region, a dielectric layer is formed on the P-type drift region, the gate region is formed in the dielectric layer, the gate region is formed on the N-type highly doped region, the third cell region further includes an isolation dielectric, and the isolation dielectric is formed in the P-type drift region and on two sides of the N-type well region.

9. The semiconductor device according to any one of claims 1 to 8, wherein the third cell region includes a gate region and a drain region, a P-type highly doped region is formed on the drain region, a P-type drift region is formed on the P-type highly doped region, a first N-type well region and a second N-type well region are formed in the P-type drift region, a P-type well region is formed between the first N-type well region and the second N-type well region, an N-type high-doped region is formed in the second N-type well region, a dielectric layer is formed on the P-type well region and the second N-type well region, the gate region is formed in the dielectric layer, the gate region is formed on the N-type high-doping region, the second N-type well region is positioned between the first N-type well region and the dielectric layer, the lateral extension size of the first N-type well region is smaller than that of the P-type drift region.

10. The semiconductor device according to any one of claims 1 to 9, wherein the third cell region includes a gate region and a drain region, the drain region has a P-type highly doped region formed thereon, the P-type highly doped region has a P-type drift region formed thereon, the P-type drift region has a first N-type well region and a second N-type well region formed therein, a P-type well region is formed between the first N-type well region and the second N-type well region, an N-type highly doped region is formed therein, a dielectric layer is formed on at least the P-type well region and the second N-type well region, the gate region is formed in the dielectric layer, and the gate region is formed on the N-type highly doped region, the second N-type well region is located between the first N-type well region and the dielectric layer, a lateral extension dimension of the first N-type well region is smaller than a lateral extension dimension of the P-type drift region, the third unit cell region further comprises an isolation medium, and the isolation medium is arranged on one common side of the first N-type well region, the P-type well region and the second N-type well region.

Technical Field

The present disclosure belongs to the field of semiconductor technology, and particularly relates to a semiconductor device for battery protection.

Background

In the battery system, overcharge and overdischarge of the battery not only reduce the lifespan of the battery, but also cause safety accidents of explosion and fire when serious. The battery is, for example, a lithium battery pack or the like.

In the prior art, a device for protecting a battery in a battery system often cannot completely turn off a charging current or a discharging circuit under the condition of overcharge or overdischarge of the battery, so that potential safety hazards exist.

Disclosure of Invention

In order to solve one of the above technical problems, the present disclosure provides a semiconductor device for battery protection.

The semiconductor device for battery protection of the present disclosure is realized by the following technical solutions.

The present disclosure provides a semiconductor device including: a first cell region having a first field effect transistor formed therein; the second cell area is provided with a second field effect transistor which is used as a first switch, and the first switch is used for controlling the connection and disconnection between the source electrode of the first field effect transistor and the substrate; the third cell area is provided with a second switch, and the second switch is used for controlling the connection and disconnection between the grid electrode and the drain electrode of the first field effect transistor; the second cell area and the third cell area are formed on the first cell area, and the second cell area and the third cell area are formed adjacently.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region includes a source region, a substrate electrode region, a gate region, and a drain region, the first cell region has a first parasitic diode and a second parasitic diode formed therein, the first parasitic diode and the second parasitic diode constitute an anti-series structure, the first parasitic diode and the second parasitic diode are formed between the source region and the drain region, and a junction region of the first parasitic diode and the second parasitic diode formed in the first cell region is formed at least on the substrate electrode region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second cell region includes a source region, a substrate electrode region, a gate region, and a drain region, the second field effect transistor formed by the second cell region has a fourth parasitic diode formed between the source region and the substrate electrode region of the second field effect transistor.

According to the semiconductor device of at least one embodiment of the present disclosure, the gate region of the second cell region is disposed corresponding to the gate region of the first cell region, the source region of the second cell region is disposed corresponding to the source region of the first cell region, the substrate electrode region of the second cell region is disposed corresponding to the substrate electrode region of the first cell region, and the drain region of the second cell region is disposed corresponding to the drain region of the first cell region.

According to the semiconductor device of at least one embodiment of the present disclosure, the third unit cell region includes a gate region and a drain region, a third parasitic diode and a resistor are formed between the drain region and the gate region of the third unit cell region, and the third parasitic diode and the resistor form a series structure.

According to the semiconductor device of at least one embodiment of the present disclosure, the gate region of the third cell region is disposed corresponding to the gate region of the first cell region, and the drain region of the third cell region is disposed corresponding to the drain region of the first cell region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, an N-type well region is formed between the P-type well region and the second N-type high-doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high doping region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region, and a first isolation dielectric is formed between at least one part of the gate region and at least one part of the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doped region, and a second isolation medium is formed between the P-type high-doped region and the second N-type high-doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, an N-type well region is formed between the P-type well region and the second N-type high-doped region, a dielectric layer is formed on the N-type drift region, the substrate electrode region is formed in the dielectric layer, the substrate electrode region is arranged on the P-type high doping region, the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, at least one part of the source region penetrates through the dielectric layer to be contacted with the second N-type high doping region, a second isolation dielectric is formed between the P-type high doping region and the second N-type high doping region, and a first isolation medium is formed between at least one part of the gate region and at least one part of the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, and a substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doping region, the gate region is formed in the third medium region, the gate region is isolated from the second N-type high-doping region, the N-type well region, the P-type well region and the N-type drift region at least through the third medium region, the source region is formed on the medium layer, and at least one part of the source region penetrates through the medium layer to be in contact with the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is formed in the third medium region and is at least isolated from the second N-type high-doped region, the N-type well region, the P-type well region and the N-type drift region through the third medium region, the source region is formed on the medium layer, and at least one part of the source region passes through the medium layer to be contacted with the second N-type high-doped region, and a second isolation medium is formed between the P-type high-doping area and the second N-type high-doping area.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, an N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, one part of the gate region is formed in the medium layer, the other part of the gate region is formed in the third medium region and is isolated from the second N-type high-doped region, the N-type well region, the P-type well region and the N-type drift region at least through the third medium region, the other part of the gate region is isolated from the second N-type high-doped region, the P-type well region and the N-type drift region, the source region is formed on the medium layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, an N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, one part of the gate region is formed in the medium layer, the other part of the gate region is formed in the third medium region and is isolated from the second N-type high-doped region, the N-type well region, the P-type well region and the N-type drift region at least through the third medium region, the other part of the gate region is isolated from the second N-type high-doped region, the P-type well region and the N-type drift region, the source region is formed on the medium layer, at least one part of the source region penetrates through the dielectric layer to be contacted with the second N-type high-doping region, and a second isolation dielectric is formed between the P-type high-doping region and the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, the N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, and a substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high doping region, the gate region is of a separation structure and is formed in the third medium region, the gate region is isolated from the second N-type high-doping region, the N-type well region, the P-type well region and the N-type drift region at least through the third dielectric region, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doped region is formed on the drain region, an N-type drift region is formed on the first N-type high-doped region, a P-type well region, an N-type well region, a third medium region and a second N-type high-doped region are formed in the N-type drift region, a P-type high-doped region is formed in the P-type well region, an N-type well region is formed between the P-type well region and the second N-type high-doped region, a medium layer is formed on the N-type drift region, the substrate electrode region is formed in the medium layer, the substrate electrode region is arranged on the P-type high-doped region, the gate region is of a separated structure, the gate region is formed in the third medium region and at least passes through the third medium region, the gate region is isolated from the second N-type high-doped region, the N-type well region, the P-type well region and the N-type drift region, the source region is formed on the medium layer, and at least one part of the source region passes through the medium layer to be contacted with the second N-type high-doped region, and a second isolation medium is formed between the P-type high-doping area and the second N-type high-doping area.

According to the semiconductor device of at least one embodiment of the present disclosure, the second field effect transistor is an NMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a drain region, a first N-type highly doped region is formed on the drain region, an N-type drift region is formed on the first N-type highly doped region, a first P-type well region, a second P-type well region, an N-type well region, a first P-type highly doped region, a second N-type highly doped region, a third N-type highly doped region and a fourth N-type highly doped region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the second N-type highly doped region is formed in the N-type well region, the third N-type highly doped region, the fourth N-type highly doped region, the first P-type highly doped region and the second P-type highly doped region are formed in the second P-type well region, the first P-type highly doped region and the third N-type highly doped region are adjacently arranged, and the second P-type highly doped region and the fourth N-type highly doped region are adjacently arranged, a dielectric region is formed between the third N-type high-doping region and the fourth N-type high-doping region, a gate region is formed in the dielectric region, a dielectric region is formed between the second N-type high-doping region and the first P-type high-doping region, a metal floating region is formed in the dielectric region, a dielectric region is formed on one side, opposite to the fourth N-type high-doping region, of the second P-type high-doping region, and a metal floating region is formed in the dielectric region; the second cell region also comprises a dielectric layer, the substrate electrode region is formed in the dielectric layer, one end part region of the substrate electrode region is contacted with the third N-type high-doping region and the first P-type high-doping region, and the other end part region of the substrate electrode region is contacted with the fourth N-type high-doping region and the second P-type high-doping region; the source region is formed on the dielectric layer, and at least a part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the N-type well region and the second P-type well region, the gate region is formed in the dielectric layer, the gate region is formed on the P-type highly doped region, the second P-type well region is located between the first P-type well region and the dielectric layer, and the lateral extension dimension of the first P-type well region is smaller than the lateral extension dimension of the N-type drift region.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on at least the N-type well region and the second P-type well region, the gate region is formed in the dielectric layer, and the gate region is formed on the P-type high-doping region, the second P-type well region is positioned between the first P-type well region and the dielectric layer, the transverse extension dimension of the first P-type well region is smaller than that of the N-type drift region, the third cell region further comprises an isolation medium, and the isolation medium is arranged on one common side of the first P-type well region, the N-type well region and the second P-type well region.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic circuit diagram of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 2 is a schematic view of the overall layout structure of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 3 is a schematic circuit configuration diagram of a first cell region (MN1) of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 4 is a schematic circuit diagram corresponding to the second cell region (MNB) of the semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural diagram of a first cell region of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 6 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 7 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 8 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

The left and right views of fig. 9 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 5.

The left and right views of fig. 10 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 6.

Fig. 11 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 12 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 13 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 14 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

The left and right views of fig. 15 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 11.

The left and right views of fig. 16 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 12.

Fig. 17 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 18 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

The left and right views of fig. 19 are schematic cross-sectional views of two different positions of the structure shown in fig. 17 (designed as a T-shaped three-dimensional trench-gate structure).

Fig. 20 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 21 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

The left and right views of fig. 22 are schematic cross-sectional views of two different locations of the structure shown in fig. 20 (designed as a three-dimensional in-vivo thick-oxide trench gate structure).

Fig. 23 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 24 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

The left and right views of fig. 25 are schematic cross-sectional views of two different locations of the structure shown in fig. 23 (designed as a three-dimensional split trench-gate structure).

Fig. 26 is a schematic structural view of a second cell region of the semiconductor device for battery protection according to one embodiment of the present disclosure.

Fig. 27 is a schematic structural view of a second cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

The left and right views of fig. 28 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 27.

Fig. 29 is a schematic structural view of a second cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 30 is a schematic structural view of a third cell region of the semiconductor device for battery protection according to one embodiment of the present disclosure.

Fig. 31 is a schematic structural view of a third cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 32 is a schematic structural view of a third cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 33 is a schematic structural view of a third cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

As shown in fig. 1 and 2, a semiconductor device of the present disclosure includes: a first cell region 100, the first cell region 100 having a first field effect transistor formed therein; a second cell area 200, wherein a second field effect transistor is formed in the second cell area 200, and the second field effect transistor is used as a first switch for controlling the connection and disconnection between the source electrode of the first field effect transistor and the substrate; and a third cell area 300, the third cell area 300 being formed with a second switch for controlling connection and disconnection between the gate and the drain of the first field effect transistor; the second cell area 200 and the third cell area 300 are formed on the first cell area 100, and the second cell area 200 and the third cell area 300 are formed adjacent to each other.

Fig. 5 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 1 and 5, the first field effect transistor (MN1) of the semiconductor device is an NMOS transistor; the first unit cell region 100 includes a source region 101(S), a substrate electrode region 102(B), a gate region 104(G), and a drain region 111(D), the drain region 111(D) is formed with a first N-type highly doped region 110(N +), the first N-type highly doped region 110(N +) is formed with an N-type drift region 109(ND), the N-type drift region 109(ND) is formed with a P-type well region 106(PW), an N-type well region 108(N), and a second N-type highly doped region 107(N +), the P-type well region 106(PW) is formed with a P-type highly doped region 105(P +), the N-type well region 108(N) is formed between the P-type well region 106(PW) and the second N-type highly doped region 107(N +), the N-type drift region 109(ND) is formed with a dielectric layer 103, the substrate electrode region 102(B) is formed in the dielectric layer 103, and the substrate electrode region 102(B) is disposed on the P-type highly doped region 105(P +), the gate region 104(G) is formed in the dielectric layer 103, the source region 101(S) is formed on the dielectric layer 103, and at least a portion of the source region 103(S) is in contact with the second N-type highly doped region 107(N +) through the dielectric layer 103.

The first cell region 100 shown in fig. 5 has a symmetrical structure in the lateral direction.

The doping concentration of the N + region is greater than that of the N region, and the doping concentration of the P + region is greater than that of the PW region.

The source region 101 may be made of a metal material, the dielectric layer 103 is an oxide layer, the substrate electrode region 102 is made of a metal material, the gate region 104 may be made of polysilicon, the P-type highly doped region 105 is made of P-type doped silicon, the P-type well region 106 is made of P-type doped silicon, the second N-type highly doped region 107 and the first N-type highly doped region 110 are made of N-type doped silicon, the N-type well region 108 is made of N-type doped silicon, the N-type drift region 109 is made of N-type doped silicon, and the drain region 111 may be made of a metal material.

As shown in fig. 5, the N region and the PW region form a parasitic diode D2 (also shown as D2 in fig. 1), the PW region and the ND region form a parasitic diode D1 (also shown as D1 in fig. 1), and the P + region and the N + region are isolated from each other by a PN junction.

Fig. 6 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The first field effect transistor is an NMOS transistor; the first unit cell region 100 includes a source region 101(S), a substrate electrode region 102(B), a gate region 104(G), and a drain region 111(D), the drain region 111(D) is formed with a first N-type highly doped region 110(N +), the first N-type highly doped region 110(N +) is formed with an N-type drift region 109(ND), the N-type drift region 109(ND) is formed with a P-type well region 106(PW), an N-type well region 108(N), and a second N-type highly doped region 107(P +), the P-type well region 106(PW) is formed with a P-type highly doped region 105(P +), the N-type well region 108(N) is formed between the P-type well region 106(PW) and the second N-type highly doped region 107(P +), the N-type drift region 109(ND) is formed with a dielectric layer 103, the substrate electrode region 102(B) is formed in the dielectric layer 103, and the substrate electrode region 102(B) is disposed on the P-type highly doped region 105(P +), a gate region 104(G) is formed in the dielectric layer 103, a source region 101(S) is formed on the dielectric layer 103, and at least a portion of the source region 103(S) is in contact with the second N-type highly doped region 107(N +) through the dielectric layer 103, and a first isolation dielectric 112 is formed between at least a portion of the gate region 104(G) and at least a portion of the second N-type highly doped region 107(N +).

Similar to the structure shown in fig. 5, the first cell region 100 shown in fig. 6 has a symmetrical structure in the lateral direction.

The first isolation dielectric 112 may be an oxide layer. The G-N voltage resistance is improved by the first isolation medium 112.

Fig. 7 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, the N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, and the substrate electrode region 102 is disposed on the P-type highly doped region 105, the gate region 104 is formed in the dielectric layer 103, the source region 101 is formed on the dielectric layer 103, and at least a portion of the source region 103 contacts the second N-type highly doped region 107 through the dielectric layer 103, and a second isolation dielectric 113 is formed between the P-type highly doped region 105 and the second N-type highly doped region 107.

Similar to the structure shown in fig. 5, the first cell region 100 shown in fig. 7 has a laterally symmetrical structure.

The second isolation dielectric 113 may be an oxide layer, i.e., the P + region is isolated from the N + region by the second isolation dielectric (trench dielectric).

Fig. 8 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, the N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, the substrate electrode region 102 is arranged on the P-type highly doped region 105, the gate region 104 is formed in the dielectric layer 103, the source region 101 is formed on the dielectric layer 103, at least a part of the source region 103 passes through the dielectric layer 103 to contact with the second N-type highly doped region 107, and a second isolation dielectric layer 113 is formed between the P-type highly doped region 105 and the second N-type highly doped region 107, and a first isolation medium 112 is formed between at least a portion of the gate region 104 and at least a portion of the second N-type highly doped region 107.

Similar to the structure shown in fig. 7, the first cell region 100 shown in fig. 8 has a symmetrical structure in the lateral direction. The G-N voltage resistance is improved by the first isolation medium 112.

The left and right views of fig. 9 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 5.

The left and right views of fig. 10 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 6.

Fig. 11 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 12 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 11 and 12, the first field effect transistor is an NMOS transistor; the first unit cell region 100 includes a source region 101(S), a substrate electrode region 102(B), a gate region 104(G), and a drain region 111(D), the drain region 111(D) is formed with a first N-type highly doped region 110(N +), the first N-type highly doped region 110(N +) is formed with an N-type drift region 109(ND), the N-type drift region 109(ND) is formed with a P-type well region 106(PW), an N-type well region 108(N), a third dielectric region 114, and a second N-type highly doped region 107(N +), the P-type well region 106(PW) is formed with a P-type highly doped region 105(P +), the N-type well region 108(N) is formed between the P-type well region 106(PW) and the second N-type highly doped region 107(N +), the N-type drift region 109(ND) is formed with a dielectric layer 103, the substrate electrode region 102(B) is formed in the dielectric layer 103, and the substrate electrode region 102(B) is disposed on the P-type highly doped region 105(P +), the gate region 104(G) is formed in the third dielectric region 114, the gate region 104(G) is isolated from the second N-type highly doped region 107(N +), the N-type well region 108(N), the P-type well region 106(PW), and the N-type drift region 109(ND) at least by the third dielectric region 114, the source region 101(S) is formed on the dielectric layer 103, and at least a portion of the source region 103(S) contacts the second N-type highly doped region 107(N +) through the dielectric layer 103.

In fig. 11, there is an N region between the N + region and the third dielectric region 114, and in fig. 12, there is no N region between the N + region and the third dielectric region 114.

The gate region in the first cell region shown in fig. 11 and 12 is a trench gate.

The first cell region 100 shown in fig. 11 and 12 has a symmetrical structure in the lateral direction.

As shown in fig. 11 and 12, the N region and the PW region form a parasitic diode D2 (also shown as D2 in fig. 1), the PW region and the ND region form a parasitic diode D1 (also shown as D1 in fig. 1), and the P + region and the N + region are isolated from each other by a PN junction.

Fig. 13 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 14 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 13 and 14, the first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108, a third dielectric region 114 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, an N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, the substrate electrode region 102 is arranged on the P-type highly doped region 105, the gate region 104 is formed in the third dielectric region 114, and the gate region 104 is isolated from the second N-type highly doped region 107, the N-type well region 108, the P-type drift region 106 and the N-type drift region 109 at least by the third dielectric region 114, the source region 101 is formed on the dielectric layer 103, and at least a portion of the source region 103 contacts the second N-type highly doped region 107 through the dielectric layer 103, and a second isolation dielectric 113 is formed between the P-type highly doped region 105 and the second N-type highly doped region 107.

In fig. 13, there is an N region between the N + region and the third dielectric region 114, and in fig. 14, there is no N region between the N + region and the third dielectric region 114.

The gate region in the first cell region 100 shown in fig. 13 and 14 is a trench gate.

The first cell region 100 shown in fig. 13 and 14 has a symmetrical structure in the lateral direction.

In fig. 13 and 14, the P + region and the N + region are isolated by a second isolation dielectric 113 (trench dielectric).

The left and right views of fig. 15 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 11.

The left and right views of fig. 16 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 12.

Fig. 17 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 17, the first field effect transistor is an NMOS transistor; the first unit cell region 100 includes a source region 101(S), a substrate electrode region 102(B), a gate region 104(G), and a drain region 111(D), the drain region 111(D) is formed with a first N-type highly doped region 110(N +), the first N-type highly doped region 110(N +) is formed with an N-type drift region 109(ND), the N-type drift region 109(ND) is formed with a P-type well region 106(PW), an N-type well region 108(N), a third dielectric region 114, and a second N-type highly doped region 107(N +), the P-type well region 106(PW) is formed with a P-type highly doped region 105(P +), the N-type well region 108(N) is formed between the P-type well region 106(PW) and the second N-type highly doped region 107(N +), the N-type drift region 109(ND) is formed with a dielectric layer 103, the substrate electrode region 102(B) is formed in the dielectric layer 103, and the substrate electrode region 102(B) is disposed on the P-type highly doped region 105(P +), a portion of the gate region 104(G) is formed in the dielectric layer 103, another portion of the gate region 104(G) is formed in the third dielectric region 114, the other portion of the gate region 104(G) is isolated from the second N-type highly doped region 107(N +), the N-type well region 108(N), the P-type well region 106(PW), and the N-type drift region 109(NW) at least through the third dielectric region 114, the source region 101(S) is formed on the dielectric layer 103, and at least a portion of the source region 103(S) contacts the second N-type highly doped region 107(N +) through the dielectric layer 103.

The gate region 104 is a T-shaped trench gate.

Fig. 17 shows the first cell region 100 as a symmetrical structure in the lateral direction.

In fig. 17, the N region and the PW region form a parasitic diode D2 (D2 is shown in fig. 1), the PW region and the ND region form a parasitic diode D1 (D1 is shown in fig. 1), and the P + region and the N + region are isolated from each other by a PN junction.

Fig. 18 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 18, the first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108, a third dielectric region 114 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, the N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, the substrate electrode region 102 is arranged on the P-type highly doped region 105, a part of the gate region 104 is formed in the dielectric layer 103, another part of the gate region 104 is formed in the third dielectric region 114, and at least through the third dielectric region 114, another part of the gate region 104 and the second N-type highly doped region 107, The N-well 108, the P-well 106 and the N-drift 109 are isolated, the source region 101 is formed on the dielectric layer 103, at least a portion of the source region 103 contacts the second N-type highly doped region 107 through the dielectric layer 103, and a second isolation dielectric 113 is formed between the P-type highly doped region 105 and the second N-type highly doped region 107.

Similar to the structure shown in fig. 17, the first cell region 100 shown in fig. 18 has a symmetrical structure in the lateral direction.

In fig. 18, the P + region and the N + region are isolated by a second isolation dielectric 113 (trench dielectric).

The gate region 104 is a T-shaped trench gate.

The left and right views of fig. 19 are schematic cross-sectional views of two different positions of the structure shown in fig. 17 (designed as a T-shaped three-dimensional trench-gate structure).

Fig. 20 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 20, the first field effect transistor is an NMOS transistor; the first unit cell region 100 includes a source region 101(S), a substrate electrode region 102(B), a gate region 104(G), and a drain region 111(D), the drain region 111(D) is formed with a first N-type highly doped region 110(N +), the first N-type highly doped region 110(N +) is formed with an N-type drift region 109(ND), the N-type drift region 109(ND) is formed with a P-type well region 106(PW), an N-type well region 108(N), a third dielectric region 114, and a second N-type highly doped region 107(N +), the P-type well region 106(PW) is formed with a P-type highly doped region 105(P +), the N-type well region 108(N) is formed between the P-type well region 106(PW) and the second N-type highly doped region 107(N +), the N-type drift region 109(ND) is formed with a dielectric layer 103, the substrate electrode region 102(B) is formed in the dielectric layer 103, and the substrate electrode region 102(B) is disposed on the P-type highly doped region 105(P +), the gate region 104(G) is formed in the third dielectric region 114, the gate region 104(G) is isolated from the second N-type highly doped region 107(N +), the N-type well region 108(N), the P-type well region 106(PW), and the N-type drift region 109(ND) at least by the third dielectric region 114, the source region 101(S) is formed on the dielectric layer 103, and at least a portion of the source region 103(S) contacts the second N-type highly doped region 107(N +) through the dielectric layer 103.

Unlike the structure shown in fig. 12, the device structure in fig. 20 employs a thick oxide trench gate in vivo, i.e., the thickness of the third dielectric region 114 (vertical in fig. 20) is greater than, e.g., more than twice, the thickness of the gate region 104.

The first cell region 100 shown in fig. 20 has a symmetrical structure in the lateral direction.

Fig. 21 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 21, the first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108, a third dielectric region 114 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, an N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, the substrate electrode region 102 is arranged on the P-type highly doped region 105, the gate region 104 is formed in the third dielectric region 114, and the gate region 104 is isolated from the second N-type highly doped region 107, the N-type well region 108, the P-type drift region 106 and the N-type drift region 109 at least by the third dielectric region 114, the source region 101 is formed on the dielectric layer 103, and at least a portion of the source region 103 contacts the second N-type highly doped region 107 through the dielectric layer 103, and a second isolation dielectric 113 is formed between the P-type highly doped region 105 and the second N-type highly doped region 107.

There is no N region between the N + region and the third dielectric region 114 in fig. 21.

Unlike the structure shown in fig. 14, the device structure in fig. 21 employs a thick oxide trench gate in vivo, i.e., the thickness of the third dielectric region 114 (vertical in fig. 21) is greater than, e.g., more than twice, the thickness of the gate region 104.

The first cell region 100 shown in fig. 21 has a symmetrical structure in the lateral direction.

In fig. 21, the P + region is isolated from the N + region by a second isolation dielectric 113 (trench dielectric).

Fig. 23 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108, a third dielectric region 114 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, an N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, the substrate electrode region 102 is arranged on the P-type highly doped region 105, the gate region 104 is of a separate structure, the gate region 104 is formed in the third dielectric region 114, and at least the gate region 104 and the second N-type highly doped region 107, the N-type well region 108, the second N-type highly doped region 107, the N-type highly doped region 105, the gate region 108, the second N-type highly doped region 107 and the N-type highly doped region 107, The P-type well region 106 and the N-type drift region 109 are isolated, the source region 101 is formed on the dielectric layer 103, and at least a portion of the source region 103 contacts the second N-type highly doped region 107 through the dielectric layer 103.

Unlike the structure shown in fig. 12, the device structure in fig. 23 employs a split trench gate structure.

The first cell region 100 shown in fig. 23 has a symmetrical structure in the lateral direction.

Fig. 24 is a schematic structural view of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The first field effect transistor is an NMOS transistor; the first unit cell region 100 comprises a source region 101, a substrate electrode region 102, a gate region 104 and a drain region 111, wherein a first N-type highly doped region 110 is formed on the drain region 111, an N-type drift region 109 is formed on the first N-type highly doped region 110, a P-type well region 106, an N-type well region 108, a third dielectric region 114 and a second N-type highly doped region 107 are formed in the N-type drift region 109, a P-type highly doped region 105 is formed in the P-type well region 106, an N-type well region 108 is formed between the P-type well region 106 and the second N-type highly doped region 107, a dielectric layer 103 is formed on the N-type drift region 109, the substrate electrode region 102 is formed in the dielectric layer 103, the substrate electrode region 102 is arranged on the P-type highly doped region 105, the gate region 104 is of a separate structure, the gate region 104 is formed in the third dielectric region 114, and at least the gate region 104 and the second N-type highly doped region 107, the N-type well region 108, the second N-type highly doped region 107, the N-type highly doped region 105, the gate region 108, the second N-type highly doped region 107 and the N-type highly doped region 107, The P-type well region 106 and the N-type drift region 109 are isolated, the source region 101 is formed on the dielectric layer 103, at least a portion of the source region 103 contacts the second N-type highly doped region 107 through the dielectric layer 103, and a second isolation dielectric 113 is formed between the P-type highly doped region 105 and the second N-type highly doped region 107.

There is no N region between the N + region and the third dielectric region 114 in fig. 24.

Unlike the structure shown in fig. 14, the device structure in fig. 24 employs a split trench gate structure.

The first cell region 100 shown in fig. 24 has a symmetrical structure in the lateral direction.

In fig. 24, the P + region and the N + region are isolated by a second isolation dielectric 113 (trench dielectric).

The left and right views of fig. 25 are schematic cross-sectional views of two different locations of the structure shown in fig. 23 (designed as a three-dimensional split trench-gate structure).

In the above embodiments, the first field effect transistors of the semiconductor device are all NMOS transistors, and it should be understood by those skilled in the art that the first field effect transistors may also be designed as PMOS transistors, and if the first field effect transistors are designed as PMOS transistors, the "P type" and the "N type" in the first cell region 100 of the above embodiments are exchanged, so that a plurality of first cell regions forming PMOS transistors of the above embodiments can be formed.

The MN1 circuit structure in fig. 1 and 3 can be implemented by using the first cell region in the above embodiments.

Fig. 26 is a schematic structural diagram of a second cell region 200 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 26, the second field effect transistor of the semiconductor device is an NMOS transistor; the second cell region 200 includes a source region (S), a substrate electrode region (B), a gate region (G) and a drain region (D), the drain region (D) is formed with a first N-type highly doped region (N +), the first N-type highly doped region (N +) is formed with an N-type drift region (ND), the N-type drift region (ND) is formed with a first P-type well region (PW), a second P-type well region, an N-type well region (N), a P-type highly doped region (P +), a second N-type highly doped region (N +), and a third N-type highly doped region (N +), the N-type well region (N) is formed between the first P-type well region (PW) and the second P-type well region, the second N-type highly doped region (N +) is formed in the N-type well region (N +), the third N-type highly doped region (N +) and the P-type highly doped region (P +) are formed in the second P-type well region (P +), the second N-type highly doped region (N +) and the third N-type highly doped region (N +) are isolated through a PN junction; the second cell region 200 further comprises a dielectric layer, a substrate electrode region (B) is formed in the dielectric layer, and the substrate electrode region (B) is in contact with the third N-type highly doped region (N +) and the P-type highly doped region (P +); the gate region (G) is formed in the dielectric layer, the source region (S) is formed on the dielectric layer, and at least a portion of the source region (S) is in contact with the second N-type highly doped region (N +) through the dielectric layer.

In fig. 26, the gate region (G) is a planar gate structure, and the PN structure between the second N-type highly doped region (N +) and the third N-type highly doped region (N +) is a parasitic diode D4 (D4 is shown in fig. 1 and 4).

The gate region (G) of the second cell region 200 corresponds to the gate region (G) of the first cell region 100 in the above embodiment, the source region (S) of the second cell region 200 corresponds to the source region (S) of the first cell region 100, the substrate electrode region (B) of the second cell region 200 corresponds to the substrate electrode region (B) of the first cell region 100, the dielectric layer of the second cell region 200 corresponds to the dielectric layer of the first cell region 100, the N-type drift region of the second cell region 200 corresponds to the N-type drift region of the first cell region 100, the drain region (D) of the second cell region 200 corresponds to the drain region (D) of the first cell region 100, and the first N-type heavily doped region (N +) formed on the drain region of the second cell region 200 corresponds to the first N-type heavily doped region (N +) formed on the drain region of the first cell region 100.

As shown in fig. 2, the second cell region 200 is formed on the first cell region 100.

In fig. 26, the second cell region 200 isolates adjacent second cell regions by PN junctions.

Fig. 27 is a schematic structural view of a second cell region 200 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The second field effect transistor is an NMOS transistor; the second cell region 200 comprises a source region, a substrate electrode region, a gate region and a drain region, wherein a first N-type high-doping region is formed on the drain region, an N-type drift region is formed on the first N-type high-doping region, a first P-type well region, a second P-type well region, an N-type well region, a P-type high-doping region, a second N-type high-doping region and a third N-type high-doping region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the second N-type high-doping region is formed in the N-type well region, the third N-type high-doping region and the P-type high-doping region are formed in the second P-type well region and are formed adjacently, and the second N-type high-doping region and the third N-type high-doping region are isolated through a PN junction; the second cell region 200 further comprises a dielectric layer, a substrate electrode region is formed in the dielectric layer, and the substrate electrode region is in contact with the third N-type high-doping region and the P-type high-doping region; the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least one part of the source region penetrates through the dielectric layer to be in contact with the second N-type high-doping region; the second cell region 200 further includes an isolation dielectric formed between the dielectric layer and the first P-type well region.

In fig. 27, the gate region (G) is a planar gate structure, and a PN structure between the second N-type highly doped region (N +) and the third N-type highly doped region (N +) is a parasitic diode D4 (D4 is shown in fig. 1 and 4).

In fig. 27, the second cell region 200 isolates adjacent second cell regions by an isolation medium.

The left and right views of fig. 28 are schematic cross-sectional views of two different positions of the structure (designed as a three-dimensional structure) shown in fig. 27.

Fig. 29 is a schematic structural view of a second cell region 200 of a semiconductor device for battery protection according to still another embodiment of the present disclosure. The second field effect transistor is an NMOS transistor; the second cell region 200 includes a source region (S), a substrate electrode region (B1), a gate region (G) and a drain region (D), wherein the drain region (D) is formed with a first N-type highly doped region (N +), the first N-type highly doped region (N +) is formed with an N-type drift region (ND), the N-type drift region (ND) is formed with a first P-type well region (PW), a second P-type well region (N), a first P-type highly doped region (P +), a second N-type highly doped region (N +), a third N-type highly doped region (N +), and a fourth N-type highly doped region (N +), the N-type well region (N) is formed between the first P-type well region (P +) and the second P-type well region, the second N-type highly doped region (N +) is formed in the N-type well region (N +), the third N-type highly doped region (N +), the fourth N-type highly doped region (N +), the second N-type well region (N + is formed between the second P-type well region (P) and the fourth P-type well region (N +) A first P-type high-doping area (P +) and a second P-type high-doping area (P +) are formed in a second P-type well region, the first P-type high-doping area (P +) and a third N-type high-doping area (N +) are adjacently arranged, the second P-type high-doping area (P +) and a fourth N-type high-doping area (N +) are adjacently arranged, a medium area is formed between the third N-type high-doping area (N +) and the fourth N-type high-doping area (N +), a gate area (G) is formed in the medium area, a medium area is formed between the second N-type high-doping area (N +) and the first P-type high-doping area (P +), a metal floating area is formed in the medium area, and a medium area is formed on the side of the second P-type high-doping area (P +) opposite to the fourth N-type high-doping area (N +); the second cell region 200 further comprises a dielectric layer, the substrate electrode region (B1) is formed in the dielectric layer, one end region of the substrate electrode region (B1) is in contact with the third N-type highly doped region (N +) and the first P-type highly doped region (P +), and the other end region of the substrate electrode region (B +) is in contact with the fourth N-type highly doped region (N +) and the second P-type highly doped region (P +); the source region (S) is formed on the dielectric layer, and at least a part of the source region (S) passes through the dielectric layer to be in contact with the second N-type highly doped region (N +).

As shown in fig. 29, the N-well and the second P-well form a parasitic diode D4 (D4 is shown in fig. 1 and 4).

In the above embodiments, the second field effect transistors of the semiconductor device are all NMOS transistors, and it should be understood by those skilled in the art that the second field effect transistors may also be designed as PMOS transistors, and if the second field effect transistors are designed as PMOS transistors, the "P type" and the "N type" in the second cell region 200 of the above embodiments are exchanged, so that a plurality of second cell regions forming PMOS transistors of the above embodiments can be formed.

The MNB circuit structures in fig. 1 and 4 can be implemented by using the second cell regions of the above embodiments.

Fig. 30 is a schematic structural view of a third cell region 300 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 30, the third cell region 300 includes a gate region (G) and a drain region (D), an N-type highly doped region (N +) is formed on the drain region (D), an N-type drift region (ND) is formed on the N-type highly doped region (N +), a P-type well region (PW) is formed in the N-type drift region (ND), a P-type highly doped region (P +) is formed in the P-type well region (PW), a dielectric layer is formed on the N-type drift region (ND), the gate region (G) is formed in the dielectric layer, and the gate region (G) is formed on the P-type highly doped region (P +).

The P-well (PW) and the N-drift (ND) form a second switch, i.e., a third parasitic diode D3, i.e., a voltage-withstanding diode D3 (a voltage-withstanding diode D3 is shown in fig. 1), and the N-drift (ND) serves as a resistor R1 in fig. 1. The resistance of R1 can be adjusted by adjusting the thickness and/or doping concentration of the N-type drift region.

Fig. 31 is a schematic structural view of a third cell region 300 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 31, the third cell region 300 includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a P-type well region is formed in the N-type drift region, a P-type highly doped region is formed in the P-type well region, a dielectric layer is formed on the N-type drift region, the gate region is formed in the dielectric layer, and the gate region is formed on the P-type highly doped region, the third cell region 300 further includes an isolation dielectric, and the isolation dielectric is formed in the N-type drift region and on two sides of the P-type well region.

Fig. 32 is a schematic structural view of a third cell region 300 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 32, the third cell region 300 includes a gate region (G) and a drain region (D), an N-type highly doped region (N +) is formed on the drain region (D), an N-type drift region (ND) is formed on the N-type highly doped region (N +), a first P-type well region (PW) and a second P-type well region are formed in the N-type drift region (ND), an N-type well region (N) is formed between the first P-type well region (PW) and the second P-type well region, a P-type highly doped region (P +) is formed in the second P-type well region, a dielectric layer is formed on the N-type well region (N) and the second P-type well region, the gate region (G) is formed in the dielectric layer, and the gate region (G) is formed on the P-type high-doping region (P +), the second P-type well region is positioned between the first P-type well region (PW) and the dielectric layer, and the transverse extension dimension of the first P-type well region (PW) is smaller than that of the N-type drift region (ND).

Those skilled in the art can adjust the resistance of R1 by adjusting the thickness and/or doping concentration of the N-type drift region, and can also adjust the resistance of R1 by adjusting the lateral extension of the PW region relative to the lateral extension of the ND region.

Fig. 33 is a schematic structural view of a third cell region 300 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 33, the third cell region 300 includes a gate region and a drain region, an N-type highly doped region is formed on the drain region, an N-type drift region is formed on the N-type highly doped region, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on at least the N-type well region and the second P-type well region, the gate region is formed in the dielectric layer, and the gate region is formed on the P-type highly doped region, the second P-type well region is located between the first P-type well region and the dielectric layer, the lateral extension dimension of the first P-type well region is smaller than the lateral extension dimension of the N-type drift region, the third cell region 300 further includes an isolation medium, and the isolation medium is disposed on one common side of the first P-type well region, the N-type well region and the second P-type well region.

The gate region (G) of the third cell region 300 is disposed corresponding to the gate region (G) of the first cell region 100 in the above embodiment, the dielectric layer of the third cell region 300 is disposed corresponding to the dielectric layer of the first cell region 100, the N-type drift region of the third cell region 300 is disposed corresponding to the N-type drift region of the first cell region 100, the drain region (D) of the third cell region 300 is disposed corresponding to the drain region (D) of the first cell region 100, and the N-type highly doped region (N +) formed on the drain region of the third cell region 300 is disposed corresponding to the first N-type highly doped region (N +) formed on the drain region of the first cell region 100.

As shown in fig. 2, the third cell region 300 is formed on the first cell region 100.

The D3& R1 circuit structure in fig. 1 can be implemented using the third cell region of the various embodiments described above.

It should be understood by those skilled in the art that the sizes and shapes of the D region, the N + region, the ND region, the PW region, the G region, the S region, the B region, the N + region, the P + region, the dielectric layer, the isolation dielectric, etc. in the above embodiments are all exemplary, and those skilled in the art can appropriately adjust the sizes and shapes, and fall within the protection scope of the present disclosure.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

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