阅读说明：本技术 包括鳍式场效应晶体管的半导体器件 (Semiconductor device including fin field effect transistor ) 是由 李东颖 叶致锴 李宗霖 杨育佳 萧孟轩 于 2017-06-01 设计创作，主要内容包括：本申请的实施例涉及包括FinFET的半导体器件,包括：第一FinFET,包括沿第一方向延伸的第一鳍结构和第一源/漏外延结构；第二FinFET,包括沿第一方向延伸的第二鳍结构和第二源/漏外延结构；第一介电层,分隔第一和第二源/漏外延结构；以及第一源/漏接触件,接触第一源/漏外延结构,其中：第一FinFET仅包括一个鳍结构,第一源/漏外延结构在沿着与第一方向垂直的第二方向的截面中相对于第一鳍结构是不对称的,第一源/漏接触件接触第一源/漏外延结构的顶面和一个侧面并且接触隔离绝缘层,以及第二介电层与第一源/漏外延结构的另一侧面接触。(Embodiments of the present application relate to a semiconductor device including a FinFET, including: a first FinFET including a first fin structure and a first source/drain epitaxial structure extending in a first direction; a second FinFET including a second fin structure and a second source/drain epitaxial structure extending along the first direction; a first dielectric layer separating the first and second source/drain epitaxial structures; and a first source/drain contact contacting the first source/drain epitaxial structure, wherein: the first FinFET includes only one fin structure, the first source/drain epitaxial structure is asymmetric with respect to the first fin structure in a cross section along a second direction perpendicular to the first direction, the first source/drain contact contacts a top surface and one side surface of the first source/drain epitaxial structure and contacts the isolation insulating layer, and the second dielectric layer contacts the other side surface of the first source/drain epitaxial structure.)

1. A semiconductor device comprising a fin field effect transistor (FinFET), comprising:

a first FinFET including a first fin structure and a first source/drain epitaxial structure extending in a first direction and protruding from the isolation insulating layer;

a second FinFET disposed adjacent to the first FinFET, including a second fin structure extending in the first direction and protruding the isolation insulating layer and a second source/drain epitaxial structure;

a first dielectric layer separating the first source/drain epitaxial structure and the second source/drain epitaxial structure; and

a first source/drain contact contacting the first source/drain epitaxial structure, wherein:

the first FinFET includes only one fin structure,

the first source/drain epitaxial structure is asymmetric with respect to the first fin structure in a cross-section along a second direction perpendicular to the first direction,

the first source/drain contact contacts a top surface and a side surface of the first source/drain epitaxial structure and contacts the isolation insulating layer, an

A second dielectric layer is in contact with the other side of the first source/drain epitaxial structure.

2. The semiconductor device of claim 1, wherein the second source/drain epitaxial structure is symmetric with respect to the second fin structure in a cross-section along the second direction.

3. The semiconductor device of claim 1, further comprising:

a second source/drain contact contacting the second source/drain epitaxial structure.

4. The semiconductor device of claim 1, wherein the first source/drain epitaxial structure is formed on a top surface and side surfaces of an upper portion of the first fin structure protruding from the isolation insulating layer.

5. The semiconductor device of claim 3, wherein the first dielectric layer is in contact with one side of the second source/drain epitaxial structure and the second dielectric layer is in contact with the other side of the second source/drain epitaxial structure.

6. The semiconductor device of claim 3, wherein:

the first dielectric layer includes a lower dielectric layer and an upper dielectric layer disposed on the lower dielectric layer and made of a different material from the lower dielectric layer, and

the lower dielectric layer is in contact with the first source/drain contact and the second source/drain epitaxial structure.

7. A semiconductor device comprising a fin field effect transistor (FinFET), comprising:

a first source/drain structure comprising a first fin structure that is only one of the first source/drain structures and extends in a first direction, a first source/drain epitaxial layer formed on the first fin structure;

a second source/drain structure comprising a second fin structure that is only one of the second source/drain structures and extends in the first direction, a second source/drain epitaxial layer being formed on the second fin structure;

a third source/drain structure comprising a third fin structure that is only one of the third source/drain structures and extends in the first direction, a third source/drain epitaxial layer being formed on the third fin structure; and

a first dielectric layer separating the first source/drain structure and the second source/drain structure, wherein:

the first source/drain epitaxial layer is formed on a top surface and a side surface of an upper portion of the first fin structure protruding from the isolation insulating layer and is asymmetric with respect to the first fin structure in a cross section along a second direction perpendicular to the first fin structure, the first source/drain epitaxial layer not being in contact with other fin structures except the first fin structure,

one side of an upper portion of the first fin structure is covered by a silicide layer and a portion of another side of the upper portion of the first fin structure is in direct contact with the first dielectric layer, an

The second source/drain epitaxial layer is merged with the third source/drain epitaxial layer.

8. The semiconductor device of claim 7, further comprising:

a first source/drain contact contacting the first source/drain epitaxial layer; and

a second source/drain contact contacting the second source/drain epitaxial layer and the third source/drain epitaxial layer,

wherein the first source/drain contact is in contact with one side of the first source/drain epitaxial layer and the isolation insulating layer, an

The first dielectric layer contacts the other side of the first source/drain epitaxial layer, one side of the second source/drain epitaxial layer, and the isolation insulating layer.

9. A semiconductor device comprising a fin field effect transistor (FinFET), comprising:

a first source/drain structure comprising a first fin structure extending in a first direction, a first source/drain epitaxial layer formed on the first fin structure;

a second source/drain structure comprising a second fin structure extending in the first direction, a second source/drain epitaxial layer formed on the second fin structure,

a third source/drain structure comprising a third fin structure extending in the first direction, a third source/drain epitaxial layer formed on the third fin structure; and

a first dielectric layer separating the first source/drain structure and the second source/drain structure, wherein:

the first source/drain epitaxial layer is formed on a top surface and a side surface of an upper portion of the first fin structure protruding from the isolation insulating layer and is asymmetric with respect to the first fin structure in a cross section along a second direction perpendicular to the first direction, the first source/drain epitaxial layer is not in contact with other fin structures except the first fin structure,

one side of an upper portion of the first fin structure is covered by a silicide layer, and a portion of another side of the upper portion of the first fin structure is in direct contact with the first dielectric layer,

said second source/drain epitaxial layer merging with said third source/drain epitaxial layer, an

The first source/drain epitaxial layer and the second source/drain epitaxial layer have a first conductivity type, and the third source/drain epitaxial layer has a second conductivity type different from the first conductivity type.

10. The semiconductor device of claim 9, wherein:

the first dielectric layer includes a lower dielectric layer and an upper dielectric layer disposed on the lower dielectric layer and made of a different material from the lower dielectric layer, an

The lower dielectric layer is in contact with the first source/drain epitaxial layer and the second source/drain epitaxial layer.

Technical Field

Embodiments of the present application relate generally to the field of semiconductors, and more particularly, to semiconductor devices including fin field effect transistors (finfets).

Background

As the semiconductor industry moves into nanotechnology process nodes in the process of pursuing higher device densities, higher performance, and lower costs, challenges from fabrication and design issues have led to the development of three-dimensional designs such as fin field effect transistors (finfets) and the use of metal gate structures with high-k (dielectric constant) materials. A metal gate structure is generally manufactured by using a gate replacement technique, and a source electrode and a drain electrode are formed by using an epitaxial growth method.

Disclosure of Invention

Embodiments of the present application provide a method of forming a semiconductor device including a fin field effect transistor (FinFET), the method including: forming a sacrificial layer above the source/drain structure and the isolation insulating layer of the fin field effect transistor structure; forming a mask pattern over the sacrificial layer; patterning the sacrificial layer and the source/drain structure by using the mask pattern as an etching mask, thereby forming an opening adjacent to the patterned sacrificial layer and the patterned source/drain structure; forming a dielectric layer in the opening; after forming the dielectric layer, removing the patterned sacrificial layer to form a contact opening over the patterned source/drain structure; and forming a conductive layer in the contact opening.

Another embodiment of the present application provides a method of forming a semiconductor device including a fin field effect transistor (FinFET), the method including: forming a sacrificial layer over a first source/drain structure of a first finfet structure, a second source/drain structure of a second finfet structure, and a spacer insulating layer, the first and second source/drain structures being merged; forming a mask pattern over the sacrificial layer; patterning the sacrificial layer and the first and second source/drain structures by using the mask pattern as an etch mask, thereby separating the first and second source/drain structures and forming an opening adjacent to the patterned sacrificial layer and the patterned first and second source/drain structures; forming a dielectric layer in the opening; after forming the dielectric layer, removing the patterned sacrificial layer to form contact openings over the patterned first source/drain structures and the patterned second source/drain structures, respectively; and forming a conductive layer in the contact opening.

Yet another embodiment of the present application provides a semiconductor device including a fin field effect transistor (FinFET), including: a first finfet comprising a first fin structure and a first source/drain structure extending in a first direction; a second fin field effect transistor disposed adjacent to the first fin field effect transistor and including a second fin structure and a second source/drain structure extending in the first direction; and a dielectric layer separating the first source/drain structure and the second source/drain structure, wherein: the first source/drain structure is asymmetric with respect to the first fin structure in a cross-section along a second direction that intersects the first direction.

Drawings

Various aspects of the present application may be best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A-1C illustrate one of various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 2A-2C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 3A-3C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 4A-4C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 5A-5C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 6A-6C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 7A-7C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Figures 8A-8C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 9A-9C illustrate one of the various stages of a semiconductor device fabrication process according to some embodiments of the present application.

Fig. 10A-10E illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 11A and 11B illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 12A and 12B illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 13 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 14 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 15A and 15B illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 16A and 16B illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 17A and 17B illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 18 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 19 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 20 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 21A-21D illustrate one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 22A and 22B illustrate exemplary cross-sectional views of semiconductor devices according to some embodiments of the present application.

Fig. 23 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 24 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 25 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 26 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 27 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Fig. 28 illustrates one of the various stages of a semiconductor device fabrication process in accordance with one or more embodiments of the present application.

Detailed Description

It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present application. Of course, these are merely examples and are not intended to limit the present application. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired properties of the device. Further, in the following description, forming a first part over or on a second part may include embodiments in which the first part and the second part are formed in direct contact, and may also include examples in which an additional part may be formed between the first part and the second part, so that the first part and the second part may not be in direct contact. The various components may be arbitrarily drawn in different scales for simplicity and clarity. In the drawings, some layers/components may be omitted for simplicity.

Furthermore, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element (or components) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the term "made of …" may mean "including" or "consisting of …". Further, in the following manufacturing processes, there may be one or more additional operations in/between the operations described, and the order of the operations may be changed.

Disclosed embodiments relate to methods of forming source/drain (S/D) structures for fin field effect transistors (finfets), including methods of isolating or separating S/D structures. Embodiments such as those disclosed herein are generally applicable not only to finfets, but also to double-gate, surrounding-gate, omega-gate or full-ring-gate transistors, 2-dimensional FETs, and/or nanowire transistors, or any suitable device having source/drain epitaxially grown layers.

Fig. 1A-9C illustrate various ones of a semiconductor device fabrication process according to some embodiments of the present application. Like reference numerals are used to refer to like elements throughout the various views and illustrative embodiments. In fig. 1A to 9C, an "a" diagram (e.g., fig. 1A, fig. 2A, etc.) shows a perspective view, a "B" diagram (e.g., fig. 1B, fig. 2B, etc.) shows a sectional view along a Y direction corresponding to a line Y1-Y1 shown in the "a" diagram, and a "C" diagram (e.g., fig. 1C, fig. 2C, etc.) shows a sectional view along an X direction corresponding to a line X1-X1 shown in the "a" diagram. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 1A-9C, and that some of the operations described below may be replaced or eliminated with respect to additional embodiments of the method. The order of operations/processes may be interchanged.

Referring first to fig. 1A-1C, fig. 1A-1C illustrate the structure after various fabrication operations are performed to form a FinFET structure. As shown in fig. 1A-1C, source/drain structures 120 and metal gates 130 are formed over a substrate 101 along with a gate dielectric layer 131. Such a structure may be formed by the following manufacturing operations.

In fig. 1A to 1C, a substrate 101 having one or more fin structures is shown, wherein one fin structure 102 is shown. It should be understood that one fin structure is shown for illustrative purposes, but other embodiments may include any number of fin structures. In some embodiments, some or more dummy fin structures are formed adjacent to fin structures of an active FinFET. The fin structure 102 extends in the X-direction and protrudes out of the substrate in the Z-direction, while the gate 130 extends in the Y-direction.

The substrate 101 may include various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with a p-type or n-type dopant. For example, the doped region may be doped with a p-type dopant, such as boron or BF₂(ii) a n-type dopants such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for n-type finfets or alternatively configured for p-type finfets.

In some embodiments, the substrate 101 may be made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; suitable alloy or compound semiconductors such as group IV compound semiconductors (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), group III-V compound semiconductors (e.g., gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), or indium gallium phosphide (GaInP)), and the like. Further, the substrate 101 may include an epitaxial layer (epi layer), which may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

For example, the fin structures 102 may be formed using a patterning process to form trenches such that the fin structures 102 are formed between adjacent fin structures. As discussed in more detail below, the fin structure 102 will be used to form a FinFET.

An isolation region, such as a Shallow Trench Isolation (STI)105, is disposed in a trench above the substrate 101. In some embodiments, one or more liner layers are formed over the substrate 101 and over the sidewalls of the bottom 103 of the fin structure 102 prior to forming the isolation insulating layer 105. In some embodiments, the liner layer includes a first fin liner layer 106 formed on the substrate 101 and on sidewalls of the bottom 103 of the fin structure 102 and a second fin liner layer 108 formed on the first fin substrate layer 106. In some embodiments, each spacer layer has a thickness between about 1nm and about 20 nm.

In some embodiments, the first fin liner layer 106 comprises silicon oxide and has a thickness between about 0.5nm and about 5nm, and the second fin liner layer 108 comprises silicon nitride and has a thickness between about 0.5nm and about 5 nm. The liner layer may be deposited by one or more processes such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD), although any acceptable process may be utilized.

The isolation insulating layer 105 may be made of a suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, fluorine doped silicate glass (FSG), low-k dielectrics such as carbon doped oxide, very low-k dielectrics such as porous carbon doped silicon dioxide, polymers such as polyimide, combinations of these, and the like. In some embodiments, the isolation insulating layer 105 is formed by a process such as CVD, flowable CVD (fcvd), or a spin-on-glass process, although any acceptable process may be utilized. Subsequently, portions of the isolation insulating layer 105 extending over the top surface of the fin structure 102 and portions of the liner layer located over the top surface of the fin structure 102 are removed, for example, using an etching process, Chemical Mechanical Polishing (CMP), or the like.

In some embodiments, the isolation insulating layer 105 and the liner layer are recessed to expose the upper portion 104 of the fin structure 102 as shown in fig. 1A-1C. In some embodiments, the isolation insulating layer 105 and the pad layer are recessed using a single etch process or a multiple etch process. In some embodiments, wherein the isolation insulating layer 105 is made of silicon oxide, the etching process may be a dry etching, a chemical etching, or a wet cleaning process, for example. For example, the chemical etch may employ fluorine-containing chemicals such as dilute hydrofluoric (dHF) acid. In some embodiments, fin height H is after the fin formation process_finAbout 30nm or higher, such as about 50nm or higher. In one embodiment, the fin height is between about 40nm and about 80 nm. It should be appreciated that the fin height may be modified by subsequent processing. Other materials, processes, and dimensions may be used.

After forming the fin structure 102, the exposed fin structureA dummy gate structure including a dummy gate dielectric layer and a dummy gate electrode is formed over 102. The dummy gate dielectric layer and dummy gate electrode will then be used to define and form the source/drain regions. In some embodiments, the dummy gate dielectric layer and the dummy gate electrode are formed by depositing and patterning a dummy dielectric layer formed over the exposed fin structure 102 and a dummy electrode layer over the dummy dielectric layer. The dummy dielectric layer may be formed by thermal oxidation, CVD, sputtering, or any other method known and used in the art for forming dummy dielectric layers. In some embodiments, the dummy dielectric layer may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, SiCN, SiON and SiN, low-k dielectrics (such as carbon-doped oxides), very low-k dielectrics (such as porous carbon-doped silicon dioxide), polymers (such as polyimide), and the like, or combinations thereof. In some embodiments, SiO is used₂。

Subsequently, a dummy electrode layer is formed over the dummy dielectric layer. In some embodiments, the dummy electrode layer is a conductive material and may be selected from the group consisting of amorphous silicon, polycrystalline silicon, amorphous germanium, polycrystalline germanium, amorphous silicon-germanium, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy electrode layer may be deposited by PVD, CVD, sputter deposition or other techniques known and used in the art for depositing conductive materials. Other materials, both conductive and non-conductive, may be used. In one embodiment, polysilicon is used.

A mask pattern may be formed over the dummy electrode layer to facilitate patterning. The mask pattern may be made of SiO₂、SiCN、SiON、Al₂O₃SiN, or other suitable material. The dummy electrode layer is patterned into a dummy gate electrode by using the mask pattern as an etching mask. In some embodiments, the dummy dielectric layer is also patterned to define a dummy gate dielectric layer.

Subsequently, sidewall spacers 132 are formed along sidewalls of the dummy gate structures. The sidewall spacers 132 may be formed by depositing and anisotropically etching an insulating layer deposited over the dummy gate structures, the fin structures 102, and the isolation insulating layer 105. In some casesIn an embodiment, the sidewall spacer 132 is formed of silicon nitride, and may have a single-layer structure. In an alternative embodiment, the sidewall spacers 132 may have a composite structure including multiple layers. For example, the sidewall spacers 132 may include a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. Such as SiO may also be used₂Other materials such as SiCN, SiON, SiN, SiOCN, other low-k materials, or combinations thereof. In some embodiments, the thickness of the sidewall spacers 132 is in a range from about 5nm to about 40 nm.

After forming the dummy gate structures and sidewall spacers, source/drain (S/D) structures 120 are formed on the exposed portions 104 of the fin structure 102 along opposite sides of the dummy gate structures. S/D structures 120 may be epitaxially formed on the exposed side and top surfaces of fin structure 104. In some embodiments, the fin structure 104 may be recessed and the S/D structures epitaxially formed on exposed portions of the recessed fins. The use of epitaxially grown material in the source/drain regions allows the source/drain regions to stress the channel of the FinFET.

The materials of the S/D structure 120 for the n-type and p-type finfets may be different such that one type of material for the n-type FinFET applies a tensile stress to the channel region and the other type of material for the p-type FinFET applies a compressive stress. For example, SiP or SiC may be used to form n-type FinFETs, and SiGe or Ge may be used to form p-type FinFETs. Other materials may be used. In some embodiments, the S/D structure 120 includes two or more epitaxial layers having different compositions and/or different dopant concentrations.

In some embodiments using different materials for the n-type and p-type devices, one structure (e.g., an n-type fin structure) is masked while an epitaxial material is formed for the other structure (e.g., a p-type fin structure), and the process is repeated for the other. The S/D structure 120 may be doped by an implantation process to implant an appropriate dopant or by in-situ doping when growing the material. For example, for a p-channel FET, the channel may be Si or Si_1-xGe_xThe doped epitaxial film may be boron doped Si_1-yGe_yWhereinY is equal to or greater than x to introduce a longitudinal compressive strain to the channel to enhance hole mobility. For an n-channel FET, the channel may be Si, for example, the doped epitaxial film may be phosphorus doped silicon (Si: P) or phosphorus doped silicon-carbon (Si)_1-zC_zP). In the channel is a metal such as In_mGa_1-mIn the case of a compound semiconductor of As, for example, the doped epitaxial film may be In_mGa_1-mAs, wherein n is less than or equal to m.

As shown in fig. 1A and 1B, the S/D structure 120 extends wider in the Y-direction than the fin structure 104. In some embodiments, the cross-section of the S/D structures 120 in the Y-direction is substantially hexagonal, and in other embodiments, the cross-section of the S/D structures 120 is diamond-shaped, cylindrical, or bar-shaped. In some embodiments, the width W of the S/D structure in the Y direction_SDIn the range from about 25nm to about 100 nm.

After forming the S/D structure 120, a first insulating layer 122 serving as a liner layer is deposited to cover the S/D structure 120 and on the sidewall spacers 132 of the dummy gate structure. The first insulating layer 122 serves as an etch stop during patterning of subsequently formed dielectric materials. In some embodiments, the first insulating layer 122 comprises SiO₂SiCN, SiON, SiN, and other suitable dielectric materials. In one embodiment, SiN is used. The first insulating layer 122 may be made of a plurality of layers including a combination of the above materials. First insulating layer 122 may be deposited by one or more processes, such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. In some embodiments, the first insulating layer 122 has a thickness between about 0.5nm and about 5 nm. In other embodiments, other thicknesses may be used.

After the first insulating layer 122 is formed, a first sacrificial layer 115 is formed over the first insulating layer 122. In some embodiments, the first sacrificial layer comprises one or more layers of a dielectric material, such as SiO₂SiCN, SiON, SiOC, SiOH, SiN or other suitable dielectric material. In some embodiments, the first sacrificial layer is formed by a film formation process such as CVD, PVD, ALD, FCVD, or spin-on-glass process115, but any acceptable process may be utilized. Subsequently, a portion of the first insulating layer 122 is removed to expose an upper surface of the dummy gate electrode, for example, using an etching process, CMP, or the like.

Subsequently, the dummy gate electrode and the dummy gate dielectric layer are removed. The removal process may include one or more etching processes. For example, in some embodiments, the removal process includes a selective etch using a dry etch or a wet etch. When dry etching is used, the process gas may include CF₄、CHF₃、NF₃、SF₆、 Br₂、HBr、Cl₂Or a combination thereof. Such as N may optionally be used₂、O₂Or a diluent gas of Ar. When wet etching is used, the etching solution (etchant) may include NH₄OH:H₂O₂:H₂O(APM)、 NH₂OH、KOH、HNO₃:NH₄F:H₂O, and the like. The dummy gate dielectric layer may be removed using a wet etch process, such as diluted HF acid may be used. Other processes and materials may be used.

After removing the dummy gate structure, a gate dielectric layer 131 is formed over the channel region of the fin structure 104. In some embodiments, gate dielectric layer 131 includes one or more high-k dielectric layers (e.g., having a dielectric constant greater than 3.9). For example, the one or more gate dielectric layers may include one or more layers of metal oxides or silicates of Hf, Al, Zr, combinations thereof, and multilayers thereof. Other suitable materials include La, Mg, Ba, Ti, Pb, Zr in the form of metal oxides, metal alloy oxides, and combinations thereof. Exemplary materials include MgO_x、BaTi_xO_y、BaSr_xTi_yO_z、PbTi_xO_y、 PbZr_xTi_yO_z、SiCN、SiON、SiN、Al₂O₃、La₂O₃、Ta₂O₃、Y₂O₃、HfO₂、ZrO₂、 HfSiON、YGe_xO_y、YSi_xO_yAnd LaAlO₃And the like. The gate dielectric layer 131 is formed by molecular beam deposition (M)BD), ALD, PVD, etc. In some embodiments, the gate dielectric layer 131 has a thickness of about 0.5nm to about 5 nm. In some embodiments, a gate dielectric layer 131 is also formed on the sides of the sidewall spacers 132.

In some embodiments, an interfacial layer (not shown) may be formed over the channel region 104 and the gate dielectric layer 131 may be formed over the interfacial layer prior to forming the gate dielectric layer 131. The interface layer helps to buffer the subsequently formed high-k dielectric layer from the underlying semiconductor material. In some embodiments, the interfacial layer is a chemical silicon oxide formed by a chemical reaction. For example, deionized water + ozone (DIO) may be used₃)、NH₄OH+H₂O₂+H₂O (apm) or other methods to form chemical silicon oxide. For other embodiments of the interfacial layer, different materials or processes may be utilized. In an embodiment, the interfacial layer has a thickness of about 0.2nm to about 1 nm.

After forming the gate dielectric layer 131, the gate electrode 130 is formed over the gate dielectric layer 131. The gate electrode 130 may be a metal selected from the group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr. In some embodiments, the gate electrode 130 includes a metal selected from the group of TiN, WN, TaN, and Ru. Metal alloys such as Ti-Al, Ru-Ta, Ru-Zr, Pt-Ti, Co-Ni, and Ni-Ta may be used and/or WN may be used_x、TiN_x、MoN_x、TaN_xAnd TaSi_xN_yThe metal nitride of (2). In some embodiments, the gate electrode 130 has a thickness in the range of about 5nm to about 100 nm. The gate electrode 130 may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof. A planarization process such as CMP may be performed to remove excess material.

In some embodiments of the present application, the gate electrode 130 includes one or more work function adjusting layers (not shown) disposed on the gate dielectric layer 131. The work function adjusting layer is made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC or a multilayer of two or more of these materials. For an n-channel FinFET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi is used as a work function adjusting layer, while for a p-channel FinFET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co is used as a work function adjusting layer.

Thereafter, the gate electrode 130, the gate dielectric layer 131, and the work function adjusting layer are recessed, and a gate cap layer 134 is formed on the recessed gate electrode 130. In some embodiments, when gate electrode 130 is made primarily of W, for example, a dry etch process (using Cl) may be used in a temperature range of 24 ℃ to 150 ℃ and at a pressure below 1 torr₂/O₂/BCl₃) The gate electrode is recessed.

After recessing the gate electrode 130, a gate cap layer 134 is formed in the recess to protect the gate electrode 130 during subsequent processes. In some embodiments, the gate cap layer 134 comprises SiO₂、SiCN、 SiON、SiN、Al₂O₃、La₂O₃SiN, combinations thereof, etc., although other suitable dielectric films may be used. For example, the gate cap layer 134 may be formed using CVD, PVD, spin coating, or the like. Other suitable process steps may be used. A planarization process such as CMP may be performed to remove excess material.

Fig. 2A-2C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

As shown in fig. 2A to 2C, the first sacrificial layer 115 is at least partially removed from both side regions of the S/D structure 120 to form the opening 116. In some embodiments, all of the first sacrificial layer 115 is removed. The first sacrificial layer 115 may be removed by a suitable etching operation, such as dry etching and/or wet etching. The etching operation stops substantially at the first insulating layer 122. In some embodiments, the first insulating layer 122 has a thickness between about 0.5nm to about 10 nm.

Fig. 3A-3C illustrate exemplary views of one of the various stages for fabricating a FinFET device, in accordance with some embodiments.

After the opening 116 is formed, a second sacrificial layer 140 is formed in the opening 116. Second sacrificeThe layer 140 is made of a material having a higher (e.g., 5 or more) etch selectivity with respect to the material of the first insulating layer 122 and/or the isolation insulating layer 105. In some embodiments, the second sacrificial layer 140 is made of one or more layers of group IV materials, such as Si, SiGe, SiC, Ge, SiGeC, and GeSn, which may be crystalline, polycrystalline, or amorphous and may be doped or undoped. In other embodiments, the second sacrificial layer 140 is composed of SiOC, SiC, SiON, SiCN, SiOCN, SiN and/or SiO₂Is formed of one or more silicon-based dielectric layers. Aluminum-based dielectric materials such as alumina, aluminum oxycarbide, and aluminum oxynitride may be used. SOC (spin-carbon) may also be used. In certain embodiments, the second sacrificial layer 140 is made of one or more layers of a group III-V compound semiconductor including, but not limited to, GaAs, GaN, InGaAs, InAs, InP, InSb, InAsSb, AlN, and/or AlGaN. The second sacrificial layer 140 may be deposited by one or more processes such as PVD, CVD, or ALD, although any acceptable process may be utilized. Other materials and/or processes may be used. In one embodiment, Si is used as the second sacrificial layer.

A planarization operation such as an etch-back process or CMP may be performed to planarize the upper surface of the second sacrificial layer 140. The upper surface of the gate cap layer 134 is exposed by the planarization operation. In some embodiments, the height H of the second sacrificial layer, measured from the surface of the first insulating layer 122 on the isolation insulating layer 105, after the planarization operation_sacrIn the range from about 100nm to about 350 nm.

Fig. 4A-4C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

After the second sacrificial layer 140 is formed, a mask pattern 142 is formed over the second sacrificial layer 140. The mask pattern 142 may be formed by patterning a suitable layer of mask material using a photolithography operation. The mask pattern 142 extends in the X direction and has a width W in the Y direction_hmIn some embodiments, the width W_hmIn the range of from about 5nm to about 100nm, and in other embodiments, in the range of from about 10nm to about 40 nm. Width ofW_hmMay be other values depending on the design rules and/or type of semiconductor device.

The mask pattern 142 is made of one or more layers of dielectric material, such as SiO₂SiN and/or SiON and/or TiN. The material for the mask pattern 142 may be deposited by one or more processes such as PVD, CVD, or ALD, but any acceptable process may be utilized. Other materials and/or processes may be used.

The second sacrificial layer 140, the first insulating layer 122, and the S/D structure 120 are anisotropically etched by using the mask pattern 142 as an etching mask, thereby forming an opening 144 adjacent to the patterned second sacrificial layer 140 and the S/D structure 120. The etching operation may include a plurality of etching processes using different plasma gases.

When a Si-based material (e.g., polysilicon or amorphous silicon) is used as the second sacrificial layer 140, it is possible to form a layer by using, for example, a gas including HBr or Cl₂And SF₆The etching is performed by plasma dry etching of the gas (2). When SOC (spin on carbon) is used as the second sacrificial layer 140, N may be included by using, for example₂And H₂Or gases comprising SO₂And O₂The etching is performed by plasma dry etching of the gas (2). When a Si oxide-based material formed by FCVD is used as the second sacrificial layer 140, etching may be performed by plasma dry etching using, for example, a gas including fluorocarbon and/or fluorine. When a Ge-based material (e.g., Ge or SiGe) is used as the second sacrificial layer 140, etching may be performed by plasma dry etching using, for example, a gas including fluorocarbon or a gas including halogen. During etching, the substrate may be heated at a temperature between about 20 ℃ to about 200 ℃.

By this etching operation, at least the sides of the S/D structure 120 are removed such that the etched sides of the S/D structure 120 are substantially parallel to the sides of the upper fin structure 104. In some embodiments, the amount of etching of one side of the S/D structure 120 (substantially equal to W as shown in FIG. 1B)_SDAnd W shown in FIG. 4B_hmHalf of the difference between) is in the range from about 5nm to about 40 nm. In some embodimentsAfter the patterning (etching) of the S/D structure 120, when both side portions are etched, the width of the patterned S/D structure 120 in the Y direction is in a range from about 10nm to about 40 nm.

In fig. 4A and 4B, both side portions of the S/D structure 120 are etched and in other embodiments, only one side portion of the S/D structure 120 is etched by using the mask pattern 142 having a different shape.

It should be noted that as shown in fig. 4A, the gate cap layer 134 is not substantially etched during the patterning of the second sacrificial layer 140 and the source/drain structure 120. In other words, the material for the mask pattern 142 has a high etch selectivity (e.g., 5 or more) with respect to the gate cap layer 134.

Fig. 5A-5C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

The mask pattern 142 is removed by using a suitable etching operation and/or a planarization operation such as CMP. In some embodiments, after removing the mask pattern 142, the height H of the second sacrificial layer 140 from the surface of the isolation insulation layer 105_etchIn the range from about 80nm to about 250 nm.

Fig. 6A-6C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

After removing the mask pattern 142, a second insulating layer 146 is formed over the patterned second sacrificial layer 140 and the patterned S/D structure 120. As shown in fig. 6A, a second insulating layer 146 is also formed on the sidewall spacers 132 and the gate capping layer 134.

In some embodiments, second insulating layer 146 comprises SiO₂SiCN, SiON, SiCN, SiOCN, and SiN, but other suitable dielectric materials may be used. In one embodiment, a silicon nitride based material such as SiN is used. The second insulating layer 146 may be made of a plurality of layers including a combination of the above materials. Second insulating layer 146 can be deposited by one or more processes, such as PVD, CVD, or ALD, although any acceptable process can be utilized. Other materials and/or processes may be used. In some casesIn an embodiment, the second insulating layer 146 has a thickness between about 1nm and about 10 nm. In other embodiments, other thicknesses are used.

In some embodiments, as shown in fig. 6A and 6B, before forming the second insulating layer 146, a silicide layer 126 is formed on the patterned S/D structure 120 to reduce R between the S/D structure and a contact metal formed later_c. The metal silicide formation process may form a metal silicide on the sides of the S/D structure. The metal silicide formation process includes a metal film deposition on the S/D structure 120, a heat treatment to form a metal silicide at an interface or surface of the S/D structure 120, and an etching process to remove excess unreacted metal. The metal silicide comprises TiSi_x、NiSi_x、CoSi_x、NiCoSi_xAnd TaSi_xHowever, other suitable silicide materials may be used. In some embodiments, silicide layer 126 has a thickness between about 0.5nm and about 10 nm. In other embodiments, the silicide layer is not formed at this stage of the fabrication operation, and may be formed at a later stage of fabrication.

Fig. 7A-7C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

After forming the second insulating layer 146, a first interlayer dielectric (ILD) layer 145 is formed to fill the opening 144 and over the second sacrificial layer 140 and the S/D structure 120.

ILD layer 145 may comprise a single layer or multiple layers. In some embodiments, ILD layer 145 comprises SiO₂SiCN, SiOC, SiON, SiOCN, SiN, or low-k materials, but other suitable dielectric films may be used. ILD layer 145 may be formed by CVD, PECVD or ALD, FCVD, or spin-on-glass processes. A planarization process, such as a CMP process, may be performed to remove excess material. In some embodiments, the upper surface of the second sacrificial layer 140 (and the cap insulating layer 134) is exposed by a planarization process.

In some embodiments, when FCVD is used, a curing process is performed on the flowable isolating dielectric precursor. The curing process may include UV curing, ozone (O)₃) Plasma curing or low temperature O₃Plasma + UV curing (LTB + UV curing) to convert the flowable isolating dielectric precursor into a dielectric layer such as a silicon oxide layer. In some embodiments, the process temperature range of the UV curing process is between about 0 ℃ and about 10 ℃. In some embodiments, O₃The process temperature range of the plasma curing process is between about 100 ℃ and about 250 ℃. In some embodiments, the process temperature range for the LTB + UV curing process is between about 30 ℃ and about 50 ℃. In some embodiments, in order to save process time, the curing process may be performed only once after the deposition process, but is not limited thereto. The deposition process and the curing process may be alternately performed. In other embodiments, the flowable insulating dielectric precursor may also be converted directly into a dielectric layer by an oxidation process that introduces nitrogen, oxygen, ozone, or steam directly.

To further increase the structural density of the ILD layer, a thermal treatment process may be performed on the isolating dielectric layer after the curing process. The heat treatment process includes a steam-containing heat treatment process (wet annealing) and a nitrogen-containing heat treatment process (dry annealing). In some embodiments, the process temperature range for the steam-containing heat treatment process is between about 400 ℃ and about 1000 ℃, and the process temperature for the nitrogen-containing gas heat treatment process is between about 1000 ℃ and about 1200 ℃. In other embodiments, the temperature of the heat treatment may be reduced to about 400 ℃ by exposing the film to ultraviolet radiation, for example, in an ultraviolet heat treatment (UVTP) process.

In some embodiments, the ILD layer may have a relative dielectric constant of less than 6 after curing or processing.

In other embodiments, a spin-on dielectric (SOD) process is performed to form ILD layer 145. In this embodiment, the second insulating layer 146, the nitrogen-containing liner layer, is formed in a previous process to provide a suitable interlayer layer for the isolation dielectric layer deposited in the contact isolation region by the SOD process. Thus, the ILD layer may be formed by an SOD process using a suitable precursor.

In the SOD process for ILD layer 145, the precursor may be an organosilicon compound such as, but not limited to, siloxanes, methylsiloxanes, polysilazanes and hydrogen silsesquioxanes, perhydropolysilazanes (PHPS), and other suitable materials. The SOD precursor is dissolved in a compatible organic solvent of the coating solution typically used for spin-on chemistry. For example, suitable organic solvents include dibutyl ether (DBE), toluene, xylene, Propylene Glycol Methyl Ether Acetate (PGMEA), ethyl lactate, isopropyl alcohol (IPA), and the like, and it is preferable to use xylene as a solvent for PHPS. The concentration of the SOD precursor in the solution can be varied to adjust the consistency (i.e., viscosity) of the solution and the thickness of the coating. In some embodiments, a solution containing between about 4% to about 30% by weight of the SOD precursor may be used. In other embodiments, a solution containing between about 8% to about 20% by weight of the SOD precursor is used. Additional minor additives such as surfactants and binders may be included in the solution.

During the precursor spin coating process, the wafer is rotated to uniformly diffuse the SOD precursor from the center of the wafer to the edge. In some embodiments, the rotational speed of the casting spin used to coat the SOD precursor on the substrate may be from 100rpm to 3000rpm for a 12 inch wafer. In some embodiments, the dynamic dispense rate of the SOD precursor is about 1ml/sec, and the dispense slurry will spread completely to the edge of the wafer before the main velocity. Thus, the SOD precursor can completely cover the bottom of the contact isolation hole and fill the opening 144.

Subsequently, after SOD deposition, a pre-bake process was performed to stabilize the SOD layer. In some embodiments, the pre-bake process is performed at a low temperature in the range of about 100 ℃ to about 200 ℃ in an air environment. After the pre-baking process, a heat treatment process is performed to densify the SOD layer. In some embodiments, the heat treatment process is an annealing process performed at a high temperature in a range of about 400 ℃ to about 1100 ℃. The annealing process may be a process using a material including steam, O₂And H₂Wet annealing process or use of gases including N₂And O₂Dry annealing of the gas. In other embodiments, the thermal treatment process uses a plasma at a lower temperature ranging from about 150 ℃ to about 400 ℃. Preferably water vapor (H)₂O) and hydrogen (H)₂) Partial pressure ratio ofThe ratio is controlled to be about 1X 10^-11To a value in the range of about 1.55.

Fig. 8A-8C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

Subsequently, the second sacrificial layer 140 is removed, followed by the removal of the remaining first insulating layer 122 on top of the S/D structure 120, thereby forming a contact opening 148. As shown in fig. 8A-8C, the contact opening 148 is defined by the second insulating layer 146 and the sidewall spacer 132. The etching operation to remove the second sacrificial layer 140 may be isotropic or anisotropic.

When a Si-based material (e.g., polysilicon or amorphous silicon) is used as the second sacrificial layer 140, it is possible to form a thin film by using, for example, a material including Cl₂And NF₃Or gas comprising F₂Plasma dry etching of the gas (2), or use of NH₄The etching is performed by wet etching of OH and/or Tetramethylammonium (TMAH). When SOC (spin on carbon) is used as the second sacrificial layer 140, it is possible to use a material including N, for example₂And H₂Or gases comprising SO₂And O₂The etching is performed by plasma dry etching of the gas (2). When a Si oxide-based material formed by FCVD is used as the second sacrificial layer 140, etching may be performed by wet etching using, for example, HF or BHF. When a Ge-based material (e.g., Ge or SiGe) is used as the second sacrificial layer 140, dry etching using plasma such as ozone or use of NH-containing material may be used₄OH and H₂O₂Or containing HCl and H₂O₂The wet etching of the solution of (4) is performed. The remaining first insulating layer 122 may be removed by a suitable etching operation.

Fig. 9A-9C illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

After removing the second sacrificial layer 140 and the remaining first insulating layer 122, an additional silicide layer 127 is formed on the exposed top of the S/D structure 120. When the silicide layer 126 is not formed, the silicide layer is only disposed on the top of the S/D structure 120 (at the bottom of the contact opening 148 defined by the second insulating layer 146 and the sidewall spacers 132). Silicide layer 127 may be formed by a metal silicide formation process similar to the formation of silicide layer 126. In some embodiments, silicide layer 127 has a thickness between about 0.5nm and about 10 nm.

Subsequently, contacts 150 are formed in the contact openings 148 to contact the silicide layers 127 formed on the tops of the S/D structures 120.

The contact 150 may include a single layer or a multi-layer structure. For example, in some embodiments, the contacts 150 in the contact openings 148 include a contact liner layer, such as a diffusion barrier layer, an adhesive layer, or the like, and a contact body formed over the contact liner layer. The contact liner layer may include Ti, TiN, Ta, TaN, or the like formed by ALD, CVD, or the like. The contacts may be formed by depositing a conductive material, such as one or more layers of Ni, Ta, TaN, W, Co, Ti, TiN, Al, Cu, Au, alloys thereof, combinations thereof, and the like, although other suitable metals may also be used. A planarization process such as CMP may be performed to remove excess material from the surface of ILD layer 145.

In some embodiments, after forming the contacts 150, the height H of the gate structure including the gate cap layer 134, measured from the top of the fin structure 104_gA height H of the metal gate 130 in a range from about 20nm to 100nm and measured from a top of the fin structure 104_mgIn the range from about 10nm to about 60 nm.

After forming the contacts 150, a CMOS process is further performed to form various components such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers.

Fig. 10A to 21D illustrate various ones of semiconductor device fabrication processes according to other embodiments of the present application. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 10A-21D, and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/processes may be interchanged. Materials, configurations, dimensions, and/or processes the same as or similar to those of the above-described embodiment described with reference to fig. 1A to 9C may be employed in the following embodiments, and thus detailed descriptions may be omitted.

Fig. 10A to 21D illustrate respective processes in a semiconductor device manufacturing process of a Static Random Access Memory (SRAM) cell formed of a FinFET. As shown in fig. 10A to 10E, source/drain structures 220 and 221 and a metal gate 230 are formed over a substrate 201 together with a gate dielectric layer 231. Such a structure may be formed by the manufacturing operations described above.

FIG. 10A shows a plan view of an SRAM cell. Fig. 10B is a perspective view of the area AR corresponding to fig. 10A. The cell boundary of one SRAM cell is shown by SC. Within one SRAM cell, there are two gates 230 and four fin structures 202. First conductivity type S/D structures 220 and second conductivity type S/D structures 221 are formed over the fin structure between the gates. In one embodiment, the first conductivity type is p-type and the second conductivity type is n-type. In another embodiment, the first conductivity type is n-type and the second conductivity type is p-type.

Similar to fig. 1A-1C, a fin structure 202 including a bottom portion 203 and an upper portion 204 is disposed over a substrate 201. The bottom portion 203 is embedded within the insulating spacer layer 205 and the upper portion 204 protrudes from the insulating spacer layer 205. Gate capping layers 234 are formed on the gates 230, respectively, and the gate capping layers 234 and the gates 230 are disposed between the sidewall spacers 232. A first insulating layer 222 covers the S/D structures and a first sacrificial layer 215 is formed over the S/D structures between the gate structures covered by the first insulating layer 222.

Fig. 10C to 10E are sectional views corresponding to lines Y21-Y21, Y22-Y22, and Y23-Y23 of fig. 10A, respectively. At this stage of the fabrication operation, some S/D structures undesirably merge with one or two adjacent S/D structures due to the narrower separation between adjacent fin structures. For example, when the spacing S between two adjacent fin structures_finBelow about 100nm, the epitaxially formed layers of adjacent S/D structures tend to merge.

In the cross-sectional view shown in fig. 10C corresponding to line Y21-Y21, adjacent second conductivity type S/D structures 221 (more specifically, epitaxially formed layers) merge. In the cross-sectional view corresponding to the line Y22-Y22 shown in fig. 10D, the adjacent second conductive-type S/D structures 221 (more specifically, the epitaxial formation layers) are merged, and the adjacent first conductive-type S/D structures 220 are respectively merged with the second conductive-type S/D structures. In the cross-sectional view shown in fig. 10E corresponding to line Y23-Y23, adjacent second conductivity type S/D structures 221 merge, adjacent first conductivity type S/D structures 220 merge, and adjacent first conductivity type S/D structures respectively merge with the second conductivity type S/D structures. Some of the merged S/D structures will be separated by the following operations. In some embodiments, a void 269 is formed beneath the merged portion of the S/D structure. In other embodiments, one S/D structure is not merged with a neighboring S/D structure, but is in close proximity to a neighboring S/D structure (e.g., less than about 3nm), which may cause current leakage through electrical breakdown. Embodiments of the present application are applicable to such close proximity S/D structures.

Fig. 11A and 11B illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the application. Fig. 11A is a perspective view corresponding to line Y23-Y23 of fig. 10A and 10B, and fig. 11B is a sectional view corresponding to line Y23-Y23 of fig. 10A and 10B.

Similar to fig. 2A-2C, first sacrificial layer 215 is at least partially removed from both side regions of S/D structures 220 and 221 to form opening 216 and expose first insulating layer 222. In some embodiments, all of first sacrificial layer 215 is removed.

Fig. 12A and 12B illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the application. Fig. 12A is a perspective view corresponding to line Y23-Y23 of fig. 10A and 10B, and fig. 12B is a sectional view corresponding to line Y23-Y23 of fig. 10A and 10B.

Similar to fig. 3A to 3C, after the opening 216 is formed, the second sacrificial layer 240 is formed in the opening 216.

Fig. 13 illustrates an exemplary view of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

Similar to fig. 4A to 4C, after the second sacrificial layer 240 is formed, the second sacrificial layer 240 and the gate structure are formedA mask pattern 242 is formed thereon. In some embodiments, the portion of the mask pattern 242 over the S/D structure has a width W in a range from about 10nm to about 40nm_hm。

The second sacrificial layer 240, the first insulating layer 222, and the S/D structures 220 and 221 are anisotropically etched by using the mask pattern 242 as an etch mask, thereby forming openings 244 adjacent to the patterned second sacrificial layer 240 and the S/D structures 220 and 221.

By this etching operation, at least one side of the S/D structures 220 and 221 is removed such that the etched sides of the S/D structures 220 and 221 are substantially parallel to the sides of the upper fin structure 204.

Fig. 14 illustrates an exemplary view of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

Similar to fig. 5A to 5C, the mask pattern 242 is removed by using a suitable etching operation and/or a planarization operation such as CMP.

Fig. 15A and 15B illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the application. Fig. 15A is a perspective view corresponding to line Y23-Y23 of fig. 10A and 10B, and fig. 15B is a sectional view corresponding to line Y23-Y23 of fig. 10A and 10B.

Similar to fig. 6A-6C, after the mask pattern 242 is removed, a second insulation layer 246 is formed over the patterned second sacrificial layer 240 and the patterned S/D structures 220 and 221. As shown in fig. 15A and 15B, a second insulating layer 246 is also formed on the sidewall spacers 232 and the gate cap layer 234. In some embodiments, no silicide layer is formed on the patterned S/D structures at this stage of the fabrication operation. In other embodiments, a silicide layer is formed on the patterned S/D structure prior to forming the second insulating layer.

Fig. 16A and 16B illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the application. Fig. 16A is a perspective view corresponding to line Y23-Y23 of fig. 10A and 10B, and fig. 16B is a sectional view corresponding to line Y23-Y23 of fig. 10A and 10B.

Similar to fig. 7A-7C, after forming the second insulating layer 246, a first interlayer dielectric (ILD) layer 245 is formed to fill the opening 244 and cover the second sacrificial layer 240 and the S/D structure. A planarization process, such as a CMP process, is performed to remove excess material of ILD layer 245 and portions of second insulating layer 246. In some embodiments, the upper surface of the second sacrificial layer 240 (and the cap insulating layer 234) is exposed by a planarization process.

Fig. 17A and 17B illustrate exemplary views of one of the various stages for fabricating a FinFET device, according to some embodiments of the application. Fig. 17A is a perspective view corresponding to line Y23-Y23 of fig. 10A and 10B, and fig. 17B is a sectional view corresponding to line Y23-Y23 of fig. 10A and 10B.

Similar to fig. 8A to 8C, the second sacrificial layer 240 is removed.

Fig. 18 illustrates an exemplary view of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

Similar to fig. 8A to 8C, after removing the second sacrificial layer 240, the first insulating layer 222 remaining on the top or side of the S/D structure is removed, thereby forming a contact opening 248. As shown in fig. 18, each of the contact openings 248 is defined by a second insulating layer 246 and a sidewall spacer 232.

Fig. 19 illustrates an exemplary view of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

Similar to fig. 9A-9C, after forming contact openings 248, silicide layers 227 are formed on the exposed top and sides of S/D structures 220 and 221.

Fig. 20 illustrates an exemplary view of one of the various stages for fabricating a FinFET device, according to some embodiments of the present application.

Similar to fig. 9A-9C, contacts 250 are formed in the contact openings 248 to contact the silicide layers 227 formed on the top and sides of the S/D structures.

After forming the contacts 250, a CMOS process is further performed to form various components such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers.

FIG. 21A shows a plan view of the SRAM cell after contacts are formed. Fig. 21B to 21D are sectional views corresponding to lines Y21-Y21, Y22-Y22, and Y23-Y23 of fig. 20 and 21A, respectively. It should be noted that fig. 21A only shows the fin structure 202, the gate 230, and the S/D structures 220 and 221.

In fig. 21B, only one side of the epitaxial layer of the first conductive type S/D structure 220 has an etched surface, and both sides of the epitaxial layer of the second conductive type S/D structure 221 have etched surfaces. Accordingly, the first conductivity type S/D structure 220 has an asymmetric cross-section along the Y-direction relative to the fin structure 204. In some embodiments, the distance D between the etched surface at one side and the fin structure 204₁Is the distance D between the unetched surface at the other side (the furthest point from the fin structure) and the fin structure 204₂From about 10% to about 70%. In other embodiments, distance D₁Is a distance D₂From about 20% to about 50%.

The second conductivity type S/D structure 221 has a substantially symmetrical cross-section along the Y-direction with respect to the fin structure 204. However, the second conductive type S/D structure 221 may have a slightly asymmetric cross section due to process variations such as an overlay error in a photolithography operation. In this case, in some embodiments, the distance D between the etched surface at one side and the fin structure 204₃Is the distance D between the etched surface at the other side and the fin structure 204₄From about 60% to about 140%. In other embodiments, distance D₃Is a distance D₄From about 90% to about 110%.

In fig. 21C, only one side portion of the epitaxial layer of the first conductive type S/D structure 220 has an etched surface, similar to fig. 21B. The epitaxial layers of the second conductive type S/D structure 221 are merged at one side and the other side has an etched surface.

In fig. 21D, this cross section includes a first conductive S/D structure 220, where only one side of the epitaxial layer has an etched surface, the first conductive S/D structure 220 merging with an adjacent second conductive S/D structure 221, where each of the first conductive S/D structure 220 and the second conductive S/D structure 221 has an etched surface.

It should be noted that as shown in fig. 21B to 21D, voids 270, 271 and 272 may be formed below the S/D structure.

As described above, the S/D structure shown in fig. 21B to 21D may exist in one semiconductor device, for example, an SRAM. The structures shown in fig. 9A to 9C may be included in the same semiconductor device. In addition, the same semiconductor device may also include an S/D structure having an unetched surface, similar to the structures shown in fig. 10C to 10E.

Fig. 22A to 22B illustrate exemplary cross-sectional views of semiconductor devices according to other embodiments of the present application.

In the above embodiments, one or more epitaxial layers are formed on the upper portion 104 or 204 of the fin structure as the S/D structure 120, 220, or 221. In the embodiment shown in fig. 22A, one or more epitaxial layers are formed such that the upper portion 104 or 204 of the fin structure is recessed below the upper surface of the ILD layer 205, and then one or more epitaxial layers 320 or 321 are formed on the recessed fin structure.

In fig. 22B, the fin structure 104 or 204 is replaced with a stacked layer of a first semiconductor layer 301 and a second semiconductor layer 302 for a gate all around FET, wherein the channel of the FET is a nanowire of the first semiconductor layer or the second semiconductor layer, each of which is surrounded by a gate dielectric layer and a gate electrode.

Fig. 23-28 illustrate various stages of a semiconductor device fabrication process according to one or more embodiments of the present application. It should be understood that additional operations may be provided before, during, and after the processes shown in fig. 23-28, and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/processes may be interchanged. The same or similar materials, configurations, dimensions, and/or processes as those of the above-described embodiment described with reference to fig. 1A to 22B may be employed in the following embodiments, and thus detailed descriptions may be omitted.

As shown in fig. 23, after the structures shown in fig. 10A to 10E are formedA mask pattern 342 is formed on the first sacrificial layer 215. The mask pattern 342 is made of a material different from the first sacrificial layer 215 and includes SiO₂、SiCN、SiON、Al₂O₃、SiN、TiN、TaN、TiO₂One or more layers of Si, Ge, SiGe, SiC or other suitable material. In some embodiments, multiple patterning operations using two or more mask layers are used to form the mask patterns.

As shown in fig. 24, the first sacrificial layer 215, the first insulating layer 222, and the S/D structures 220 and 221 are anisotropically etched by using the mask pattern 342 as an etching mask, thereby forming openings 344 separating adjacent S/D structures. In some embodiments, multiple etching operations are performed. For example, an initial etch operation etches the first sacrificial layer 215 and stops on the first insulating layer 222. A subsequent etching operation etches the first sacrificial layer 215 and the epitaxial layers of the S/D structure. The etch mask used for the initial etch and the subsequent etch may be the same (using the same layer of the mask pattern) or different (using a different layer of the mask pattern).

At least one side of the S/D structures 220 and 221 is removed by an etching operation such that the etched sides of the S/D structures 220 and 221 are substantially parallel to the sides of the upper fin structure 204. The mask pattern 342 is removed by using a suitable etching operation and/or a planarization operation such as CMP.

As shown in fig. 25, after removing the mask pattern 342, a second insulating layer 346 is formed over the patterned first sacrificial layer 215 and the patterned S/D structures 220 and 221.

After the insulating layer 346 is formed, a first interlayer dielectric (ILD) layer 345 is formed to fill the opening 344 and cover the first sacrificial layer 215 and the S/D structure. A planarization process, such as a CMP process, is performed to remove excess material of the ILD layer 345 and a portion of the second insulating layer 346. In some embodiments, as shown in fig. 26, the upper surface of the first sacrificial layer 215 is exposed by a planarization process.

Subsequently, as shown in fig. 27, the first sacrificial layer 215 is removed by using a suitable etching operation, thereby forming an opening 348. In some embodiments, a wet etch operation is used.

After removing the first sacrificial layer 215, the remaining first insulating layer 222 on the top or side of the S/D structure is removed, thereby exposing the S/D structure, and a silicide layer 227 is formed on the exposed top and side of the S/D structures 220 and 221. Subsequently, contacts 250 are formed to contact the silicide layers 227 formed on the top and sides of the S/D structure.

After forming the contacts 250, a CMOS process is further performed to form various components such as additional interlayer dielectric layers, contacts/vias, interconnect metal layers, and passivation layers.

It is to be understood that not all advantages need be discussed herein, that no particular advantage is required for all embodiments or examples, and that other embodiments or examples may provide different advantages.

For example, in the present application, once the merged epitaxial layers of the source/drain structures due to narrow separation of adjacent fin structures are separated by a subsequent patterning operation, and thus the device area may be reduced without causing shorting problems between adjacent finfets. In addition, since a material having a higher etching selectivity (e.g., Si) is used as the second sacrificial layer in the separation patterning, the size of the etched S/D structure can be more precisely controlled.

In accordance with one aspect of the present application, in a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure and an isolation insulating layer of the FinFET structure. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming an opening adjacent to the patterned sacrificial layer and the patterned source/drain structure. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned sacrificial layer is removed to form contact openings over the patterned source/drain structures. A conductive layer is formed in the contact opening.

In the above method, wherein a first insulating layer is formed over the source/drain structure and the isolation insulating layer before the sacrificial layer is formed.

In the above method, wherein the sacrificial layer is made of one or more of group IV element or compound material.

In the above method, wherein the sacrificial layer is made of one or more of a silicon-based dielectric material or an aluminum-based dielectric material.

In the above method, further comprising, after patterning the sacrificial layer and the source/drain structures and before forming the dielectric layer: a second insulating layer is formed over the patterned sacrificial layer and the patterned source/drain structures.

In the above method, further comprising, after patterning the sacrificial layer and the source/drain structures and before forming the dielectric layer: forming a second insulating layer over the patterned sacrificial layer and the patterned source/drain structures, after patterning the sacrificial layer and the source/drain structures and before forming the second insulating layer: a silicide layer is formed over the patterned source/drain structures.

In the above method, further comprising, after patterning the sacrificial layer and the source/drain structures and before forming the dielectric layer: forming a second insulating layer over the patterned sacrificial layer and the patterned source/drain structure, wherein the sacrificial layer is made of a different material than the isolation insulating layer, the first insulating layer, and the second insulating layer.

In the above method, wherein: the source/drain structure includes a fin structure and one or more epitaxial layers formed on two opposing sides and a top of the fin structure, and the source/drain structure is patterned such that the one or more epitaxial layers formed on at least one of the sides are partially etched.

In the above method, wherein: the source/drain structure includes a fin structure and one or more epitaxial layers formed on two opposing sides and a top of the fin structure, and the source/drain structure is patterned such that the one or more epitaxial layers formed on at least one of the sides are partially etched, wherein the source/drain structure is patterned such that the one or more epitaxial layers formed on both of the sides are partially etched.

In the above method, wherein: the source/drain structure includes a fin structure embedded within the isolation insulating layer and one or more epitaxial layers formed on top of the fin structure, and the source/drain structure is patterned such that the one or more epitaxial layers are partially etched.

In accordance with another aspect of the present application, in a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a first source/drain structure of a first FinFET structure, a second source/drain structure of a second FinFET structure, and an isolation insulating layer. The first source/drain structure and the second source/drain structure merge. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the first and second source/drain structures are patterned by using the mask pattern as an etching mask, thereby separating the first and second source/drain structures and forming an opening adjacent to the patterned sacrificial layer and the patterned first and second source/drain structures. A dielectric layer is formed in the opening. After forming the dielectric layer, the patterned sacrificial layer is removed to form contact openings over the patterned first source/drain structure and the patterned second source/drain structure, respectively. A conductive layer is formed in the contact opening.

In the above method, wherein the first source/drain structure has the same conductivity type as the second source/drain structure.

In the above method, wherein the first source/drain structure has a different conductivity type than the second source/drain structure.

In the above method, wherein a first insulating layer is formed over the combined first and second source/drain structures and the isolation insulating layer before the sacrificial layer is formed.

In the above method, wherein the sacrificial layer is made of at least one of Si, SiGe and Ge.

In the above method, wherein the sacrificial layer is made of SiOC, SiC, SiON, SiCN, SiOCN, SiN and SiO₂Is prepared by at least one of (1).

In the above method, further comprising, after patterning the sacrificial layer and the first and second source/drain structures and before forming the dielectric layer: a second insulating layer is formed over the patterned sacrificial layer and the patterned first and second source/drain structures.

In the above method, further comprising, after patterning the sacrificial layer and the first and second source/drain structures and before forming the dielectric layer: forming a second insulating layer over the patterned sacrificial layer and the patterned first and second source/drain structures, wherein the sacrificial layer is made of a different material than the isolation insulating layer, first insulating layer, and second insulating layer.

In the above method, wherein: the first source/drain structure comprises a first epitaxial layer and the second source/drain structure comprises a second epitaxial layer, the first epitaxial layer merging with the second epitaxial layer, and patterning the first source/drain structure and the second source/drain structure such that the merged first epitaxial layer and second epitaxial layer are separated.

According to another aspect of the present application, a semiconductor device including a fin field effect transistor (FinFET) includes a first FinFET including a first fin structure and a first source/drain structure extending in a first direction, a second FinFET disposed adjacent to the first FinFET and including a second fin structure and a second source/drain structure extending in the first direction, and a dielectric layer separating the first source/drain structure and the second source/drain structure. The first source/drain structure is asymmetric with respect to the first fin structure in a cross-section along a second direction that intersects the first direction.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present application. Those skilled in the art should appreciate that they may readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced by oneself. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present application, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present application.