阅读说明：本技术 垂直存储器件 (Vertical memory device ) 是由 姜相敏 H.杨 崔至薰 于 2021-06-09 设计创作，主要内容包括：一种垂直存储器件包括：在衬底上的沟道,沟道在垂直于衬底的上表面的垂直方向上延伸；在沟道的外侧壁上的电荷存储结构,电荷存储结构包括在平行于衬底的上表面的水平方向上顺序堆叠的隧道绝缘图案、电荷存储图案和第一阻挡图案；以及在衬底上在该垂直方向上彼此间隔开的栅电极,每个栅电极围绕电荷存储结构。第一阻挡图案包括含有卤素元素的硅氧化物,包括在第一阻挡图案中的卤素元素的浓度从第一阻挡图案的面对栅电极中的相应栅电极的外侧壁朝向第一阻挡图案的面对电荷存储图案的内侧壁降低。(A vertical memory device includes: a channel on the substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate; a charge storage structure on an outer sidewall of the channel, the charge storage structure including a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to an upper surface of the substrate; and gate electrodes spaced apart from each other in the vertical direction on the substrate, each gate electrode surrounding the charge storage structure. The first barrier patterns include silicon oxide containing a halogen element, and a concentration of the halogen element included in the first barrier patterns decreases from outer sidewalls of the first barrier patterns facing the respective ones of the gate electrodes toward inner sidewalls of the first barrier patterns facing the charge storage patterns.)

1. A vertical memory device, comprising:

a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate;

a charge storage structure on an outer sidewall of the channel, the charge storage structure including a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate; and

a plurality of gate electrodes spaced apart from each other in the vertical direction on the substrate, each of the gate electrodes surrounding the charge storage structure,

wherein the first barrier pattern comprises a silicon oxide containing a halogen element, an

Wherein a concentration of the halogen element included in the first barrier pattern decreases from an outer sidewall of the first barrier pattern facing a corresponding gate electrode of the plurality of gate electrodes toward an inner sidewall of the first barrier pattern facing the charge storage pattern.

2. The vertical memory device of claim 1, wherein a concentration of the halogen element at the inner sidewall of the first barrier pattern is less than or equal to 1/5 of a concentration of the halogen element at the outer sidewall of the first barrier pattern.

3. The vertical memory device according to claim 1, wherein the concentration of the halogen element in the first barrier pattern gradually decreases from the outer sidewall toward the inner sidewall until a central portion in the horizontal direction, and is uniform from the central portion to the inner sidewall.

4. The vertical memory device according to claim 1, wherein the first barrier pattern comprises chlorine as the halogen element.

5. The vertical memory device of claim 1, wherein the first barrier pattern is free of nitrogen.

6. The vertical memory device of claim 1, wherein a thickness of the first barrier pattern in the horizontal direction is uniform along the vertical direction such that both the outer sidewall and the inner sidewall of the first barrier pattern are flat.

7. The vertical memory device of claim 1, further comprising a second blocking pattern covering a lower surface and an upper surface of each of the gate electrodes and sidewalls facing the charge storage structure, the second blocking pattern comprising a metal oxide.

8. The vertical memory device of claim 1, wherein a lowermost gate electrode of the plurality of gate electrodes is a ground select line, an uppermost gate electrode of the plurality of gate electrodes and at least one gate electrode directly below the uppermost gate electrode respectively serve as string select lines, and gate electrodes of the plurality of gate electrodes between the ground select line and the string select line respectively serve as word lines.

9. A vertical memory device, comprising:

a channel on a substrate, the channel extending in a vertical direction perpendicular to an upper surface of the substrate;

a charge storage structure on an outer sidewall of the channel, the charge storage structure including a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate, the first blocking pattern including a halogen element; and

a plurality of gate electrodes spaced apart from each other in the vertical direction on the substrate, each of the gate electrodes surrounding the charge storage structure,

wherein a thickness of the first barrier pattern in the horizontal direction is uniform in the vertical direction such that both outer and inner sidewalls of the first barrier pattern are flat, an

Wherein a concentration of the halogen element at the inner sidewall of the first barrier pattern is less than a concentration of the halogen element at the outer sidewall of the first barrier pattern.

10. The vertical memory device of claim 9, wherein the concentration of the halogen element at the inner sidewall of the first barrier pattern is less than or equal to 1/5 of the concentration of the halogen element at the outer sidewall of the first barrier pattern.

11. The vertical memory device according to claim 9, wherein the concentration of the halogen element in the first barrier pattern gradually decreases from the outer sidewall toward the inner sidewall until a central portion in the horizontal direction, and is uniform from the central portion to the inner sidewall.

12. The vertical memory device according to claim 9, wherein the halogen element of the first barrier pattern comprises chlorine.

13. The vertical memory device of claim 9, wherein the first barrier pattern is free of nitrogen.

14. The vertical memory device of claim 9, further comprising a second blocking pattern covering a lower surface and an upper surface of each of the gate electrodes and sidewalls facing the charge storage structure, the second blocking pattern comprising a metal oxide.

15. A vertical memory device, comprising:

channels on a substrate, each of the channels extending in a first direction perpendicular to an upper surface of the substrate;

a channel connection pattern on the substrate, the channel connection pattern contacting the channel;

a charge storage structure on an outer sidewall of each of the channels on the channel connection pattern, the charge storage structure including a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction parallel to the upper surface of the substrate;

a plurality of gate electrodes spaced apart from each other in the first direction on the channel connection pattern, each of the gate electrodes surrounding the charge storage structure;

dividing patterns on the substrate, each of the dividing patterns passing through the gate electrode and extending in a second direction parallel to the upper surface of the substrate to separate each of the gate electrodes in a third direction parallel to the upper surface of the substrate and crossing the second direction; and

bit lines spaced apart from each other in the second direction, each of the bit lines extending in the third direction over the channel, the bit lines electrically connected to the channel,

wherein the first barrier pattern comprises a silicon oxide containing a halogen element, an

Wherein a concentration of the halogen element included in the first barrier pattern decreases from an outer sidewall of the first barrier pattern facing a corresponding gate electrode of the plurality of gate electrodes toward an inner sidewall of the first barrier pattern facing the charge storage pattern.

16. The vertical memory device of claim 15, wherein a concentration of the halogen element at the inner sidewall of the first barrier pattern is less than or equal to 1/5 of a concentration of the halogen element at the outer sidewall of the first barrier pattern.

17. The vertical memory device according to claim 15, wherein the concentration of the halogen element in the first barrier pattern gradually decreases from the outer sidewall toward the inner sidewall until a central portion in the horizontal direction, and is uniform from the central portion to the inner sidewall.

18. The vertical memory device of claim 15, wherein the first barrier pattern is nitrogen-free.

19. The vertical memory device of claim 15, wherein a thickness of the first barrier pattern in the horizontal direction is uniform along the first direction such that both the outer sidewall and the inner sidewall of the first barrier pattern are planar.

20. The vertical memory device of claim 15, further comprising a second blocking pattern covering a lower surface and an upper surface of each of the gate electrodes and sidewalls facing the charge storage structure, the second blocking pattern comprising a metal oxide.

Technical Field

The present disclosure relates to a memory device, and more particularly, to a vertical memory device and a method of fabricating the same.

Background

In a method of manufacturing a VNAND flash memory device, a channel hole may be formed to expose an upper surface of a substrate through a mold including an insulation layer and a sacrificial layer that are alternately stacked. A preliminary barrier layer comprising silicon nitride may be formed on sidewalls and a bottom of the channel hole and oxidized to form a barrier layer. If the preliminary barrier layer is oxidized by the thermal oxidation process, nitrogen included in the preliminary barrier layer may not be easily removed, and thus a radical oxidation process may be performed. However, when the radical oxidation process is performed, a portion of the sacrificial layer including nitride may also be oxidized, so that the surface of the barrier layer may not be flat in the horizontal direction and the barrier layer may be unevenly formed in the vertical direction.

Disclosure of Invention

A method of manufacturing a vertical memory device includes alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate to form a mold. A channel hole is formed through the mold to expose an upper surface of the substrate. A first deposition process is performed using both the first precursor and the second precursor to form a first preliminary barrier layer on sidewalls and a bottom of the trench hole. The first precursor includes silane, and the second precursor includes silane and a halogen element. A second deposition process is performed using the first precursor to form a second preliminary barrier layer on sidewalls and a bottom of the trench hole. The first preliminary barrier layer and the second preliminary barrier layer form a third preliminary barrier layer. And performing an oxidation process on the third preliminary barrier layer so that the third preliminary barrier layer is transformed into the first barrier layer. The charge storage layer, the tunnel insulating layer, and the channel layer are sequentially stacked on the first barrier layer. The first blocking layer, the charge storage layer and the tunnel insulating layer form a charge storage layer structure. The sacrificial layer is removed to form a gap exposing outer sidewalls of the charge storage layer structure. A gate electrode is formed in the gap.

A method of manufacturing a vertical memory device includes forming a mold by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate. A channel hole is formed through the mold to expose an upper surface of the substrate. A first deposition process is performed using a first precursor to form a seed layer on sidewalls and a bottom of the trench hole. The first precursor includes a silane including a nitrogen-containing functional group. A second deposition process is performed using both the second precursor and the third precursor to form a first preliminary barrier layer on sidewalls and a bottom of the channel hole. The second precursor includes silane, and the third precursor includes silane and a halogen element. The second deposition process is performed at a low temperature of less than or equal to about 400 ℃. An oxidation process is performed on the first preliminary barrier layer such that the first preliminary barrier layer is transformed into a barrier layer. A charge storage layer, a tunnel insulation layer, and a channel layer are sequentially stacked on the blocking layer. The blocking layer, the charge storage layer and the tunnel insulating layer form a charge storage layer structure. The sacrificial layer is removed to form a gap exposing outer sidewalls of the charge storage layer structure. A gate electrode is formed in the gap.

A method of manufacturing a vertical memory device includes forming a mold by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate. A channel hole is formed through the mold to expose an upper surface of the substrate. A first deposition process is performed using a first precursor to form a seed layer on sidewalls and a bottom of the trench hole. The first precursor includes a silane having a nitrogen-containing functional group. A second deposition process is performed using both the second precursor and the third precursor to form a first preliminary barrier layer on sidewalls and a bottom of the channel hole. The second precursor includes silane, and the third precursor includes silane and a halogen element. A third deposition process is performed using the second precursor to form a second preliminary barrier layer on the sidewalls and bottom of the trench hole. The first preliminary barrier layer and the second preliminary barrier layer form a third preliminary barrier layer. And performing an oxidation process on the third preliminary barrier layer so that the third preliminary barrier layer is transformed into the first barrier layer. The charge storage layer, the tunnel insulating layer, and the channel layer are sequentially stacked on the first blocking layer, and the first blocking layer, the charge storage layer, and the tunnel insulating layer form a charge storage layer structure. The sacrificial layer is removed to form a gap exposing outer sidewalls of the charge storage layer structure. A gate electrode is formed in the gap.

A vertical memory device includes a channel, a charge storage structure, and a gate electrode. The channel is formed on the substrate and extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The charge storage structure is formed on an outer sidewall of the channel and includes a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate. The gate electrodes are spaced apart from each other in a vertical direction on the substrate. Each gate electrode surrounds a charge storage structure. The first barrier pattern includes silicon oxide containing a halogen element. The concentration of the halogen element included in the first barrier pattern decreases from an outer sidewall facing a corresponding one of the gate electrodes toward an inner sidewall facing the charge storage pattern.

A vertical memory device includes a channel, a charge storage structure, and a gate electrode. The channel is formed on the substrate and extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The charge storage structure is formed on an outer sidewall of the channel and includes a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate. The first barrier pattern includes a halogen element. The gate electrodes are spaced apart from each other in a vertical direction on the substrate. Each gate electrode surrounds a charge storage structure. The thickness of the first barrier pattern in the horizontal direction is substantially uniform in the vertical direction, so that both the outer sidewall and the inner sidewall of the first barrier pattern are substantially flat (e.g., planar). The concentration of the halogen element at the inner sidewall of the first barrier pattern is less than the concentration of the halogen element at the outer sidewall of the first barrier pattern.

A vertical memory device includes a channel, a channel connection pattern, a charge storage structure, a gate electrode, a partition pattern, and a bit line. The channel is formed on the substrate. Each channel extends in a first direction substantially perpendicular to the upper surface of the substrate. A channel connection pattern is formed on the substrate and contacts the channel. The charge storage structure is formed on the channel connection pattern on an outer sidewall of each channel, and includes a tunnel insulation pattern, a charge storage pattern, and a first blocking pattern sequentially stacked in a horizontal direction substantially parallel to an upper surface of the substrate. The gate electrodes are spaced apart from each other in the first direction on the channel connection pattern. Each gate electrode surrounds a charge storage structure. The division pattern is formed on the substrate. Each of the division patterns passes through the gate electrode and extends in a second direction substantially parallel to the upper surface of the substrate to separate each of the gate electrodes in a third direction substantially parallel to the upper surface of the substrate and crossing the second direction. The bit lines are spaced apart from each other in a second direction. Each bit line extends in a third direction over the channel. A bit line is electrically connected to the channel. The first barrier pattern includes silicon oxide containing a halogen element. The concentration of the halogen element included in the first barrier pattern decreases from an outer sidewall facing a corresponding one of the gate electrodes toward an inner sidewall facing the charge storage pattern.

Drawings

A more complete appreciation of the present disclosure and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

fig. 1 to 13 are sectional views illustrating a method of fabricating a vertical memory device according to an exemplary embodiment of the present disclosure; and

fig. 14 is a graph illustrating the concentration of chlorine remaining in the first barrier pattern according to the distance from the sidewall of the channel hole when the second deposition process for forming the first preliminary barrier layer is performed using Dichlorosilane (DCS) as the third precursor.

Detailed Description

The above and other aspects and features of the vertical memory device and the method of fabricating the same according to the exemplary embodiments of the present disclosure will be readily understood from the following detailed description, with reference to the accompanying drawings. Hereinafter, in the specification, a direction substantially perpendicular to the upper surface of the substrate may be referred to as a first direction, and two directions substantially parallel to the upper surface of the substrate and crossing each other may be referred to as a second direction and a third direction, respectively. In an exemplary embodiment of the present disclosure, the second direction and the third direction may be substantially perpendicular to each other.

Fig. 1 to 13 are sectional views illustrating a method of fabricating a vertical memory device according to an exemplary embodiment of the present disclosure.

Referring to fig. 1, a sacrificial layer structure 140 may be formed on a substrate 100. The sacrificial layer structure 140 may be partially removed to form a first opening 150 exposing the upper surface of the substrate 100. A support layer 160 may be formed on the substrate 100 and the sacrificial layer structure 140 to at least partially fill the first opening 150.

The substrate 100 may comprise silicon, germanium, silicon germanium, or a group III-V compound such as GaP, GaAs, GaSb, or the like. In some example embodiments of the present disclosure, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. For example, n-type impurities may be doped into the substrate 100.

The sacrificial layer structure 140 may include first to third sacrificial layers 110, 120 and 130 sequentially stacked in a first direction on the substrate 100. Each of the first and third sacrificial layers 110 and 130 may include an oxide, for example, silicon oxide, and the second sacrificial layer 120 may include a nitride, for example, silicon nitride.

The support layer 160 may include a material having an etch selectivity with respect to the first to third sacrificial layers 110, 120 and 130, for example, doped or undoped polysilicon. In some exemplary embodiments of the present disclosure, the support layer 160 may be formed by depositing doped or undoped amorphous silicon and crystallized to include doped or undoped polysilicon by performing a heat treatment or by heat generated during a deposition process for other structures.

The support layer 160 may have a uniform thickness, and thus a first recess may be formed on a portion of the support layer 160 in the first opening 150. Hereinafter, a portion of the support layer 160 in the first opening 150 may be referred to as a support pattern 165.

An insulating layer 170 may be formed on the support layer 160. The insulating layer 170 may fill a portion of the first opening 150 that is not yet filled with the support pattern 165. The upper surface of the insulating layer 170 may be planarized by a planarization process. The planarization process may include a Chemical Mechanical Polishing (CMP) process and/or an etch back process. The planarized insulating layer 170 may be referred to herein as a first insulating layer 170.

The fourth sacrificial layer 180 and the insulating layer 170 may be alternately and repeatedly formed on the first insulating layer 170, and thus a mold layer may be formed on the substrate 100. The insulating layer 170 may include an oxide, for example, silicon oxide, and the fourth sacrificial layer 180 may include a material having an etch selectivity with respect to the insulating layer 170, for example, a nitride, such as silicon nitride.

A patterning process using the photoresist pattern as an etching mask may be performed on the insulating layer 170 and the fourth sacrificial layer 180, and a trimming process for reducing an area of the photoresist pattern may also be performed. The patterning process and the trimming process may be alternately and repeatedly performed to form a mold having a plurality of step layers, each of which includes the fourth sacrificial layer 180 and the insulating layer 170 sequentially stacked on the substrate 100.

Referring to fig. 2, a first insulating interlayer 190 may be formed on the substrate 100 to cover the mold, and a channel hole 200 may be formed through the first insulating interlayer 190 and the mold by, for example, a dry etching process to expose an upper surface of the substrate 100.

In an exemplary embodiment of the present disclosure, a dry etching process may be performed until an upper surface of the substrate 100 may be exposed, and an upper portion of the substrate 100 may be further removed in the dry etching process. In the exemplary embodiment of the present disclosure, a plurality of channel holes 200 may be formed in each of the second and third directions, and thus a channel hole array may be defined.

A seed layer 210 including silicon may be formed on the sidewalls and bottom of the trench hole 200, and a portion of the seed layer 210 may also be formed on the upper surface of the first insulating interlayer 190.

In an exemplary embodiment of the present disclosure, the seed layer 210 may be formed by a first deposition process using a first precursor, which may include silane having a functional group containing nitrogen. For example, the first precursor may include Diisopropylaminosilane (DIPAS), Dipropylaminosilane (DPAS), Dimethylaminosilane (DMAS), Diethylaminosilane (DEAS), di (tert-butylamino) silane (DTBAS), and the like. Accordingly, the seed layer 210, which may be formed by the first deposition process, may include nitrogen as well as silicon.

Referring to fig. 3, a first preliminary barrier layer 220 including silicon may be formed on sidewalls and a bottom of the trench hole 200.

In an exemplary embodiment of the present disclosure, the first preliminary barrier layer 220 may be formed by a second deposition process using a second precursor and a third precursor (each of which may include silicon). The second precursor may include, for example, Monosilane (MS), and the third precursor may include silane and a halogen element, such as fluorine, chlorine, bromine, iodine, and the like.In particular, the third precursor may include, for example, difluorosilane (SiH)₂F₂) Dichlorosilane (DCS) (SiH)₂Cl₂) Dibromosilane (SiH)₂Br₂) Diiodosilane (SiH)₂I₂) And the like.

During the second deposition process, the halogen element may be pyrolyzed (pyrolized) from the third precursor, and the decomposed halogen element may remove the functional group including nitrogen on the surface of the seed layer 210 and a portion, mainly an upper portion, of the first preliminary barrier layer 220. Accordingly, a lower portion of the first preliminary barrier layer 220 may be thicker than an upper portion thereof, and the first preliminary barrier layer 220 may not be formed on the upper surface of the first insulating interlayer 190.

In general, if the second deposition process is performed using only the second precursor without using the third precursor, the thickness of a layer deposited at the upper portion of the channel hole 200 may increase, and thus the entrance of the channel hole 200 may be narrowed, so that the layer may not be formed at the lower portion of the channel hole 200. However, in the exemplary embodiment of the present disclosure, the second deposition process may be performed using the third precursor and the second precursor together, and thus the thickness of the first preliminary barrier layer 220 deposited at the upper portion of the channel hole 200 may be reduced due to the etching operation of the halogen element included in the third precursor, and the first preliminary barrier layer 220 may be easily deposited at the lower portion of the channel hole 200. Further, a thickness of a portion of the first preliminary barrier layer 220 at a lower portion of the channel hole 200 may be greater than a thickness of a portion of the first preliminary barrier layer 220 at an upper portion of the channel hole 200.

In exemplary embodiments of the present disclosure, the second deposition process may be performed under a hydrogen atmosphere and at a low temperature of less than or equal to about 400 ℃. As described above, the seed layer 210 formed by the first deposition process may include nitrogen, and hydrogen may be used as a catalyst for pyrolyzing halogen elements included in the third precursor on the surface of the seed layer 210 including nitrogen even at a low temperature during the second deposition process. Accordingly, the first preliminary blocking layer 220 may be deposited on the upper portion and the lower portion of the trench hole 200 even at a low temperature under a hydrogen atmosphere.

A purge process may be performed on the substrate 100 having the first preliminary barrier layer 220 thereon.

Referring to fig. 4, a third deposition process using only the second precursor may be performed to form a second preliminary barrier layer on the first preliminary barrier layer 220 and the first insulating interlayer 190. The second preliminary barrier layer, together with the first preliminary barrier layer 220, may form a third preliminary barrier layer 225. Third preliminary barrier layer 225 may include nitrogen-free polysilicon.

The third deposition process may be performed using only the second precursor, and thus the thickness of a portion of the second preliminary barrier layer at the upper portion of the channel hole 200 may be greater than the thickness of a portion of the second preliminary barrier layer at the lower portion thereof. Since a portion of the first preliminary barrier layer 220 at a lower portion of the channel hole 200 is thicker than a portion of the first preliminary barrier layer 220 at an upper portion of the channel hole 200, the third preliminary barrier layer 225 including the first preliminary barrier layer 220 and the second preliminary barrier layer formed by the third deposition process may have a uniform thickness in the channel hole 200.

Referring to fig. 5, an oxidation process may be performed on the third preliminary barrier layer 225, and thus the third preliminary barrier layer 225 may be converted into the first barrier layer 230 including silicon oxide.

In example embodiments of the present disclosure, the oxidation process may be performed by a thermal oxidation process. Alternatively, the oxidation process may be performed by a radical oxidation process.

In exemplary embodiments of the present disclosure, the oxidation process may include a clean oxidation process, a dry oxidation process, a wet oxidation process, and the like.

The third preliminary barrier layer 225 may include polysilicon and may cover sidewalls of the channel hole 200, and thus, a portion of the fourth sacrificial layer 180 including nitride and adjacent to the channel hole 200 may not be oxidized during the oxidation process.

Referring to fig. 6, a charge storage layer 240, a tunnel insulation layer 250, and a channel layer 270 may be sequentially formed on the first blocking layer 230, and a filling layer 280 may be formed on the channel layer 270 to fill the channel hole 200. The first blocking layer 230, the charge storage layer 240, and the tunnel insulating layer 250 sequentially stacked on the sidewall and the bottom of the channel hole 200 may form a charge storage layer structure 260.

The charge storage layer 240 may include a nitride, such as silicon nitride. The tunnel insulating layer 250 may include an oxide, for example, silicon oxide. The channel layer 270 may include, for example, polysilicon. The fill layer 280 may include an oxide, such as silicon oxide.

Referring to fig. 7, the fill layer 280, the channel layer 270, and the charge storage layer structure 260 may be planarized until an upper surface of the first insulating interlayer 190 is exposed to form a fill pattern 285, a channel 275, and a charge storage structure 265 in the channel hole 200, respectively. The charge storage structure 265 may include a first blocking pattern 235, a charge storage pattern 245, and a tunnel insulation pattern 255 sequentially stacked on the sidewall and the bottom of the channel hole 200.

In an exemplary embodiment of the present disclosure, the filling pattern 285 may have a pillar shape extending in the first direction, and each of the channel 275 and the charge storage structure 265 may have a cup shape.

Since the channel holes 200 in which the channels 275 are formed may define an array of channel holes, the channels 275 in the channel holes 200 may also define an array of channels.

An upper portion of the filling pattern 285 and an upper portion of the channel 275 may be removed to form a second recess, a pad layer may be formed on the first insulating interlayer 190 to fill the second recess, and the pad layer may be planarized until an upper surface of the first insulating interlayer 190 may be exposed to form a pad 295.

Referring to fig. 8, a second insulating interlayer 300 may be formed on the first insulating interlayer 190 and the pad 295. The second opening 310 may be formed through the first and second insulating interlayers 190 and 300 and the mold by a dry etching process.

In an exemplary embodiment of the present disclosure, a dry etching process may be performed until an upper surface of the support layer 160 or an upper surface of the support pattern 165 may be exposed, and an upper portion of the support layer 160 or an upper portion of the support pattern 165 may also be removed during the dry etching process. In forming the second opening 310, the insulating layer 170 and the fourth sacrificial layer 180 (e.g., as seen in fig. 7) of the mold may be exposed to create an insulating pattern 175 and a sacrificial pattern 185, as discussed below.

In an exemplary embodiment of the present disclosure, the second opening 310 may extend in the second direction, and a plurality of second openings 310 may be formed in the third direction. When the second opening 310 is formed, the insulating layer 170 may be divided into the insulating patterns 175, each of the insulating patterns 175 may extend in the second direction, and the fourth sacrificial layer 180 may be divided into the fourth sacrificial patterns 185, each of the fourth sacrificial patterns 185 may extend in the second direction.

A spacer layer may be formed on sidewalls of the second opening 310, the exposed upper surface of the substrate 100, and the upper surface of the second insulating interlayer 300, and the spacer layer may be anisotropically etched to remove portions of the spacer layer on the upper surface of the support layer 160 and the upper surface of the support pattern 165, so that the spacers 320 may be formed, and the upper surface of the support layer 160 and the upper surface of the support pattern 165 may be exposed again.

In an exemplary embodiment of the present disclosure, the spacer 320 may include, for example, undoped amorphous silicon or undoped polysilicon. When the spacer 320 includes undoped amorphous silicon, the undoped amorphous silicon may be crystallized in a subsequent deposition process.

Portions of the support layer 160 and the support pattern 165 not covered by the spacers 320 and portions of the sacrificial layer structure 140 thereunder may be removed to enlarge the second opening 310 downward. Accordingly, the second opening 310 may expose the upper surface of the substrate 100 and further extend through the upper portion of the substrate 100.

When the sacrificial layer structure 140 is partially removed, the sidewall of the second opening 310 may be covered by the spacer 320, and the spacer 320 includes a material different from that of the sacrificial layer structure 140, so that the insulating pattern 175 and the fourth sacrificial pattern 185 included in the mold may not be removed.

Referring to fig. 9, the sacrificial layer structure 140 exposed by the second opening 310 may be removed to form a first gap 330 exposing a lower outer sidewall of the charge storage structure 265. The portion of the charge storage structure 265 exposed by the first gap 330 may be further removed to expose a lower outer sidewall of the channel 275.

The sacrificial layer structure 140 and the charge storage structure 265 may be removed by a wet etching process using, for example, hydrofluoric acid or phosphoric acid. When the first gap 330 is formed, the support layer 160, the support pattern 165, the channels 275, and the filling pattern 285 may not be removed so that the mold does not collapse.

When forming the first gap 330, the charge storage structure 265 may be divided into an upper portion extending through the mold to cover most of the outer sidewalls of the channel 275 and a lower portion on the substrate 100 covering the bottom surface of the channel 275.

Referring to fig. 10, after removing the spacer 320, a channel connection pattern 340 may be formed to fill the first gap 330.

The channel connection pattern 340 may be formed by forming a channel connection layer on the substrate 100 and the second insulating interlayer 300 to fill the second opening 310 and the first gap 330, and performing an etch-back process on the channel connection layer. The channel connection layer may include, for example, amorphous silicon doped with n-type impurities, and may be crystallized by heat generated by a subsequent deposition process to include polycrystalline silicon doped with n-type impurities. When the channel connection pattern 340 is formed, channels 275 between second openings 310 adjacent in the third direction among the second openings 310 may be electrically connected to each other to form a channel block.

An air gap 350 may be formed in the channel connection pattern 340.

Referring to fig. 11, for example, an n-type impurity may be implanted into an upper portion of the substrate 100 exposed through the second opening 310 to form the impurity region 105.

The fourth sacrificial pattern 185 may be removed to form a second gap 360 exposing the outer sidewall of the charge storage structure 265. The fourth sacrificial pattern 185 may be removed by a wet etching process using, for example, phosphoric acid or hydrofluoric acid.

Referring to fig. 12, a second barrier layer may be formed on the exposed outer sidewalls of the charge storage structure 265, the inner walls of the second gap 360, the surface of the insulating pattern 175, the sidewalls of the support layer 160 and the support pattern 165, the sidewalls of the channel connection pattern 340, the upper surface of the substrate 100, and the upper surface of the second insulating interlayer 300, and a gate electrode layer may be formed on the second barrier layer. The gate electrode layer may include a gate blocking layer and a gate conductive layer that are sequentially stacked.

The second barrier layer may include, for example, a metal oxide, the gate barrier layer may include a metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like, and the gate conductive layer may include a metal such as tungsten, copper, or the like.

The gate electrode layer may be partially removed to form a gate electrode 380 in each of the second gaps 360. In an exemplary embodiment of the present disclosure, the gate electrode layer may be partially removed by a wet etching process.

In the exemplary embodiment of the present disclosure, the gate electrode 380 may extend in the second direction, and a plurality of gate electrodes 380 may be formed in the first direction, which may form a gate electrode structure. In addition, a plurality of gate electrode structures may be formed in the third direction and may be spaced apart from each other by the second opening 310.

In an exemplary embodiment of the present disclosure, each gate electrode 380 included in the gate electrode structure may function as one of a Ground Selection Line (GSL), a word line, and a String Selection Line (SSL) according to its position. In the exemplary embodiment of the present disclosure, the lowermost one of the gate electrodes 380 may be used as the GSL, the uppermost one of the gate electrodes 380 and the second from above may be respectively used as the SSL, and the plurality of gate electrodes 380 between the GSL and the SSL may be respectively used as the word lines. According to an example embodiment of the present disclosure, one or more gate electrodes 380 may be further formed below the GSL or above the SSL, which may serve as Gate Induced Drain Leakage (GIDL) for body erase (body erase) using the GIDL phenomenon. Some of the gate electrodes 380 used as word lines may be dummy word lines.

A partition layer may be formed on the second barrier layer to fill the second opening 310, and the partition layer and the second barrier layer may be planarized until an upper surface of the second insulating interlayer 300 is exposed. Accordingly, the second barrier layer may be transformed into the second barrier pattern 370, and the division layer may be transformed into the division pattern 390 filling the second opening 310 and extending in the second direction.

Referring to fig. 13, a third insulating interlayer 400 may be formed on the second insulating interlayer 300, the partition pattern 390, and the second barrier pattern 370, and a contact plug 410 may be formed through the second insulating interlayer 300 and the third insulating interlayer 400 to contact the upper surface of the pad 295.

The bit line 420 may be formed on an upper surface of the contact plug 410. In an exemplary embodiment of the present disclosure, the bit lines 420 may extend in the third direction, and the plurality of bit lines 420 may be spaced apart from each other in the second direction.

Upper contact plugs respectively contacting the upper surfaces of the gate electrodes 380 and upper wirings for applying electrical signals thereto may be further formed, so that a vertical memory device may be manufactured.

As described above, the seed layer 210 may be formed on the sidewalls and the bottom of the channel hole 200 through a first deposition process using a first precursor, which may include silane having a nitrogen-containing functional group, the first preliminary barrier layer 220 may be formed on the sidewalls and the bottom of the channel hole 200 through a second deposition process using a second precursor including MS and a third precursor that may include both silane and a halogen element, and the second preliminary barrier layer may be formed on the first preliminary barrier layer 220 through a third deposition process using only the second precursor including MS. The first preliminary barrier layer 220 and the second preliminary barrier layer may form a third preliminary barrier layer 225 including polysilicon, and the third preliminary barrier layer 225 may be formed on sidewalls and a bottom of the trench hole 200. The third preliminary barrier layer 225 may be oxidized to form a first barrier layer 230 including silicon oxide.

During the second deposition process, the halogen element included in the third precursor may be pyrolyzed to remove the functional group including nitrogen in the seed layer 210, and the first preliminary barrier layer 220 may be partially etched to reduce the thickness of a portion of the first preliminary barrier layer 220 at an upper portion of the trench hole 200. Accordingly, during the second deposition process, the first preliminary barrier layer 220 may not be thick at the entrance of the channel hole 200, and may be formed at a lower portion of the channel hole 200. Further, a portion of the first preliminary barrier layer 220 at a lower portion of the channel hole 200 may have a thickness greater than that of a portion of the first preliminary barrier layer 220 at an upper portion of the channel hole 200.

The third deposition process may be further performed using only the second precursor including the MS, and thus a portion of the second preliminary barrier layer on the first preliminary barrier layer 220 located at an upper portion of the channel hole 200 may be relatively thick, and the third preliminary barrier layer 225 including the first preliminary barrier layer 220 and the second preliminary barrier layer may have a substantially uniform thickness along the sidewall of the channel hole 200. In particular, the plurality of channel holes 200 may be arranged in the second and third directions, and the third preliminary blocking layers 225 in the channel holes 200 may have uniform thicknesses, respectively.

During the second deposition process for forming the first preliminary barrier layer 220, nitrogen contained in the seed layer 210 may be removed by a halogen element contained in the third precursor, and thus the third preliminary barrier layer 225 may have polysilicon substantially free of nitrogen, and an oxidation process may be performed on the third preliminary barrier layer 225 to form the first barrier layer 230. The third preliminary barrier layer 225 may include polysilicon instead of nitride, and thus, even if a radical oxidation process is performed instead of a thermal oxidation process, a portion of each fourth sacrificial layer 180 adjacent to the channel hole 200 may not be oxidized.

Accordingly, the thicknesses of the portions of the first barrier patterns 235 included in the charge storage structure 265 (which may be adjacent to the insulating layer 170 and the fourth sacrificial layer 180, respectively) in the horizontal direction substantially parallel to the upper surface of the substrate 100 may be substantially equal to each other. For example, the thickness of the first barrier patterns 235 in the horizontal direction may be substantially uniform in the first direction, and the surface of the first barrier patterns 235 may be flat (e.g., planar). Accordingly, the first barrier patterns 235 may have desired characteristics.

When the second deposition process is performed on the seed layer 210 having the nitrogen-containing functional group under the hydrogen atmosphere, the halogen element contained in the third precursor may be pyrolyzed even at a low temperature to have an etching effect, and thus the processes for forming the first preliminary barrier layer 220 and the first barrier layer 230 may be performed at a low temperature, so that degradation of adjacent structures caused by a high-temperature process may be prevented.

Fig. 14 is a graph illustrating the concentration of chlorine remaining in the first barrier patterns 235 according to the distance from the sidewalls of the trench hole 200 when the second deposition process for forming the first preliminary barrier layer 220 is performed using DCS as a third precursor.

Referring to fig. 13 and 14, the chlorine concentration in the first barrier pattern 235 decreases from the outer sidewall of the first barrier pattern 235 facing the gate electrode 380 or the second barrier pattern 370 toward the inner sidewall of the first barrier pattern 235 facing the charge storage pattern 245. This is because when the first preliminary barrier layer 220 is deposited from the sidewalls of the channel hole 200 during the second deposition process, chlorine contained in the third precursor may be pyrolyzed to be removed together with the nitrogen-containing functional groups of the seed layer 210. Therefore, even if the third precursor includes other halogen elements such as fluorine, bromine, iodine, and the like, the concentrations of the other halogen elements may be similar.

In an exemplary embodiment of the present disclosure, the chlorine concentration at the inner sidewalls of the first barrier patterns 235 may be less than or equal to about 1/5 (e.g., 1/10) of the chlorine concentration at the outer sidewalls of the first barrier patterns 235. In an exemplary embodiment of the present disclosure, the chlorine concentration in the first barrier pattern 235 may gradually decrease from the outer sidewall toward the inner sidewall up to a central portion in a horizontal direction, and may be substantially uniform from the central portion to the inner sidewall.

The vertical memory device manufactured by the above process may have the following structural features.

The vertical memory device may include a channel 275 extending in a first direction on the substrate 100. The channel connection pattern 340 contacts the channel 275 on the substrate 100. The charge storage structure 265 is disposed on an outer sidewall of each channel 275, and includes a tunnel insulation pattern 255, a charge storage pattern 245, and a first blocking pattern 235 sequentially stacked in a horizontal direction. The gate electrodes 380 are spaced apart from each other in the first direction on the channel connection pattern 340 and surround the charge storage structure 265. The division pattern 390 is disposed on the substrate 100, passes through the gate electrode 380, and extends in the second direction to separate the gate electrode 380 in the third direction. The bit lines 420 are spaced apart from each other in the second direction, extend in the third direction, and are electrically connected to the channels 275.

In an exemplary embodiment of the present disclosure, the first barrier pattern 235 may include silicon oxide containing a halogen element (e.g., fluorine, chlorine, bromine, iodine, etc.), and the concentration of the halogen element in the first barrier pattern 235 may decrease from an outer sidewall facing the gate electrode 380 toward an inner sidewall facing the charge storage pattern 245.

In an exemplary embodiment of the present disclosure, the concentration of the halogen element in the first barrier patterns 235 at the inner sidewall may be less than or equal to about 1/5 of the concentration of the halogen element in the first barrier patterns 235 at the outer sidewall.

In an exemplary embodiment of the present disclosure, the concentration of the halogen element in the first barrier patterns 235 may gradually decrease from the outer sidewall toward the inner sidewall up to a central portion in a horizontal direction, and may be substantially uniform from the central portion to the inner sidewall.

In an exemplary embodiment of the present disclosure, the first barrier pattern 235 may be substantially free of nitrogen.

In an exemplary embodiment of the present disclosure, the thickness of the first barrier patterns 235 in the horizontal direction may be substantially uniform in the vertical direction, and thus the inner and outer sidewalls of the first barrier patterns 235 may be substantially flat (e.g., planar).

In an exemplary embodiment of the present disclosure, the second blocking pattern 370 may cover a lower surface and an upper surface of each gate electrode 380 and a sidewall facing the charge storage structure 265, and may include a metal oxide.

Although exemplary embodiments of the present disclosure have been particularly shown and described, it will be understood by those of ordinary skill in the art that changes in form and details may be made therein without departing from the spirit and scope of the following claims.

This application claims priority from korean patent application No. 10-2020-0069614 filed in Korean Intellectual Property Office (KIPO) on 9/6/2020, which is hereby incorporated by reference in its entirety.