阅读说明：本技术 一种含多协议通讯接口外设的微控制器芯片及其运行方法 (Microcontroller chip containing multi-protocol communication interface peripheral and operation method thereof ) 是由 王春华 于 2021-11-12 设计创作，主要内容包括：本发明公开了一种含多协议通讯接口外设的微控制器芯片及其运行方法,包括多协议通讯接口外设,所述多协议通讯接口外设连接到系统总线上,所述多协议通讯接口外设与I/O端口连接,所述多协议通讯接口外设包括专用RISC指令集微内核、代码存储器及存储在代码存储器上并可被RISC指令集微内核执行的代码程序,所述代码程序至少包括置1和清0两种位操作指令,所述指令为单周期指令,当RISC指令集微内核执行该代码程序时可实现I/O端口输出1或0。本发明使微控制器芯片的接口外设更加灵活,提高了微控制器芯片的通用性,其通讯协议可改版或升级,减少了部分冗余或备用通讯接口,节约了成本。(The invention discloses a micro-controller chip containing multi-protocol communication interface peripheral equipment and an operation method thereof, wherein the micro-controller chip comprises the multi-protocol communication interface peripheral equipment, the multi-protocol communication interface peripheral equipment is connected to a system bus, the multi-protocol communication interface peripheral equipment is connected with an I/O port, the multi-protocol communication interface peripheral equipment comprises a special RISC instruction set micro-kernel, a code memory and a code program which is stored on the code memory and can be executed by the RISC instruction set micro-kernel, the code program at least comprises two bit operation instructions of setting 1 and clearing 0, the instruction is a single-cycle instruction, and when the RISC instruction set micro-kernel executes the code program, the I/O port can output 1 or 0. The invention makes the interface of the microcontroller chip be more flexible, improves the universality of the microcontroller chip, can modify or upgrade the communication protocol, reduces partial redundancy or spare communication interfaces and saves the cost.)

1. A microcontroller chip containing multi-protocol communication interface peripheral equipment is characterized by comprising a main processor core, a system bus, a plurality of peripheral equipment and an I/O port, wherein the peripheral equipment also comprises the multi-protocol communication interface peripheral equipment, the multi-protocol communication interface peripheral equipment is connected to the system bus, the multi-protocol communication interface peripheral equipment is connected with the I/O port, the multi-protocol communication interface peripheral equipment comprises an RISC instruction set micro-core, a code memory and a code program which is stored on the code memory and can be executed by the RISC instruction set micro-core, the code program at least comprises two bit operation instructions of setting 1 and clearing 0, the instruction is a single-cycle instruction, and when the RISC instruction set micro-core executes the code program, the I/O port can output 1 or 0.

2. The microcontroller chip with multi-protocol communication interface peripheral of claim 1 wherein the data bit width of the main processor core is 32 bits or 64 bits and the data bit width of the RISC instruction set microcore is 4 bits or 8 bits.

3. The microcontroller chip with the multi-protocol communication interface peripheral of claim 1 further comprising a selector, wherein the multi-protocol communication interface peripheral and the main processor core are connected to the I/O port through the selector.

4. The microcontroller chip with multi-protocol communication interface peripheral device according to claim 1 wherein the code memory is SRAM and is connected to the system bus, the code memory further operable for data storage by the main processor core.

5. The microcontroller chip having the multi-protocol communication interface peripheral device according to claim 1, wherein the code memory is a one-time programmable memory OTP, and a code program in the code memory is preset by a microcontroller chip manufacturer before shipment.

6. The microcontroller chip with multi-protocol communication interface peripheral of any one of claims 1 through 5 wherein the host processor core includes a plurality of peripheral data exchange registers, the peripheral data exchange registers being disposed at a side of the multi-protocol communication interface peripheral, the peripheral data exchange registers corresponding to data registers of data bit widths of the N RISC instruction set microcores, N being a value of a data bit width of the host processor core divided by a data bit width of the RISC instruction set microcore.

7. The microcontroller chip with the multi-protocol communication interface peripheral of any one of claims 1 through 5 wherein the main processor core further comprises an interrupt controller, the multi-protocol communication interface peripheral being connected to the interrupt controller via an interrupt request signal line.

8. The microcontroller chip according to one of claims 1 through 5 further comprising at least one of a DMA controller and an arbiter, wherein the multi-protocol communication interface peripheral is connected to at least one of the DMA controller and the arbiter via a plurality of signal lines.

9. The microcontroller chip having a multi-protocol communication interface peripheral device according to any one of claims 1-5, wherein the number of I/O ports connected to the multi-protocol communication interface peripheral device is not more than 4.

10. A method of operating a microcontroller chip having a multi-protocol communication interface peripheral device according to any one of claims 1 to 9, comprising the steps of:

burning a main program target code into a Flash memory of a microcontroller chip, wherein the main program target code comprises a target code of an I/O port control program, and the target code of the I/O port control program is developed based on a RISC instruction set microkernel;

the chip is powered on or reset, the RISC instruction set micro-kernel is in a forbidden state by default, and the main processor kernel loads the target code of the I/O port control program from the Flash memory of the chip to the code memory in the multi-protocol communication interface peripheral equipment;

RISC instruction set microkernel execution is enabled.

Technical Field

The invention belongs to the field of microcontroller chip design, and particularly relates to a microcontroller chip containing a flexible multi-protocol communication interface peripheral and an operation method thereof.

Background

As shown in fig. 1, a general microcontroller chip may support a plurality of interfaces for external communication, including a serial port (UART), a 4-line SPI, a two-line I2C, a two-line USB, and the like, and some interfaces also need to provide a plurality of sets of redundancies for diversified applications, resulting in a plurality of MCU peripherals and redundancies. A 32-bit MCU such as CH32F103 provides 3 sets of serial ports, 2 sets of I2C, and 2 sets of SPIs, but in most practical applications, only some of the communication interfaces will be used.

Most communication interfaces are well known and definite in protocol in the industry, but some communication protocols are non-well known communication protocols customized by various manufacturers, for example, a 1-wire communication interface lacks sufficient industry knowledge, a plurality of chip manufacturers respectively customize a 1-wire communication protocol of their own, and in addition, a plurality of two-wire communication interfaces have the condition that the names are similar but the actual communication protocols are different.

As a general microcontroller chip manufacturer, if one core is considered to be general, controllers of the communication interfaces of the above-mentioned multiple protocols need to be mounted on a system bus, and the controllers are realized by pure hardware digital logic, support multiple flexible parameters, but for a non-consensus communication interface with an unclear protocol, the problem is not a parameter problem, but a problem of the same name but different protocols. Therefore, the microcontroller chip generally does not provide a communication interface of the non-consensus protocol, and is left to be implemented by a user by controlling the I/O simulation by software. However, the software implementation has disadvantages that such non-consensus communication protocols are generally low in speed, most of which are dozens to hundreds of kbits, a few microseconds to hundreds of microseconds may be needed for transmitting a few bytes of data, and the main processor core of the high-performance microcontroller chip runs at least dozens or hundreds of MHz, which occupies a CPU time for low-speed communication and wastes a large amount of power consumption, and the protocol interaction process is frequently interrupted by other system peripherals. If the interrupt mode is adopted, frequent interference of one interrupt every few microseconds is caused to the microcontroller chip, and the system efficiency is reduced.

Disclosure of Invention

The purpose of the invention is as follows: the invention provides a microcontroller chip containing a multi-protocol communication interface peripheral and an operation method thereof, aiming at solving the problems that the existing high-performance microcontroller is inconvenient to support a non-consensus communication protocol and the existing communication interface peripheral cannot support a flexible protocol and needs to provide a plurality of groups of redundant fixed protocol communication interfaces to cause waste.

The technical scheme is as follows: a microcontroller chip containing a multi-protocol communication interface peripheral comprises a main processor core, a system bus, a plurality of peripherals and an I/O port, wherein the peripherals comprise the multi-protocol communication interface peripheral, the multi-protocol communication interface peripheral is connected to the system bus and is connected with the I/O port, the multi-protocol communication interface peripheral comprises an RISC instruction set microcore, a code memory and a code program which is stored on the code memory and can be executed by the RISC instruction set microcore, the code program at least comprises two bit operation instructions of setting 1 and clearing 0, the instruction is a single-cycle instruction, and when the RISC instruction set microcore executes the code program, the I/O port can output 1 or 0.

Further, the data bit width of the main processor core is 32 bits or 64 bits, and the data bit width of the RISC instruction set microkernel is 4 bits or 8 bits.

The multi-protocol communication interface peripheral and the main processor core are connected with the I/O port through the selector.

Further, the code memory is an SRAM and is connected to the system bus, and the code memory can also be used for storing data of the main processor core. The SRAM facilitates dynamic loading of object code for I/O port control programs of different protocols. The SRAM can also be used as a data memory of a main processor when a multi-protocol communication interface peripheral is not needed.

Further, the code memory is a one-time programmable memory (OTP), and a code program in the code memory is preset by a microcontroller chip manufacturer before factory shipment.

Furthermore, the main processor core comprises a plurality of peripheral data exchange registers, the peripheral data exchange registers are arranged on one side of the multi-protocol communication interface peripheral, the peripheral data exchange registers correspond to data registers with data bit width of the N RISC instruction set microcores, and N is a value obtained by dividing the data bit width of the main processor core by the data bit width of the RISC instruction set microcore.

Furthermore, the main processor core also comprises an interrupt controller, and the multi-protocol communication interface peripheral is connected with the interrupt controller through an interrupt request signal line.

Furthermore, the multi-protocol communication interface peripheral equipment is connected with at least one of the DMA controller and the arbiter through a plurality of signal lines.

Furthermore, the number of the I/O ports connected with the multi-protocol communication interface peripheral is not more than 4.

An operation method of the microcontroller chip with the multi-protocol communication interface peripheral is characterized by comprising the following steps:

burning a main program target code into a Flash memory of a microcontroller chip, wherein the main program target code comprises a target code of an I/O port control program, and the target code of the I/O port control program is developed based on a RISC instruction set microkernel;

the chip is powered on or reset, the RISC instruction set micro-kernel is in a forbidden state by default, and the main processor kernel loads the target code of the I/O port control program from the Flash memory of the chip to the code memory in the multi-protocol communication interface peripheral equipment;

RISC instruction set microkernel execution is enabled.

Compared with the prior art, the invention provides a microcontroller chip containing a multi-protocol communication interface peripheral and an operation method thereof, and has the following beneficial effects:

(1) flexibility and versatility. The multi-protocol communication interface peripheral designed according to the invention can easily face diversified non-consensus communication protocols by loading target codes of I/O port control programs of different communication protocols, thereby further improving the universality of the microcontroller chip.

(2) Can be upgraded. When a common microcontroller chip is designed, a common communication interface controller is built in, and the common microcontroller chip cannot be newly added after being manufactured and cannot be suitable for large version changing and upgrading of a communication protocol. After the microcontroller chip designed according to the invention is manufactured, the I/O port control program of the communication protocol can still be updated to follow the version upgrade of the third-party communication protocol, so that the compatibility of the microcontroller chip is improved, and the capability of adapting to the technical and market changes is improved.

(3) The cost is low. The RISC instruction set microkernel in the multi-protocol communication interface peripheral is a special RISC instruction set microkernel which is specially used for processing I/O interface protocols, performance and cost optimization can be carried out on the kernel, bit width is reduced to reduce cost, bit operation instructions of a single cycle are increased or optimized to improve I/O operation efficiency, unnecessary address space and algorithm instructions are reduced to control the scale and the cost of the kernel, and the multi-protocol communication interface peripheral can be realized only by the scale of 2000 to 3500 gates. In contrast, the conventional I2C protocol two-wire interface dedicated peripheral controller also requires a size of 2000 gates; the basic 32-bit M3 core, which is the main processor core, is approximately 70000 gate in size, and 64-bit cores are multiplied. Therefore, the scale of the special RISC instruction set microkernel and the common external of the special protocol are set to be the same grade, which is far smaller than the scale of the main processor kernel, and the goal and the thought are completely different from the goal and the thought of adopting a dual-core or even multi-core microcontroller scheme for pursuing the operation performance. In addition, the universality enables the system scheme to reduce a part of redundant or standby communication interfaces, thereby further saving the cost.

The method can realize high flexibility at low cost, benefits from the pertinence of a scheme and the understanding of a microkernel design target, has small data volume and low speed for an I/O interface protocol, particularly a medium-low speed serial interface protocol below several MHz, is suitable for a special RISC instruction set microkernel to simulate an interface communication protocol by a plurality of instructions, and can replace more time for smaller hardware scale and higher flexibility. In contrast, a purely hardware digital logic dedicated controller is more suitable for protocol-specific high-speed interfaces.

Drawings

FIG. 1 is a prior art 32-bit high performance microcontroller architecture with peripheral redundancy, typically without a 1-wire interface;

FIG. 2 is a diagram illustrating an embodiment of a microcontroller architecture including a multi-protocol communication interface peripheral device;

FIG. 3 is a diagram illustrating a second embodiment of a microcontroller architecture including a multi-protocol communication interface peripheral device;

FIG. 4 is a diagram illustrating an exemplary architecture of a third embodiment of a micro-controller including a peripheral device with multiple protocol communication interfaces.

Detailed Description

The invention is further explained below with reference to the figures and the specific embodiments.

The first embodiment is as follows:

a microcontroller chip containing a multi-protocol communication interface peripheral comprises a main processor core, a system bus, a plurality of peripherals and an I/O port, wherein the peripherals comprise the multi-protocol communication interface peripheral, the multi-protocol communication interface peripheral is used as one of a plurality of peripheral modules, is hung on the system bus of the microcontroller chip and is connected through a clock signal line, a reset signal line, an address signal line and a data signal line, and the address signal line and the data signal line are contained in the system bus. The multi-protocol communication interface peripheral equipment is connected with an I/O port, the multi-protocol communication interface peripheral equipment comprises a RISC instruction set micro-kernel, a code memory and a code program which is stored on the code memory and can be executed by the RISC instruction set micro-kernel, the code program at least comprises a 1 setting bit operation instruction and a 0 clearing bit operation instruction, the instruction is a single-cycle instruction, and when the RISC instruction set micro-kernel executes the code program, the I/O port can be efficiently output with 1 or 0. Further, shift operation instructions such as shift left and shift right, bit copy, bit insert, bit test, loop, etc. may be included to more efficiently support I/O state read, output setup operations, and mimic interface protocols.

The data bit width of the main processor core in this embodiment is 32 bits, or may be more than 32 bits, such as 64 bits; the data bit width of the RISC instruction set microkernel is 8 bits, or may not exceed 8 bits, such as 4 bits.

The RISC instruction set microkernel is a special RISC instruction set microkernel, is specially used for controlling the output and the input of an I/O port, has small bit width and high speed after being optimized, improves the I/O operation efficiency by optimizing bit operation instructions, and reduces unnecessary larger address space and algorithm instructions to control the microkernel scale so as to save the cost. Different from the basic equal-time parallel dual-core design in the common dual-core CPU, the RISC instruction set micro-core is only used as a peripheral of a system bus, shows the similar characteristics and permission as a common hardware logic special controller, is specially used for processing an I/O interface protocol, and has the scale and the required resources far smaller than those of a main processor core.

The multi-protocol communication interface peripheral device of this embodiment includes 1-wire external connection, and is connected to one I/O port, and may also be connected to different numbers of I/O ports as required, and generally does not exceed four. The multi-protocol communication interface peripheral equipment can be directly connected with the I/O port, and can also be connected with the I/O port through the selector. Referring to fig. 2, the multi-protocol communication interface peripheral and the main processor core of the present embodiment are connected to the I/O port through a selector, and the selector is configured to select whether the multi-protocol communication interface peripheral is connected to the I/O or the main processor core is connected to the I/O. When the peripheral is not needed, the main processor core can be selected to be connected with the I/O, and the I/O is directly used as a common GPIO.

The code memory in the embodiment stores a plurality of instructions of the RISC instruction set microkernel, the code memory in the embodiment adopts the SRAM with a 512 × 32bit structure, and the data bit width is 32 bits, so that the code memory is conveniently and efficiently connected to the system bus. And when the code memory is used for providing instructions, 4 bits are discarded from every 32 bits, and the data interface which is combined into 1K 14 bits can be used for storing 1024 instructions with 14bit width. The SRAM allows a user to write a communication protocol program by himself to realize a user-defined communication interface, and when a multi-protocol communication interface peripheral is not used, the SRAM can also be used as a data storage of a main processor to store data, so that resources are not wasted. For a single-port SRAM, a system bus and an instruction channel of a RISC instruction set microkernel can be connected with the SRAM through a selector or an arbiter; for dual port SRAM, the system bus and the instruction channels of the RISC instruction set microkernel are each connected to one port of the SRAM.

The main processor core comprises a plurality of peripheral data exchange registers, including an input data register, an output data register, a control register, a state register and the like, the peripheral data exchange registers are arranged at one side of the multi-protocol communication interface peripheral, each peripheral data exchange register corresponds to a data register with a data bit width not exceeding 4 RISC instruction set microcores, and 4 is obtained by dividing the data bit width 32 of the main processor core by the data bit width 8 of the RISC instruction set microcore. 4 data with 8 bit width are merged and submitted to a system bus according to 32 bits, so that the main processor can conveniently access in a single cycle, and the CPU time of the kernel of the main processor can be saved.

The main processor core also comprises an interrupt controller, and the multi-protocol communication interface peripheral is connected with the interrupt controller through an interrupt request signal line.

An operation method of the microcontroller chip with the multi-protocol communication interface peripheral comprises the following steps:

burning a main program target code into a Flash memory of the microcontroller chip, wherein the main program target code comprises a target code of an I/O port control program. The target code of the I/O port control program is developed in advance based on the RISC instruction set microkernel, the I/O port control programs of a plurality of communication protocols can be developed in advance, the I/O port control program corresponding to the communication protocol is selected according to actual needs and integrated into the target code of the main program of the microcontroller chip;

the chip is powered on or reset, the RISC instruction set micro-kernel is in a forbidden state by default, the main processor kernel operates firstly, and the main processor kernel loads the target code of the I/O port control program from the Flash memory of the chip to the code memory in the multi-protocol communication interface peripheral equipment;

RISC instruction set microkernel execution is enabled.

The loading of the object code and the operation of the RISC instruction set microkernel can be executed only when needed.

In addition, after the chip is powered on or reset, the hardware can automatically load the target code of the I/O port control program from the Flash memory of the chip into the code memory in the peripheral equipment of the multi-protocol communication interface and enable the RISC instruction set microkernel to run.

In addition, according to the requirement, during the running period of the RISC instruction set microkernel, the target code of the I/O port control program can be changed at any time, the RISC instruction set microkernel is forbidden firstly, the main processor kernel loads the target code of the new I/O port control program into the code memory in the multi-protocol communication interface peripheral equipment from the Flash memory of the chip, and the communication protocol can be updated by running the RISC instruction set microkernel again.

Example two:

compared with the first embodiment, the difference is that the data bit width of the main processor core of the second embodiment is 32 bits, and the main frequency is 200 MHz; the data bit width of the RISC instruction set microkernel is 8 bits, and the dominant frequency is 200 MHz; the code memory adopts a dual-port SRAM with a 1K X32 bit structure, and when the code is provided, the lowest bit address signal selects the low 16 bits or 16 bits of 32bit data to output, so that a 4KB instruction storage space with 2K X16 bits is formed; the system comprises 2 external IO connections and mode control thereof, and can realize serial port, two-wire and one-wire protocol communication by connecting a plurality of control signal wires, mode signal wires and input/output signal wires with 2I/O ports.

The microcontroller chip also comprises a DMA controller and/or an arbiter, and the multi-protocol communication interface peripheral is connected with the DMA controller and/or the arbiter through a plurality of signal lines, so that data can be directly exchanged with a system main memory, and the occupation of CPU time of a main processor core is further reduced.

Example three:

compared with the first embodiment, the difference is that the main processor core of the third embodiment has a data width of 32 bits, and the main frequency is 100 MHz; the data bit width of the RISC instruction set microkernel is 4 bits, and the dominant frequency is 10 MHz. Every 8 data registers on the RISC microkernel side are combined into a 32-bit register which can be efficiently accessed by a main processor, and a plurality of 32-bit registers are included for exchanging data, control bits and states; the external IO connection with 1 line and its mode control are connected with 1I/O port through multiple signals. The code memory adopts a one-time programmable memory OTP with lower cost than Flash and has 1K multiplied by 10bit instruction storage space; the codes in the OTP can be preset by a microcontroller chip manufacturer before leaving factory, and are completely independent of the main program of the microcontroller, thereby being convenient for keeping the user secret and improving the safety. Compared with a pure hardware controller redesigned by a target program of a preset interface protocol before the chip leaves a factory, the time of multiple links of chip rear-end wiring, data processing, board making, chip flowing, packaging and the like is saved, and the method is favorable for rapidly upgrading the protocol and timely responding to market demands.