阅读说明：本技术 一种交换机及数据访问方法 (Switch and data access method ) 是由 商轲 雷雄 孙东 卢杰 薛建军 于 2021-06-30 设计创作，主要内容包括：本发明实施例提供了一种交换机及数据访问方法,涉及通信技术领域,可以提高CPU访问I2C器件的效率,减少访问I2C器件对CPU的占用。本发明实施例的交换机包括：中央处理器CPU、复杂可编程逻辑器件CPLD芯片和多个集成电路总线I2C器件。CPU通过串行外设接口SPI与CPLD芯片连接；CPLD芯片包括多个I2C模拟接口,每个I2C模拟接口通过两个I/O管脚模拟实现；CPLD芯片包括的每个I2C模拟接口与不同的I2C器件连接。CPU用于通过SPI向CPLD芯片发送访问指令；CPLD芯片用于基于访问指令通过I2C模拟接口对I2C器件进行读写操作。(The embodiment of the invention provides a switch and a data access method, relates to the technical field of communication, and can improve the efficiency of a CPU (Central processing Unit) accessing an I2C device and reduce the occupation of the access I2C device on the CPU. The switch of the embodiment of the invention comprises: the device comprises a Central Processing Unit (CPU), a Complex Programmable Logic Device (CPLD) chip and a plurality of integrated circuit bus I2C devices. The CPU is connected with the CPLD chip through a Serial Peripheral Interface (SPI); the CPLD chip comprises a plurality of I2C analog interfaces, and each I2C analog interface is realized by simulating two I/O pins; each I2C analog interface included in the CPLD chip is connected to a different I2C device. The CPU is used for sending an access instruction to the CPLD chip through the SPI; the CPLD chip is used for reading and writing the I2C device through the I2C analog interface based on the access instruction.)

1. A switch, comprising: the device comprises a Central Processing Unit (CPU), a Complex Programmable Logic Device (CPLD) chip and a plurality of integrated circuit bus I2C devices;

the CPU is connected with the CPLD chip through a Serial Peripheral Interface (SPI); the CPLD chip comprises a plurality of I2C analog interfaces, and each I2C analog interface is realized by two I/O pin simulation; each I2C analog interface included in the CPLD chip is connected with different I2C devices;

the CPU is used for sending an access instruction to the CPLD chip through the SPI;

the CPLD chip is used for performing read-write operation on the I2C device through an I2C analog interface based on the access instruction.

2. The switch according to claim 1,

the first I2C analog interface of the CPLD chip is connected with a plurality of I2C devices with different physical addresses; and/or the presence of a gas in the gas,

the second I2C analog interface of the CPLD chip is connected to an analog switch, the analog switch is connected to a plurality of I2C devices with the same physical address, and the analog switch is used for selectively switching on or off the access channel of each I2C device connected with the analog switch.

3. The switch according to claim 1,

the CPU comprises an I2C interface, and is connected with a specified I2C device through an I2C interface; alternatively, the first and second electrodes may be,

one I2C analog interface of the CPLD chip is connected with the specified I2C device.

4. The switch of claim 3, wherein the designated I2C devices include power supplies and fans.

5. A data access method applied to a CPU, the CPU being located in the switch of any one of claims 1-4, the method comprising:

the CPU sends an access instruction to the CPLD chip through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through an I2C simulation interface based on the access instruction to obtain a read-write result;

and the CPU acquires the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.

6. The method according to claim 5, wherein the access instruction is a write instruction, the write instruction carrying data to be written;

the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI, and the read-write result comprises the following steps:

and the CPU acquires a writing result of the data to be written from the CPLD chip through the SPI, and the writing result is used for indicating writing success or writing failure.

7. The method of claim 5, wherein the access instruction is a read instruction; the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI, and the read-write result comprises the following steps:

the CPU obtains data to be read from the CPLD chip through the SPI, and the data to be read is data read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface by the CPLD chip.

8. A data access method, applied to a CPLD chip, located in the switch of any one of claims 1-4, the method comprising:

receiving an access instruction sent by a CPU through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed;

and performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access command, and storing a read-write result, so that the CPU can obtain the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.

9. The method according to claim 8, wherein the access instruction is a write instruction, and the write instruction carries data to be written;

the performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction and storing a read-write result comprises:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed;

receiving a write response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and storing a write result of the data to be written based on the write response, wherein the write result is used for indicating write success or write failure.

10. The method of claim 8, wherein the access instruction is a read instruction; the performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction and storing a read-write result comprises:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

reading data to be read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the device to be accessed;

and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a switch and a data access method.

Background

A Central Processing Unit (CPU) on a board of the switch may access an I2C device, such as an Electrically Erasable Programmable Read Only Memory (EEPROM), a temperature sensor, a Real Time Clock (RTC), and an optical module, included in the board through an Inter-Integrated Circuit (I2C) bus. I2C is a low speed Serial bus consisting of two lines, a Serial Clock Line (SCL) and a Serial Data line (SDA).

As shown in fig. 1, different types of I2C devices on the single board of the switch can be connected to different I2C interfaces of the CPU, such as the temperature sensing chip, the RTC chip and the EEPROM in fig. 1 are connected to the I2C1 interface of the CPU; the power supply and the fan are connected to an I2C2 interface of the CPU; one end of the analog switch is connected with the service interface modules 0-N, the other end is connected with the I2C3 interface of the CPU, and the rest I2C devices are connected with the I2C4 interface of the CPU.

The number of I2C devices on the single board of the switch is large, the CPU needs to perform one round of access to the I2C devices through the I2C bus at intervals, because the rate of the I2C bus is low, the CPU accessing a large number of I2C devices will occupy a large amount of time of the CPU, the access efficiency is low, and the CPU cannot perform other services when accessing the I2C device.

Disclosure of Invention

The embodiment of the invention aims to provide a switch and a data access method, so as to improve the efficiency of accessing an I2C device by a CPU and reduce the occupation of the I2C device on the CPU. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present invention provides a switch, including: the device comprises a Central Processing Unit (CPU), a Complex Programmable Logic Device (CPLD) chip and a plurality of integrated circuit bus I2C devices;

the CPU is connected with the CPLD chip through a Serial Peripheral Interface (SPI); the CPLD chip comprises a plurality of I2C analog interfaces, and each I2C analog interface is realized by two I/O pin simulation; each I2C analog interface included in the CPLD chip is connected with different I2C devices;

the CPU is used for sending an access instruction to the CPLD chip through the SPI;

the CPLD chip is used for performing read-write operation on the I2C device through an I2C analog interface based on the access instruction.

Optionally, the first I2C analog interface of the CPLD chip is connected to a plurality of I2C devices with different physical addresses; and/or the presence of a gas in the gas,

the second I2C analog interface of the CPLD chip is connected to an analog switch, the analog switch is connected to a plurality of I2C devices with the same physical address, and the analog switch is used for selectively switching on or off the access channel of each I2C device connected with the analog switch.

Optionally, the CPU includes an I2C interface, and the CPU is connected with a specified I2C device through an I2C interface; alternatively, the first and second electrodes may be,

one I2C analog interface of the CPLD chip is connected with the specified I2C device.

Optionally, the designated I2C device includes a power supply and a fan.

In a second aspect, an embodiment of the present invention provides a data access method, which is applied to a CPU, where the CPU is located in a switch according to any one of the first aspect, and the method includes:

the CPU sends an access instruction to the CPLD chip through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through an I2C simulation interface based on the access instruction to obtain a read-write result;

and the CPU acquires the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.

Optionally, the access instruction is a write instruction, and the write instruction carries data to be written;

the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI, and the read-write result comprises the following steps:

and the CPU acquires a writing result of the data to be written from the CPLD chip through the SPI, and the writing result is used for indicating writing success or writing failure.

Optionally, the access instruction is a read instruction; the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI, and the read-write result comprises the following steps:

the CPU obtains data to be read from the CPLD chip through the SPI, and the data to be read is data read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface by the CPLD chip.

In a third aspect, an embodiment of the present invention provides a data access method, which is applied to a CPLD chip, where the CPLD chip is located in the switch in any one of the first aspect, and the method includes:

receiving an access instruction sent by a CPU through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed;

and performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access command, and storing a read-write result, so that the CPU can obtain the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.

Optionally, the access instruction is a write instruction, and the write instruction carries data to be written;

the performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction and storing a read-write result comprises:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed;

receiving a write response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and storing a write result of the data to be written based on the write response, wherein the write result is used for indicating write success or write failure.

Optionally, the access instruction is a read instruction; the performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction and storing a read-write result comprises:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

reading data to be read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the device to be accessed;

and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.

Optionally, the method further includes:

if a recovery command of the CPU to the specified I2C analog interface is received through the SPI bus, an SCL clock signal of the specified I2C analog interface is pulled down for 9 times continuously.

In a fourth aspect, an embodiment of the present invention provides a data access apparatus, which is applied to a CPU, where the CPU is located in the switch in the first aspect, and the apparatus includes:

the write-in module is used for sending an access instruction to the CPLD chip through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction to obtain a read-write result;

and the acquisition module is used for acquiring the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.

Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the acquisition module is specifically configured to:

and acquiring a writing result of the data to be written from the CPLD chip through the SPI, wherein the writing result is used for indicating writing success or writing failure.

Optionally, the access instruction is a read instruction; the acquisition module is specifically configured to:

and acquiring data to be read from the CPLD chip through the SPI, wherein the data to be read is data read from a register corresponding to the register address in the I2C device to be accessed by the CPLD chip through an I2C analog interface.

In a fifth aspect, an embodiment of the present invention provides a data access device, which is applied to a CPLD chip, where the CPLD chip is located in the switch in the first aspect, and the device includes:

the receiving module is used for receiving an access instruction sent by the CPU through the SPI, and the access instruction comprises a physical address and a register address of an I2C device to be accessed;

and the access module is used for performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction, and storing a read-write result, so that the CPU can obtain the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.

Optionally, the access instruction is a write instruction, and the write instruction carries data to be written;

the access module is specifically configured to:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed;

receiving a write response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and storing a write result of the data to be written based on the write response, wherein the write result is used for indicating write success or write failure.

Optionally, the access instruction is a read instruction;

the access module is specifically configured to:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

reading data to be read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the device to be accessed;

and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.

Optionally, the apparatus further comprises: a pull-down module;

the pull-down module is configured to pull down an SCL clock signal of the designated I2C analog interface 9 times continuously if a recovery command of the CPU for the designated I2C analog interface is received through an SPI bus.

According to the switch and the data access method provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip can be connected with an I2C device through an I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip carries out read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD, the CPU only needs to send an access instruction to the CPLD chip through the SPI, and meanwhile, the SPI rate is higher than the I2C bus rate, so that the occupation of the CPU by accessing the I2C device is reduced, and the access efficiency is improved.

Of course, not all of the advantages described above need to be achieved at the same time in the practice of any one product or method of the invention.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by referring to these drawings.

Fig. 1 is a schematic configuration diagram of a switch in the related art;

fig. 2 is a schematic structural diagram of a switch according to an embodiment of the present invention;

FIG. 3 is a flow chart of a data access method according to an embodiment of the present invention;

FIG. 4 is a flow chart of another data access method provided by the embodiments of the present invention;

FIG. 5 is a flowchart of a data writing method according to an embodiment of the present invention;

FIG. 6 is a flowchart of a data reading method according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a data access device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of another data access device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived from the embodiments given herein by one of ordinary skill in the art, are within the scope of the invention.

In order to improve efficiency of a Central Processing Unit (CPU) accessing an Integrated Circuit bus (I2C) device and reduce occupation of the CPU accessing the I2C device, an embodiment of the present invention provides a switch, where the switch may be a box switch or a frame switch, and the present invention is not limited in this respect.

As shown in fig. 2, the switch provided in the embodiment of the present invention includes: a CPU201, a CPLD (Complex Programmable logic device) chip 202, and a plurality of I2C devices.

The CPU201 is connected to the CPLD chip 202 through a Serial Peripheral Interface (SPI); the CPLD chip 202 includes a plurality of I2C analog interfaces, each I2C analog interface is implemented by two Input/Output (I/O) pin emulation; each I2C analog interface included in CPLD chip 202 connects to a different I2C device. The CPLD chip 202 includes a certain storage space, and a part of the storage space of the CPLD chip 202 can be used as a logic register of the CPLD chip 202, where the logic register can store an access instruction sent by the CPU201, and can also store a read-write result of the I2C device to be accessed.

The CPU201 is configured to send an access instruction to the CPLD chip 202 through the SPI; the CPLD chip 202 is used for reading and writing the I2C device through an I2C analog interface based on an access instruction.

In the embodiment of the present invention, the connection relationship between the I2C analog interface of the CPLD chip 202 and the I2C device can be set according to actual requirements.

For example, with fewer I2C devices, each I2C analog interface of CPLD chip 202 may be connected to one I2C device.

In the case of many I2C devices, each I2C analog interface of CPLD chip 202 may connect multiple I2C devices. In one embodiment, the I2C devices may be classified according to the importance of the I2C device, for example, the I2C devices inside the switch may be classified into two types, one type is an important I2C device, and the other type is a non-important I2C device, and then the I2C devices (such as the service optical modules) externally connected to the switch are used as one type. Correspondingly, one I2C analog interface of the CPLD chip 202 is connected to a critical I2C device, another I2C analog interface is connected to a non-critical I2C device, and another I2C analog interface is connected to a plurality of service port optical modules through analog switches. Alternatively, an I2C device inside the switch is taken as a class I2C device, and an I2C device outside the switch is taken as a class I2C device. Accordingly, one I2C analog interface of the CPLD chip 202 is connected to an I2C device inside the switch, and the other I2C analog interface is connected to an I2C device outside the switch through an analog switch. The classification mode of the I2C device is not limited in the embodiment of the present application, and an I2C device connected to each I2C analog interface may be set according to actual requirements.

For example, the temperature sensing chip, the RTC chip and the EEPROM in fig. 2 are a type of I2C devices, and are commonly connected to the I2C2 analog interface of the CPLD chip 202. The service port optical modules 0 to N in fig. 2 are external modules, and the service port optical modules 0 to N are I2C devices of the same type, and are connected to the I2C3 analog interface of the CPLD chip 202 through an analog switch.

The CPLD chip 202 includes a plurality of I/O pins, and for some of the I/O pins of the CPLD chip 202, SCL signals and SDA signals transmitted by the I2C interface can be respectively simulated at two I/O pins of the CPLD chip 202 by logic codes, so that the two I/O pins are simulated as one I2C interface. The embodiment of the invention realizes the function of simulating the I2C interface through partial I/O pins of the CPLD chip, and because the CPLD chip is provided with a plurality of I/O pins, the embodiment of the invention does not increase the hardware cost of the CPLD chip.

In the switch provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip can be connected with an I2C device through an I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip carries out read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD, the CPU only needs to send an access instruction to the CPLD chip through the SPI, and meanwhile, the SPI rate is higher than the I2C bus rate, so that the occupation of the CPU by accessing the I2C device is reduced, and the access efficiency is improved.

Illustratively, the rate of an I2C bus that transfers data between I2C interfaces is typically below 100 kilohertz (kHz), while the rate of an SPI bus that transfers data between SPI interfaces is typically above 2 MegaHertz (MHz), and thus the rate of SPI is much higher than the rate of an I2C bus.

In the embodiment of the invention, the first I2C analog interface of the CPLD chip 202 is connected to a plurality of I2C devices with different physical addresses; and/or the second I2C analog interface of the CPLD chip 202 is connected to an analog switch, and the analog switch is connected to a plurality of I2C devices with the same physical address. The analog switch is used for selectively opening or closing the access channel of each I2C device connected with the analog switch.

Optionally, the first I2C analog interface of the CPLD chip 202 may be connected to an I2C device.

The first I2C analog interface and the second I2C analog interface are used for distinguishing I2C analog interfaces connected with different devices and are not used for limiting the properties of the I2C analog interfaces.

For example, as shown in fig. 2, the I2C2 analog interface of the CPLD chip 202 is connected to a temperature sensing chip, an EEPROM, and an RTC chip. The temperature sensing chip, the EEPROM and the RTC chip are I2C devices of different types and have different physical addresses.

Optionally, since the physical addresses of the service port optical modules are generally the same, each service port optical module may be connected to an I2C analog interface of the CPLD chip 202. Alternatively, as shown in fig. 2, the service port optical modules 0 to N may be connected to the I2C3 analog interface of the CPLD chip 202 through analog switches. Different access channels are selected through the analog switch, so that the CPLD chip 202 can access different service port optical modules. Wherein, the analog switch selects different access channels based on the control signal of the CPLD chip 202.

In the embodiment of the invention, the CPU201 includes an I2C interface, and the CPU201 is connected with a specified I2C device through an I2C interface; alternatively, one of the I2C analog interfaces of CPLD chip 202 is connected to a designated I2C device.

Alternatively, the designated I2C device includes a power supply and a fan.

For example, as shown in fig. 2, the power supply and the fan are connected to an I2C1 interface of the CPU 201.

Since the CPU is generally provided with an I2C interface, the more important I2C devices are directly connected to the I2C interface of the CPU, which can improve the reliability of the CPU accessing these more important I2C devices.

Optionally, in addition to the power supply, the fan, the temperature sensing chip, the EEPROM, the RTC chip, and the service port optical module, there may be other I2C devices, such as a power supply monitoring module, a clock phase-locked loop, and the like.

For example, as shown in fig. 2, other I2C devices may be connected to the I2C4 analog interface of the CPLD chip 202.

According to the embodiment of the invention, all the I2C devices in the switch can be connected to the CPLD chip, so that the occupation of the access I2C device on CPU resources is reduced as much as possible, and the CPU is prevented from being occupied by the I2C interface and being incapable of performing other operations.

Meanwhile, in the related art, all I2C devices are directly connected to the I2C interface of the CPU, and in order to perform classification management on the I2C devices, each type of I2C device is connected to one I2C interface, so that the CPU needs to have a large number of I2C interfaces, which has certain limitation on the type selection of the CPU in the switch and increases the cost of the CPU.

In the embodiment of the invention, part of the I2C devices can be selected to be directly connected with the I2C interface of the CPU, or all the I2C devices in the switch are connected with the CPLD chip without being connected with the CPU, so that the CPU with fewer I2C interfaces can be selected, the limitation on the type selection of the CPU in the switch is reduced, and the cost of the CPU is reduced.

In addition, in the related art, the I2C interface is simulated through a Peripheral Component Interconnect Express (PCIE) interface or a Universal Serial Bus (USB) interface, which both require an additional chip to be added to the switch board where the CPU and the I2C device are located, thereby increasing the hardware cost of the switch.

The switch single board where the CPU and the I2C device are located generally includes a CPLD chip, and the embodiment of the present invention utilizes the CPLD chip of the switch single board to implement the function of converting the SPI protocol to the I2C protocol, and at the same time, the CPLD chip of the switch single board generally can implement the function, so that the embodiment of the present invention has no additional limitation on the type selection of the CPLD chip on the switch single board, and does not increase additional hardware cost.

The conventional switch structure is shown in fig. 1, wherein a temperature sensing chip, an RTC chip and an EEPROM are connected to an I2C1 interface of a CPU; the power supply and the fan are connected to an I2C2 interface of the CPU; one end of the analog switch is connected with the service interface modules 0-N, the other end of the analog switch is connected with the I2C3 interface of the CPU, and other I2C devices are connected with the I2C4 interface of the CPU. The I2C devices connected with the same I2C interface are distinguished through different physical addresses, and if the physical addresses of the I2C devices connected with the same I2C interface are the same, different channels are gated by the analog switch for distinguishing.

When the CPU needs to access one I2C device, the CPU sends address signals to all I2C devices connected with the CPU through each I2C interface, wherein the address signals comprise the physical address of the I2C device needing to be accessed. After each I2C device receives the address signal, if the address signal includes the same physical address as its own physical address, an Acknowledge Character (ACK) signal is fed back to the CPU to inform the CPU that further operation is possible. After receiving the ACK signal, the CPU reads data from the I2C device that sent the ACK signal or writes data to the I2C device that sent the ACK signal.

If a plurality of I2C devices with the same physical address are connected to an I2C interface of the CPU, or the load capacitance of an I2C device connected to an I2C interface of the CPU exceeds the highest capacitance (400pF, wherein pF represents the picofarad) supported by the I2C protocol, the analog switch is controlled by the CPLD chip to open the corresponding channel, so that the CPU accesses the corresponding I2C device.

In addition to regular access to I2C devices, the CPU needs to perform read and write operations on some I2C devices at intervals, i.e., poll some I2C devices. Since the CPU accesses the I2C device through the I2C interface, and the rate of the I2C interface is low, i.e., the speed of the CPU sending address signals, receiving ACK messages, and reading or writing data to the I2C device is slow, the CPU's time and resources are heavily occupied, making it difficult for the CPU to process other traffic.

In order to improve the access efficiency of the CPU, the occupation of CPU resources by the access I2C device is reduced. An embodiment of the present invention provides a data access method, which is applied to a CPU, where the CPU is located in the switch shown in fig. 2, and as shown in fig. 3, the method includes the following steps:

s301, the CPU sends an access instruction to the CPLD chip through the SPI.

The access instruction comprises a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain a read-write result.

In the embodiment of the invention, the CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as a logic register of the CPLD chip. The CPU can access the logic register of the CPLD chip through the state machine of the internal logic code of the CPLD chip so as to send an access instruction to the CPLD chip.

And S302, the CPU obtains the read-write result of the I2C device to be accessed by the CPLD chip through the SPI.

According to the data access method provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip is connected with the I2C device through an I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip carries out read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD chip, the CPU only needs to send an access instruction to the CPLD chip, and can process other services when the CPLD chip performs read-write operation on the I2C device. And because the rate of the SPI is higher than the rate of the I2C bus, the CPU obtains the read-write result of the I2C device to be accessed from the CPLD chip through the SPI, and compared with the prior art that the CPU accesses the I2C device through an I2C interface, the CPU time occupation for accessing the I2C device can be reduced, the data access efficiency is improved, and the time for processing other services by the CPU is increased.

In the embodiment of the invention, the CPU can write data into the I2C device through the CPLD chip, where the access instruction is a write instruction, and the write instruction carries data to be written.

Based on this, the above-mentioned manner in which the CPU obtains the read-write result of the to-be-accessed I2C device by the CPLD chip through the SPI in S302 may be implemented as follows: and the CPU acquires a writing result of the data to be written from the CPLD chip through the SPI. Wherein the writing result is used to indicate a write success or a write failure. Optionally, when the writing result is a writing failure, the writing result may further include a reason of the writing failure.

In the embodiment of the invention, after the CPLD chip writes data to be written into the I2C device, if an ACK message fed back by the I2C device is received within a specified time, the writing is determined to be successful; or, if the CPLD chip does not receive the ACK message fed back by the I2C device within the specified time length after the data to be written is written into the I2C device, determining that the writing fails.

And after receiving the ACK message for indicating the successful writing, the CPLD chip stores a writing result for indicating the successful writing. And if the CPLD chip does not receive the ACK message for indicating successful writing within the specified time length after the data to be written is written into the I2C device, storing a writing result for indicating failed writing. Therefore, the CPU can obtain the writing result from the CPLD chip, and the reliability of data writing is improved.

When the CPU in the embodiment of the invention needs to write data into the register of the I2C device, a write-in instruction can be sent to the CPLD chip, the CPLD chip finishes data write-in work, and the CPU can process other services in the data write-in process of the CPLD. Because the CPU and the CPLD chip are communicated through the SPI, the data transmission speed of the SPI is far higher than that of the I2C, and compared with the situation that the CPU directly writes data into an I2C device through an I2C interface, the data writing speed of the CPU can be improved, and the situation that the CPU cannot process other services because the CPU writes data into the I2C device is avoided.

In the embodiment of the present invention, the CPU may read data from the I2C device through the CPLD chip, where the access instruction is a read instruction, and the manner in which the CPU obtains the read/write result of the I2C device to be accessed through the CPLD chip in S302 by using the SPI may be implemented as follows: and the CPU acquires data to be read from the CPLD chip through the SPI. The data to be read is data read by the CPLD chip from a register corresponding to the register address in the I2C device to be accessed through the I2C analog interface.

The data to be read belongs to the read result of the I2C device to be accessed by the CPLD chip. And the reading result is used for indicating that the reading is successful or failed, and when the reading result is the reading success, the reading result comprises the data to be read, which is read by the CPLD chip. When the reading result is reading failure, the reading result also comprises a failure reason.

In the embodiment of the invention, if the CPLD chip can read the data to be read from the I2C device, the reading success is determined, the CPLD chip can store the reading result, and the reading result is used for indicating the reading success and comprises the data to be read. Or, if the CPLD chip cannot read data to be read from the I2C device, that is, after sending a read signal to the I2C device, if an ACK message fed back by the I2C signal is not received within a specified time, it is determined that the reading fails, and the CPLD chip may store a read result, where the read result is used to indicate that the reading fails.

Accordingly, the CPU can acquire the read result from the CLPD chip through the SPI.

When the CPU needs to read data from the register of the I2C device, the CPU in the embodiment of the present invention may send a read instruction to the CPLD chip, and the CPLD chip completes the data reading operation, at this time, the CPU may process other services. Because the CPU and the CPLD chip are communicated through the SPI, the data transmission speed of the SPI is far higher than that of the I2C, and compared with the situation that the CPU directly reads data through an I2C interface, the data processing method and the data processing device can improve the reading speed and avoid the situation that the CPU cannot process other services because the CPU reads the data in an I2C device.

In another embodiment of the present invention, when there are multiple access instructions, the CPU may send multiple access instructions to the CPLD chip through the SPI, so that the CPLD chip performs read-write operations on the I2C device to which each access instruction is directed through the I2C analog interface, and stores read-write results of each read-write operation.

Correspondingly, in the above S302, the reading and writing result of the CPU obtaining the CPLD chip to the I2C device to be accessed through the SPI may be implemented as:

and the CPU acquires the read-write result of the CPLD chip to the I2C device to which each access instruction aims through the SPI.

Therefore, after the CPU sends the multiple access instructions to the CPLD chip, the CPU can continue to process other services, and after the CPLD chip completes the read-write operation on the I2C device to which the multiple access instructions are directed, the CPU can read multiple read-write results from the CPLD chip at one time.

The embodiment of the invention also provides a data access method, which is applied to the CPLD chip, wherein the CPLD chip is positioned in the switch shown in the figure 2. As shown in fig. 4, the method includes the steps of:

s401, receiving an access instruction sent by the CPU through the SPI. Wherein the access instruction comprises a physical address and a register address of the I2C device to be accessed.

The CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as a logic register of the CPLD chip. The CPU can access the logic register of the CPLD chip through the state machine of the internal logic code of the CPLD chip so as to send an access instruction to the CPLD chip.

S402, based on the access command, performing read-write operation on the I2C device to be accessed through the I2C analog interface, and storing the read-write result, so that the CPU can obtain the read-write result of the I2C device to be accessed through the CPLD chip through the SPI.

The CPLD chip 202 includes a plurality of I/O pins, and for some of the I/O pins of the CPLD chip 202, SCL signals and SDA signals transmitted by the I2C interface can be respectively simulated at two I/O pins of the CPLD chip through logic codes, so that two I/O pins are simulated as one I2C interface.

According to the data access method provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip is connected with the I2C device through an I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip carries out read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD chip, the CPU only needs to send an access instruction to the CPLD chip through the SPI, and the CPU can process other services when the CPLD chip performs read-write operation on the I2C device. And because the speed of the SPI is higher than the speed of the I2C bus, the CPU obtains the read-write result from the CPLD chip through the SPI, and compared with the prior art that the CPU accesses the I2C device through the I2C interface, the CPU time occupation caused by accessing the I2C device can be reduced, the data access efficiency is improved, and the time of the CPU for processing other services is increased.

In the embodiment of the invention, when the CPU needs to write data into the I2C device, the access instruction is a write instruction, and the access instruction carries data to be written. Referring to fig. 5, in the S402, the CPLD chip performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and the storage of the read-write result can be realized through the following steps:

and S501, sending address signals to each I2C device connected with the CPLD chip through the I2C analog interface of the CPLD chip. Wherein the address signal includes a physical address of the I2C device to be accessed.

And S502, receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface.

The confirmation message is sent when the physical address in the confirmation address signal is the same as the own physical address after the device to be accessed I2C receives the address signal. The acknowledgement message may be an ACK message.

S503, writing the data to be written into the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the I2C device to be accessed.

S504, receiving a write response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed, and storing a write result of data to be written based on the write response.

Wherein the writing result is used to indicate a write success or a write failure.

In the embodiment of the invention, after the CPLD chip writes data to be written into the I2C device, if an ACK message fed back by the I2C device is received within a specified time, the writing is determined to be successful; or, if the CPLD chip does not receive the ACK message fed back by the I2C device within the specified time length after the data to be written is written into the I2C device, determining that the writing fails. And after receiving the ACK message for indicating the successful writing, the CPLD chip stores a writing result for indicating the successful writing. And if the CPLD chip does not receive the ACK message for indicating successful writing within the specified time length after the data to be written is written into the I2C device, storing a writing result for indicating failed writing.

When the CPU in the embodiment of the invention needs to write data into the register of the I2C device, a write-in instruction can be sent to the CPLD chip, the CPLD chip finishes data write-in work, and the CPU can process other services in the data write-in process of the CPLD. Because the CPU and the CPLD chip are communicated through the SPI, the data transmission speed of the SPI is far higher than that of the I2C, and compared with the situation that the CPU directly writes data into an I2C device through an I2C interface, the data writing speed of the CPU can be improved, and the situation that the CPU cannot process other services because the CPU writes data into the I2C device is avoided.

In the embodiment of the present invention, when the CPU needs to read data from the I2C device, the access instruction is a read instruction. Referring to fig. 6, in the S402, the CPLD chip performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and the storage of the read-write result can be realized through the following steps:

and S601, transmitting address signals to each I2C device connected with the CPLD chip through the I2C analog interface of the CPLD chip. Wherein the address signal includes a physical address of the I2C device to be accessed.

And S602, receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface.

After receiving the address signal, the device to be accessed I2C sends an acknowledgement message when the physical address in the acknowledgement address signal is the same as its own physical address. The acknowledgement message may be an ACK signal.

And S603, reading the data to be read from the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the I2C device to be accessed and the I2C device to be accessed.

And S604, storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.

In the embodiment of the invention, the CPU can read the data to be read once from the CPLD chip at intervals, thereby reducing the situation that the CPU reads the data to be read for many times, reducing the occupation of CPU resources, and simultaneously improving the management efficiency of the I2C bus, thereby improving the operation efficiency of the switch.

In the switch, if an error occurs in the I2C bus of the CPU during data access (for example, the CPU does not receive a response from the I2C device during reading data from the I2C device or writing data to the I2C device), the I2C bus is suspended, and the CPU can continue to access the I2C device after the I2C bus is restored.

The conventional method of restoring the I2C bus is: the CPU continuously sends 9 high level signals through the GPIO pin, namely the CPU continuously sets the GPIO pin to be high level for 9 times. When a special circuit on a single board where the CPU is located monitors continuous 9 high-level signals sent by the GPIO pin, the SCL clock signal of the I2C bus is pulled down for 9 times continuously to recover the I2C bus.

This approach to restoring the I2C bus requires additional special circuitry on the board, which increases both the complexity of restoring the I2C bus and the hardware cost of the switch.

In the embodiment of the present invention, the manner of recovering the I2C bus connected to the CPLD chip includes: if a recovery command of the CPU to the designated I2C analog interface is received through the SPI bus, an SCL clock signal of the designated I2C analog interface is pulled down for 9 times continuously. Wherein, the I2C simulation interface is designated as the I2C simulation interface with errors.

The CPU obtains a read-write result from the CPLD chip, if the read-write result is used for indicating read/write failure, the CPU sends a recovery command to the CPLD chip through the SPI, after the CPLD receives the recovery command, the I2C bus is simulated through an internal logic code, and an SCL clock signal of a specified I2C simulation interface is continuously pulled down for 9 times so as to recover the I2C bus.

Therefore, the I2C bus is restored by directly utilizing the CPLD chip in the embodiment of the invention, and because the CPLD chip is arranged in the single board of the switch, the I2C bus is restored in the embodiment of the invention without adding extra hardware in the switch, thereby reducing the hardware cost of the switch.

Based on the same inventive concept, corresponding to the above method embodiment, an embodiment of the present invention provides that, an embodiment of the present invention provides a data access apparatus, which is applied to a CPU, where the CPU is located in the switch shown in fig. 2, as shown in fig. 7, the apparatus includes: a writing module 701 and an obtaining module 702;

the write-in module 701 is configured to send an access instruction to the CPLD chip through the SPI, where the access instruction includes a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and obtains a read-write result;

the obtaining module 702 is configured to obtain, through the SPI, a read-write result of the I2C device to be accessed by the CPLD chip.

Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the obtaining module 702 is specifically configured to:

and acquiring a writing result of the data to be written from the CPLD chip through the SPI, wherein the writing result is used for indicating writing success or writing failure.

Optionally, the access instruction is a read instruction; the obtaining module 702 is specifically configured to:

and acquiring data to be read from the CPLD chip through the SPI, wherein the data to be read is data read from a register corresponding to the register address in the I2C device to be accessed by the CPLD chip through an I2C analog interface.

Based on the same inventive concept, corresponding to the above method embodiment, the embodiment of the present invention provides a data access device, which is applied to a CPLD chip, where the CPLD chip is located in the switch of the above embodiment. As shown in fig. 8, the apparatus includes: a receiving module 801 and an accessing module 802;

the receiving module 801 is configured to receive an access instruction sent by the CPU through the SPI, where the access instruction includes a physical address and a register address of an I2C device to be accessed;

the access module 802 is configured to perform read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and store a read-write result, so that the CPU obtains the read-write result of the I2C device to be accessed through the SPI.

Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the access module 802 is specifically configured to:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

writing data to be written into a register corresponding to a register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the I2C device to be accessed;

and receiving a write response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and storing a write result of the data to be written based on the write response, wherein the write result is used for indicating write success or write failure.

Optionally, the access instruction is a read instruction;

the access module 802 is specifically configured to:

sending address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;

receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the own physical address after the I2C device to be accessed receives the address signal;

reading data to be read from a register corresponding to a register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the device to be accessed;

and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.

Optionally, the apparatus further comprises: a pull-down module;

and the pull-down module is used for pulling down the SCL clock signal of the specified I2C analog interface for 9 times continuously if a recovery command of the CPU to the specified I2C analog interface is received through the SPI bus.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.