阅读说明：本技术 记录介质、运算方法以及运算装置 (Recording medium, calculation method, and calculation device ) 是由 伊见仁 冈野资睦 福场义宪 于 2020-08-28 设计创作，主要内容包括：实施方式关于记录模拟用数据的记录介质、运算方法以及运算装置。实施方式的记录介质记录输入到运算装置的模拟数据,所述运算装置执行半导体装置的模拟,所述模拟数据包含记述了模拟对象电路所含的部件的形状的部件形状信息、记述了所述模拟对象电路的动作以及连接信息的模型信息、以及所述模拟对象电路所含的所述部件的符号信息,所述运算装置将所述部件形状信息、所述模型信息以及所述符号信息建立关联而执行所述半导体装置的模拟。(Embodiments relate to a recording medium for recording simulation data, a calculation method, and a calculation device. The recording medium of an embodiment records simulation data input to an arithmetic device that executes a simulation of a semiconductor device, the simulation data including part shape information in which shapes of parts included in a simulation target circuit are described, model information in which operations and connection information of the simulation target circuit are described, and symbol information of the parts included in the simulation target circuit, and the arithmetic device executes the simulation of the semiconductor device by associating the part shape information, the model information, and the symbol information.)

1. A recording medium recording simulation data input to an arithmetic device that performs simulation of a semiconductor device, wherein,

the analog data includes:

part shape information describing the shape of a part included in the circuit to be simulated;

model information describing operation and connection information of the circuit to be simulated; and

symbol information of the component included in the analog object circuit,

the arithmetic device associates the part shape information, the model information, and the symbol information to execute the simulation of the semiconductor device.

2. The recording medium according to claim 1,

the part shape information includes information that specifies an outer shape of the part.

3. The recording medium according to claim 2,

the part shape information includes position information of a corner of the part.

4. The recording medium according to claim 1,

the component shape information includes position information of terminals of the component.

5. The recording medium according to claim 1,

the model information includes connection information of the component and operation information of the component included in the simulation target circuit.

6. The recording medium according to claim 1,

the model information contains information about the terminals of the component,

the information on the terminals of the component includes information indicating a correspondence relationship with the terminals of the component included in the component shape information.

7. The recording medium according to claim 6,

the information on the terminals of the component includes connection information of the terminals of the component.

8. The recording medium according to claim 1,

the model information includes a file name of a file describing an operation of the circuit to be simulated and information for referring to the file.

9. The recording medium according to claim 1,

the symbol information is different for each type of the component, and includes position information of a terminal of the component.

10. The recording medium according to claim 9,

the symbol information includes position information of the terminal of the component described in association with position information of the terminal of the component included in the component shape information.

11. The recording medium according to claim 1,

the part shape information, the model information, and the symbol information are described in a format that is interpreted and executed by an arithmetic unit that executes a simulation of the simulation target circuit.

12. A method of operation, wherein,

inputting simulation data including part shape information describing a shape of a part included in a simulation target circuit, model information describing an operation of the simulation target circuit, and symbol information of the part included in the simulation target circuit,

and performing simulation of the simulation target circuit by associating the part shape information, the model information, and the symbol information.

13. The operation method according to claim 12,

generating the simulation object circuit based on the model information and the sign information,

the generated analog object circuit is verified,

performing layout arrangement of components based on the verified simulation target circuit, the component shape information, and the model information,

verifying the layout configuration of the component.

14. The operation method according to claim 13,

in the verification of the layout arrangement of the components, the arrangement location of the components is verified based on the component shape information and the connection information of the components included in the model information.

15. An arithmetic device is provided with:

an input unit that inputs simulation data including part shape information describing a shape of a part included in a simulation target circuit, model information describing an operation of the simulation target circuit, and symbol information of the part included in the simulation target circuit; and

and an execution unit that associates the part shape information, the model information, and the symbol information to execute a simulation of the simulation target circuit.

16. The arithmetic device according to claim 15, comprising:

a circuit generation unit that generates the simulation target circuit based on the model information and the symbol information;

a 1 st verification unit configured to verify the generated circuit to be simulated;

a layout arrangement unit configured to perform layout arrangement of components based on the verified simulation target circuit, the component shape information, and the model information; and

and a 2 nd verification unit for verifying the layout arrangement of the components.

17. The computing device of claim 16,

the 2 nd verification unit verifies the placement location of the component based on the component shape information and the connection information of the component included in the model information in the verification of the layout placement of the component.

18. The computing device of claim 15,

the part shape information includes information that specifies an outer shape of the part.

19. The computing device of claim 18,

the part shape information includes position information of a corner of the part.

20. The computing device of claim 15,

the component shape information includes position information of terminals of the component.

Technical Field

One embodiment of the present invention relates to a recording medium for recording simulation data, a calculation method, and a calculation device.

Background

In designing a system including electric components such as a motor, simulation based on a circuit diagram or a block diagram cannot be performed in consideration of the arrangement of components and the size of the components in the system. Currently, many studies on the arrangement of components and the size of components in a system are performed manually by an operator on cad (computer Aided design), which takes time to determine the arrangement of components and the size of components.

Disclosure of Invention

An embodiment of the present invention provides a recording medium, a calculation method, and a calculation device for recording simulation data, which can efficiently study the arrangement and dimensions of components in a short time.

A recording medium of an embodiment records simulation data input to an arithmetic device that executes simulation of a semiconductor device,

the simulation data includes part shape information describing a shape of a part included in a circuit to be simulated, model information describing an operation and connection information of the circuit to be simulated, and symbol information of the part included in the circuit to be simulated, and the arithmetic device associates the part shape information, the model information, and the symbol information to execute a simulation of the semiconductor device.

Drawings

Fig. 1 is a diagram showing simulation data according to an embodiment.

Fig. 2A is a plan view showing an example of the member.

Fig. 2B is a diagram showing an example of a symbol indicating the NMOS transistor of fig. 2A.

Fig. 3 is a diagram showing a specific example of the simulation data of fig. 1.

Fig. 4 is a diagram showing an example of an external file.

Fig. 5 is a block diagram showing an example of the internal configuration of the arithmetic device.

Fig. 6 is a flowchart showing an example of the processing operation of the arithmetic device.

Fig. 7 is a circuit diagram showing an example of the simulation target circuit generated in step S2 of fig. 6.

Fig. 8 is a diagram schematically showing an example of the layout arrangement result.

Fig. 9 is a conceptual diagram of the redesign and layout rearrangement of the circuit to be simulated.

Fig. 10A is a signal waveform diagram showing a circuit simulation result of the wiring.

Fig. 10B is a signal waveform diagram showing a case where a circuit to be simulated is generated only from model information and circuit simulation is performed.

Fig. 11 shows a diagram of a signal waveform causing over-radiation.

Detailed Description

Embodiments of a recording medium, a calculation method, and a calculation device for recording simulation data will be described below with reference to the drawings. Hereinafter, the main components of the recording medium, the calculation method, and the calculation device will be mainly described, but the recording medium, the calculation method, and the calculation device may have components and functions that are not shown or described. The following description does not exclude constituent elements and functions not shown or described.

Fig. 1 is a diagram showing simulation data 1 according to an embodiment. The simulation data 1 in fig. 1 includes part shape information I1, model information I2, and symbol information I3. The simulation data 1 of fig. 1 can be recorded on a recording medium. The kind of the recording medium is not particularly specified. For example, the recording medium may be a semiconductor memory, or may be a magnetic recording device, an optical disk, or an opto-magnetic disk.

The component shape information I1 is information describing the shape of a component included in the circuit to be simulated. Here, the shape-describing information is information indicating the outer shape of the semiconductor device, and includes, for example, the size of the semiconductor device, the position information of the corner, and the like. The analog circuit is not limited, and may be an analog circuit, a digital circuit, or a mixture of an analog circuit and a digital circuit. The kind of the component is not particularly specified. The component may be an Integrated Circuit (IC) or may be a discrete component.

Fig. 2A is a plan view showing an example of the member 2. The component 2 in fig. 2A is, for example, an NMOS transistor, and has three terminals T1 to T3. The part shape information I1 includes information that defines the outer shape of the part 2. In the example of fig. 2A, the part shape information I1 contains coordinate information of a corner portion (black circle position of fig. 2A) of the part 2. The component shape information I1 may include positional information of the terminals of the component 2. As shown in fig. 2A, the component shape information I1 may include coordinate information of three terminals.

Model information I2 in fig. 1 is information describing the operation and connection information of the circuit to be simulated. Here, the operation information is information describing what operation the circuit to be simulated performs. The connection information is information indicating a connection relationship between a certain element and another element. More specifically, the information indicating to which terminal of another element each terminal of a certain element is connected, the information indicating to which input terminal or output terminal in the semiconductor device each terminal of a certain element is connected, and the like. From the description of the model information I2, a circuit can be automatically generated in a simulator or the like. The model information I2 includes connection information of the component 2 included in the simulation target circuit and operation information of the component 2. The model information I2 contains information on the terminals of the component 2. The information on the terminals of the component 2 includes information indicating the correspondence relationship with the terminals of the component 2 included in the component shape information I1. More specifically, the information on the terminals of the component 2 includes connection information of the terminals of the component 2. The model information I2 may include a file name of a file describing the operation of the circuit to be simulated and information for referring to the file.

Symbol information I3 in fig. 1 is an index indicating a component 2 included in the circuit to be simulated. The symbol information I3 is only required to be an index that makes the component 2 easily recognizable, and does not necessarily need to be an index of a uniform form. Fig. 2B is a diagram showing an example of reference numeral 3, and reference numeral 3 shows an NMOS transistor of fig. 2A. In reference numeral 3 in fig. 2B, three terminals T1 to T3 are provided in correspondence with the terminals T1 to T3 in fig. 2A. Note that, since the terminal name indicated by symbol 3 is described in correspondence with the terminal name indicated by component shape information I1 in symbol information I3, the terminal name indicated by component shape information I1 and the terminal name indicated by symbol 3 do not necessarily have to be the same. The symbol information I3 differs for each type of component 2, and includes positional information of the terminal of the component 2. The symbol information I3 is described in association with the position information of the terminal of the component 2 included in the component shape information I1.

The simulation data 1 in fig. 1 can be stored in one file (hereinafter, may be referred to as an integrated file). The file is generated in a form that can be interpreted and executed by a computer. Further, the file may be downloaded from a specific website, for example. The downloaded file can be interpreted and executed by the computer at the download site. The computer can generate a circuit and verify (simulate) the operation of the generated circuit by executing the simulation data in the integrated file. Instead of a computer, the integrated file may be input to a dedicated simulator for simulation. In the present specification, a computer or the like that interprets and executes an integrated file is collectively referred to as an arithmetic device.

Fig. 3 is a diagram showing a specific example of the simulation data 1 in fig. 1, and is the content of the integrated file. The simulation data 1 in fig. 3 shows a description example of an NMOS transistor as the component 2 in fig. 2A and 2B. The simulation data 1 in fig. 3 is text information made of ASCII code, and includes part shape information I1, model information I2, and symbol information I3. In the example of fig. 3, the component shape information I1, the model information I2, and the symbol information I3 are described in this order, but the order in which the respective pieces of information are described is arbitrary.

The part shape information I1 in fig. 3 includes a row group Ln1 describing the coordinates of the external shape of the part 2, and a row group Ln2 describing the identification information and the coordinates of the terminals T1 to T3 of the part 2. As shown in fig. 2A, the terminals T1 to T3 of the component 2 have predetermined lengths and widths, respectively, and the center coordinates of the region in which the terminals T1 to T3 are described in the row group Ln 2.

The external file "nmos. lib" is referred to in line 1 of line Ln3 describing model information I2 of fig. 3. The external file is a file describing the operation and connection information of the circuit to be simulated. Fig. 4 is a diagram showing an example of an external file. The external file of fig. 4 describes terminal information, characteristics, operation, connection information, and the like of the NMOS transistor as the component 2 of fig. 2A and 2B. The characteristics include, for example, the width of the gate electrode of the NMOS transistor, the length of the gate electrode, the thickness of the gate insulating film, and the voltage range to which the gate electrode is supplied.

In fig. 3, correspondence between each terminal of the NMOS transistor in the block shape information I1 and each terminal of the NMOS transistor in the model information I2 is described below line 2 in the line group Ln3 describing the model information I2. For example, since the identification IDs corresponding to the terminals T1 to T3 are set to "1" to "3" for the NMOS transistors in the component shape information I1, and the NMOS transistors in the model information I2 have the identification IDs "a", "B", and "C" corresponding to the terminals T1 to T3, it is described that "1" is associated with "a", "2" is associated with "B", and "3" is associated with "C".

Symbol information I3 in fig. 3 includes a row group Ln4 describing the external shape of the symbol, and a row group Ln5 describing the correspondence relationship between the terminal A, B, C of the symbol and the terminals T1 to T3 of the NMOS transistor in the part shape information I1. Fig. 3 shows an example of the model information I2, and the format of the model information I2 is arbitrary.

The integrated file including the simulation data 1 shown in fig. 3 may be stored in a storage unit, not shown, as needed. The simulation data 1 shown in fig. 3 is read out by an arithmetic device such as a simulator, and the contents of the integrated file are interpreted to execute simulation.

Fig. 5 is a block diagram showing an example of the internal configuration of the arithmetic device 10. The arithmetic device 10 of fig. 5 includes an input unit 11, a component information storage unit 12, a symbol information storage unit 13, an external file storage unit 14, an execution unit 15, an output unit 16, and a verification unit 17. The arithmetic device 10 of fig. 5 executes a simulation of the semiconductor device. The arithmetic device 10 associates the component shape information I1, the model information I2, and the symbol information I3 with each other, and uses the simulation data 1 to perform a simulation of the semiconductor device.

The input unit 11 inputs the integrated file shown in fig. 3. The operator may input the integrated file of fig. 3 by a keyboard or the like. Alternatively, the integrated file may be electronically acquired from an electric device having a communication function via the input unit 11.

The component information storage unit 12 stores various kinds of component information. As shown in fig. 2A, the component information is information on the external shape, size, number of terminals, terminal position, and the like of the component 2.

The symbol information storage unit 13 stores symbol information I3 of various components 2. The symbol information I3 is, as shown in fig. 2B, the symbol of each component 2, the terminal information included in the symbol, and the like.

The external file storage unit 14 stores an external file described in the model information I2. In the case where the operation and connection information of the circuit to be simulated are described directly in the model information I2 without referring to an external file, the external file storage unit 14 may not be provided.

The execution unit 15 reads and interprets the part shape information I1, the model information I2, and the sign information I3 described in the input integrated file, generates a simulation target circuit based on the part shape information I1, the model information I2, and the sign information I3, and executes a simulation based on the generated circuit.

As will be described later, the simulation performed by the execution unit 15 includes a plurality of simulations such as a circuit simulation, an electromagnetic field simulation, and a temperature simulation. In the present description, an example is shown in which the same execution unit 15 performs a plurality of simulations, but different simulations may be performed by a plurality of arithmetic devices 10 (simulators).

The output unit 16 outputs the simulation result executed by the execution unit 15. The output form of the simulation result is arbitrary.

The verification unit 17 verifies whether or not the circuit or layout arrangement generated based on the integrated file is appropriate based on the simulation result output from the output unit 16, and if not, changes the circuit or layout arrangement.

Fig. 6 is a flowchart showing an example of the processing operation of the arithmetic device 10. First, the integrated file is input via the input unit 11 (step S1). Next, the execution unit 15 reads out and interprets the integration file, and generates a simulation target circuit based on the part shape information I1, the model information I2, and the symbol information I3 (step S2). The generated simulation target circuit is output from the output unit 16.

Fig. 7 is a circuit diagram showing an example of the simulation target circuit generated in step S2 of fig. 6. The circuit to be simulated in fig. 7 includes a motor 21, a plurality of transistors 22 for controlling the drive of the motor 21, and a control unit 23 for controlling the gate voltages of the transistors 22 as the main components 2. The sign of each component 2 included in the analog target circuit of fig. 7 is the sign included in the sign information I3.

Next, the execution unit 15 and the verification unit 17 verify the operation of the circuit to be simulated by using the circuit simulator (step S3). Next, it is determined whether there is a problem in the operation of the circuit to be simulated based on the simulation result of the circuit simulator (step S4). If there is a problem in operation, the process from step S2 onward is repeated. In addition, in some cases, when it is determined that there is a problem in step S4, a new integrated file may be newly input. In this case, the process from step S1 onward is repeated.

If it is determined in step S4 that there is no problem with the operation, the layout arrangement is performed based on the simulation target circuit whose operation has been verified (step S5). Although the arithmetic device 10 of the present embodiment may be arranged in a layout, the processing in step S5 and thereafter may be performed by another arithmetic device 10 or the like. Alternatively, the arithmetic device 10 of the present embodiment may rely on the layout arrangement processing for another device that performs the layout arrangement, and may acquire the layout arrangement result and perform the processing after step S5.

Fig. 8 is a diagram showing an example of the layout arrangement result. In the example of fig. 8, the motor 21 of fig. 7 is disposed in the disposition region r1, the plurality of transistors 22 are disposed in the disposition region r2, and the controller 23 is disposed in the disposition region r 3.

After the layout arrangement is performed in step S5 of fig. 6, the arithmetic device 10 performs electromagnetic field simulation based on the layout arrangement result (step S6). Next, it is determined whether there is a problem in the result of the electromagnetic field simulation (step S7). For example, when it is determined that electromagnetic Interference (EMI) noise generated from a part of the layout region of the semiconductor device exceeds a predetermined threshold value by electromagnetic field simulation, it is determined that there is a problem.

If it is determined in step S7 that there is no problem, it is determined whether or not a layout change is to be performed (step S8). If it is determined that the layout change is to be performed, the process from step S5 onward is repeated. On the other hand, for example, if it is determined that the problem in step S7 is not solved to the extent of the layout change, the processing in and after step S2 is repeated.

If it is determined in step S7 that there is no problem, the layout arrangement result of step S5 is output via the output unit 16 (step S9).

Since the simulation data 1 of the present embodiment includes not only the model information I2 but also the part shape information I1 and the symbol information I3, it is possible to easily and automatically select the symbol of the part 2 used in the circuit to be simulated, and to quickly generate the circuit to be simulated. In addition, even when the layout arrangement is performed, the layout arrangement can be performed in consideration of the shape and size of the component 2 based on the component shape information I1, and the estimation of the wiring length and the wiring capacity between the components 2 becomes easy. In addition, the operation verification of the circuit to be simulated can be performed while considering the wiring length and the wiring capacity between the respective components 2 estimated by the layout arrangement in the circuit simulation, and while making each wiring have a wiring delay close to the actual wiring delay.

Fig. 9 is a conceptual diagram in which the simulation result of the simulation target circuit (upper side in fig. 9) 24 and the result of the layout (lower side in fig. 9) 25 generated by the arithmetic device 10 of the present embodiment are used together to perform the redesign of the simulation target circuit and the rearrangement of the layout.

For example, as shown in the layout arrangement 25 of fig. 9, a case where the wiring lengths L1, L2 from the control section 23 to the gate of the transistor 22 differ depending on the transistor 22 will be described.

Since the simulation data 1 of the present embodiment includes the component shape information I1, when performing layout arrangement, the components 2 can be arranged in consideration of the component shape and size, and the wiring connection between the components 2 can be performed. For example, in the layout configuration of fig. 9, a result that the wiring L1 is longer than the wiring L2 can be obtained. The longer the wiring length, the larger the wiring capacity becomes and the wiring delay becomes easy to be caused. Therefore, by reflecting the result of the layout arrangement in the circuit simulation using the left-side simulation object circuit in fig. 9, the circuit simulation can be performed based on the information that the wiring delay of the additional wiring L1 is larger than that of the wiring L2.

Fig. 10A is a signal waveform diagram showing the circuit simulation results of the wirings L1 and L2. The wiring L1 is longer than the wiring L2 in wiring length and larger in wiring capacity, and therefore, the rising timing of the waveform is delayed from the wiring L2 and the waveform is also gentle. However, in the circuit simulation of the present embodiment, the difference in the wiring length can be taken into consideration based on the layout arrangement result, and therefore, it is possible to predict the shift in the rise timing due to the difference in the wiring length and perform the operation verification of the circuit to be simulated.

Fig. 10B is a signal waveform diagram in the case where a circuit to be simulated is generated and circuit simulation is performed using only the model information I2 without using the component shape information I1 and the symbol information I3. In the case of fig. 10B, since the difference in the wiring length cannot be taken into consideration, the rise timings of the wirings L1 and L2 in fig. 9 are regarded as the same, and the accuracy of the operation verification of the circuit simulation is lowered.

Although fig. 9 shows an example in which the result of layout arrangement based on the component shape information I1 is reflected in the circuit simulation, it is possible to perform thermal simulation under conditions similar to actual operation by calculating the loss information of each component 2 from the result of the circuit simulation and using the calculated loss information as the conditions for thermal simulation in the physical shape.

For example, attention is directed to the wirings L1 and L2 in fig. 9. Assuming that a circuit simulation is performed using the circuit to be simulated in fig. 9, signal waveforms of the wiring L1 and the wiring L2 are as shown in fig. 11. The wiring L1 has a larger radiation than the wiring L2, and the amount of heat generated by the transistor 22 connected to the wiring L1 is expected to be larger. That is, it can be predicted that the heat loss of the wiring L1 is larger than that of the wiring L2. Therefore, by giving the thermal loss information obtained by the circuit simulation to the thermal simulation, the thermal simulation can be performed with the transistors 22 arranged in the layout as transistors having a larger heat generation amount than the transistors 22.

Thus, in the present embodiment, the simulation data 1 including not only the model information I2 but also the component shape information I1 and the symbol information I3 is generated, and therefore, the simulation can be performed in a state close to the actual arrangement of the components 2 and the wiring arrangement, and the accuracy of the simulation can be improved.

In addition, the selection of the component 2 symbol used in the circuit to be simulated can be performed quickly, and the circuit to be simulated can be generated quickly in accordance with the intention of the designer. Further, by using the component shape information I1, the shape and size of the component 2 arranged in the layout area can be made closer to the shape and size of the actual component.

Further, according to the present embodiment, by performing the layout arrangement based on the component shape information I1, it is possible to grasp the difference in the wiring length from the layout arrangement result, and by reflecting the difference in the wiring length to the circuit simulation, it is possible to perform the circuit simulation taking the wiring delay into consideration.

Further, according to the present embodiment, the loss information of each component 2 can be estimated from the result of the circuit simulation, and the temperature distribution in the layout area can be predicted with high accuracy by reflecting the loss information to the thermal simulation.

The simulation data 1 in fig. 1 may be data in the form of a program executable by the arithmetic device 10. That is, the simulation data 1 in fig. 1 may be described as a program format in which the part shape information I1, the model information I2, and the symbol information I3 are different parameters. More specifically, one or more functions executable by the arithmetic device 10 may be described in the program, and the program may be given component shape information I1, model information I2, and symbol information I3 as arguments of the functions.

At least a part of the arithmetic device 10 described in the above embodiment may be constituted by hardware or may be constituted by software. In the case of software, a program for realizing at least a part of the functions of the arithmetic device 10 may be stored in a recording medium such as a flexible disk or a CD-ROM, and may be read and executed by a computer. The recording medium is not limited to a removable recording medium such as a magnetic disk or an optical disk, and may be a fixed recording medium such as a hard disk device or a memory.

The program for realizing at least a part of the functions of the arithmetic device 10 may be distributed via a communication line (including wireless communication) such as the internet. Further, the same program may be encrypted, modulated, compressed, and distributed via a wired line such as the internet, a wireless line, or stored in a recording medium.