阅读说明：本技术 记录介质、运算方法以及运算装置 (Recording medium, calculation method, and calculation device ) 是由 伊见仁 冈野资睦 福场义宪 于 2020-08-28 设计创作，主要内容包括：实施方式关于记录模拟用数据的记录介质、运算方法以及运算装置。实施方式的记录介质记录输入到运算装置的模拟数据,所述运算装置执行半导体装置模拟,所述模拟数据包含了记述半导体装置的形状以及端子信息的部件形状信息、记述了所述半导体装置内的元件的动作以及连接信息的逻辑模型信息、以及记述了所述半导体装置内的功能块的位置信息的功能块信息,所述运算装置将所述部件形状信息、所述逻辑模型信息以及所述功能块信息建立关联而执行所述半导体装置模拟执行。(Embodiments relate to a recording medium for recording simulation data, a calculation method, and a calculation device. The recording medium of an embodiment records simulation data input to an arithmetic device that executes a simulation of a semiconductor device, the simulation data including component shape information in which a shape and terminal information of the semiconductor device are described, logic model information in which an operation and connection information of an element in the semiconductor device are described, and function block information in which position information of a function block in the semiconductor device is described, and the arithmetic device executes the simulation of the semiconductor device by associating the component shape information, the logic model information, and the function block information.)

1. A recording medium recording simulation data input to an arithmetic device that performs simulation of a semiconductor device, wherein,

the analog data includes:

part shape information describing a shape of the semiconductor device and terminal information;

logic model information describing operation and connection information of elements in the semiconductor device; and

functional block information describing positional information of functional blocks in the semiconductor device,

the arithmetic device associates the component shape information, the logic model information, and the function block information to execute a simulation of the semiconductor device.

2. The recording medium according to claim 1,

the functional block information includes information specifying an outer shape of a functional block in the semiconductor device and position information of the functional block in the semiconductor device.

3. The recording medium according to claim 1,

the position information of the functional block is described in association with the terminal information included in the component shape information.

4. The recording medium according to claim 1,

the logic model information includes connection information of logic blocks within the semiconductor device,

the logic model information also has corresponding information of the logic block and the function block.

5. The recording medium according to claim 4,

the logic model information includes terminal information of the logic block described in association with the terminal information included in the component shape information.

6. The recording medium according to claim 1,

the logic model information includes a file name of a file describing an operation of the semiconductor device and information for referring to the file.

7. The recording medium according to claim 1,

the component shape information includes information that defines an outer shape of the semiconductor device.

8. The recording medium according to claim 7,

the component shape information includes position information of a corner portion of the semiconductor device.

9. The recording medium according to claim 1,

the component shape information includes position information of terminals of the semiconductor device.

10. The recording medium according to claim 1,

the component shape information, the logic model information, and the function block information are described in a format that can be interpreted and executed by an arithmetic unit that executes a simulation of a circuit to be simulated.

11. A method of operation, wherein,

inputting simulation data including component shape information in which a shape and terminal information of a semiconductor device are described, logic model information in which an operation and connection information of an element in the semiconductor device are described, and function block information in which position information of a function block in the semiconductor device is described,

and associating the part shape information, the logic model information, and the function block information to execute a simulation of the semiconductor device.

12. The operation method according to claim 11,

generating the simulation object circuit based on the part shape information, the logic model information, and the function block information,

the generated analog object circuit is verified,

performing layout arrangement of components based on the verified simulation object circuit,

verifying the layout configuration of the component.

13. The operation method according to claim 11,

at least one of heat and noise generated inside the semiconductor device during the simulation of the semiconductor device is verified.

14. An arithmetic device is provided with:

an input unit that inputs simulation data including component shape information in which a shape and terminal information of a semiconductor device are described, logic model information in which an operation and connection information of an element in the semiconductor device are described, and function block information in which position information of a function block in the semiconductor device is described; and

and an execution unit that associates the component shape information, the logic model information, and the function block information to execute a simulation of the semiconductor device.

15. The arithmetic device according to claim 14, comprising:

a circuit generation unit that generates the simulation target circuit based on the component shape information, the logic model information, and the function block information;

a 1 st verification unit configured to verify the generated circuit to be simulated;

a layout arrangement unit configured to perform layout arrangement of components based on the verified simulation target circuit; and

and a 2 nd verification unit for verifying the layout arrangement of the components.

16. The computing device of claim 14,

the 1 st verification unit verifies at least one of heat and noise generated inside the semiconductor device during the simulation of the semiconductor device.

17. The computing device of claim 14,

the functional block information includes information specifying an outer shape of a functional block in the semiconductor device and position information of the functional block in the semiconductor device.

18. The computing device of claim 14,

the position information of the functional block is described in association with the terminal information included in the component shape information.

19. The computing device of claim 14,

the logic model information includes connection information of logic blocks within the semiconductor device,

the logic model information also has corresponding information of the logic block and the function block.

20. The computing device of claim 19,

the logic model information includes terminal information of the logic block described in association with the terminal information included in the component shape information.

Technical Field

One embodiment of the present invention relates to a recording medium for recording simulation data, a calculation method, and a calculation device.

Background

It is known that, in verifying physical characteristics such as heat generation and electromagnetic Interference (EMI) in a semiconductor device such as an lsi (large Scale Integrated circuit), simulation is performed in which a specific excitation source and a specific power source are set in physical circuit blocks in the semiconductor device.

However, the physical characteristics generated when the semiconductor device is actually operated are different from those of the excitation source and the power source which are fixed, and thus the verification cannot be performed accurately.

Disclosure of Invention

One embodiment of the present invention provides a recording medium, a calculation method, and a calculation device for recording simulation data capable of suppressing heat generation and noise by performing operation verification corresponding to actual operation of a semiconductor device.

A recording medium according to an embodiment of the present disclosure records simulation data input to an arithmetic device that executes a simulation of a semiconductor device, the simulation data including component shape information in which a shape and terminal information of the semiconductor device are described, logic model information in which an operation of an element in the semiconductor device and connection information are described, and function block information in which position information of a function block in the semiconductor device is described, and the arithmetic device executes the simulation of the semiconductor device by associating the component shape information, the logic model information, and the function block information.

Drawings

Fig. 1 is a diagram showing simulation data according to an embodiment.

Fig. 2A is a plan view showing an example of the semiconductor device.

Fig. 2B is a diagram showing an example of elements in the semiconductor device.

Fig. 2C is a diagram showing an example of the function block 4.

Fig. 3A is a schematic diagram showing elements in the semiconductor device created by the integration file.

Fig. 3B is a schematic diagram showing functional blocks in the semiconductor device generated by integrating files.

Fig. 4 is a diagram showing a specific example of simulation data as the content of the integrated file corresponding to fig. 3.

Fig. 5 is a block diagram showing an example of the internal configuration of the arithmetic device.

Fig. 6 is a flowchart showing an example of the processing operation of the arithmetic device.

Fig. 7A is a schematic diagram showing the result of thermal simulation of the present embodiment.

Fig. 7B is a schematic diagram showing output signal waveforms of elements corresponding to functional blocks in the semiconductor device.

Detailed Description

Embodiments of a recording medium, a calculation method, and a calculation device are described below with reference to the drawings. Hereinafter, the main components of the recording medium, the calculation method, and the calculation device will be mainly described, but the recording medium, the calculation method, and the calculation device may have components and functions that are not shown or described. The following description does not exclude constituent elements and functions not shown or described.

Fig. 1 is a diagram showing simulation data 1 according to an embodiment. The simulation data 1 in fig. 1 includes component shape information I1, logical model information I2, and function block information I3. The simulation data 1 of fig. 1 can be recorded on a recording medium. The kind of the recording medium is not particularly specified. For example, the recording medium may be a semiconductor memory, or may be a magnetic recording device, an optical disk, or an opto-magnetic disk.

The component shape information I1 is information describing the shape of the semiconductor device and the terminal information. As the semiconductor device, a semiconductor device which performs digital operation and a semiconductor device which performs analog operation are applicable. Here, the shape information is information indicating the outer shape of the semiconductor device, and includes, for example, the size of the semiconductor device, corner position information, and the like. The terminal information is information on the terminal names and terminal positions of the input terminals and output terminals of the semiconductor device.

Fig. 2A is a plan view showing an example of a semiconductor device 2 as a component. Fig. 2A shows an example of a DIP (Dual In-line Package) type semiconductor device 2, but the Package shape of the semiconductor device 2 is not defined. The semiconductor device 2 of the present embodiment can be applied to any Package shape such as SIP (Single In-line Package), PGA (Pin Grid Array), SOP (Small Outline Package), BGA (Ball Grid Array), and the like.

Logical model information I2 in fig. 1 is information describing the operation and connection information of elements in semiconductor device 2. Any element in the semiconductor device 2 can be an object of the element. Here, the operation information is information describing what kind of operation the semiconductor device 2 performs. The connection information is information indicating a connection relationship between a certain element and another element. More specifically, the information indicates which terminal of another element is connected to each terminal of a certain element, and the information indicates which input terminal or output terminal of the semiconductor device 2 is connected to each terminal of a certain element.

Fig. 2B is a diagram showing an example of the element 3 in the semiconductor device 2. The element 3 includes an element 3 not connected to the output terminal of the semiconductor device 2 and an element 3 connected to the output terminal. In this specification, an example in which these elements 3 are not distinguished will be described, but these elements 3 may be distinguished.

The functional block information I3 in fig. 1 is information describing at least positional information of functional blocks in the semiconductor device 2. A functional block is a circuit implementing a corresponding function, and is made up of one or more elements 3. On the other hand, a logical block refers to one or more elements 3 that perform respective logical operations. The function block information I3 may include information defining the external shape of the function block in the semiconductor device 2 and position information of the function block in the semiconductor device 2. The function block information I3 may also include connection information of the terminals included in the component shape information I1.

Fig. 2C is a diagram showing an example of the function block 4. Fig. 2C shows a functional block 4a for computing an AND (logical product) AND a functional block 4b for computing an OR (logical sum). Since the function block information I3 includes positional information within the semiconductor device 2, it is possible to specify at which location within the semiconductor device 2 each function block 4 is disposed, by the function block information I3.

The simulation data 1 in fig. 1 can be stored in one file (hereinafter, may be referred to as an integrated file). The file is generated in a form that can be interpreted and executed by a computer. Further, the file may be downloaded from a specific website, for example. The downloaded file can be interpreted and executed by the computer at the download site. The computer can generate a circuit and verify (simulate) the operation of the generated circuit by executing the simulation data in the integrated file. Instead of a computer, the integrated file may be input to a dedicated simulator for simulation. In the present specification, a computer or the like that interprets and executes an integrated file is collectively referred to as an arithmetic device.

Fig. 3A and 3B are schematic diagrams showing circuits in the semiconductor device 2 generated from the integration file. IN the example of fig. 3A, the semiconductor device 2 includes input terminals IN1 to IN4, a power supply terminal VDD, a ground terminal GND1, a ground terminal GND2, and an output terminal OUT. The input terminals IN1 AND IN2 are connected to AND gates, the input terminals IN3 AND IN4 are connected to OR gates, AND output terminals of these AND gates AND OR gates are connected to the output terminal OUT of the semiconductor device 2. Fig. 3B is a diagram showing the position information of the function block 4 included in the integrated file. In the example of fig. 3B, an example is shown in which the functional block 4a corresponding to the AND gate is arranged slightly above the center of the semiconductor device 2, AND the functional block 4B corresponding to the OR gate is arranged slightly below the center of the semiconductor device 2. Thus, the circuit and the layout arrangement thereof shown in fig. 3A and 3B can be generated by executing the integration file by a computer or a simulator.

Fig. 4 is a diagram showing a specific example of the simulation data 1 as the content of the integrated file corresponding to fig. 3. The simulation data 1 in fig. 4 includes part shape information I1, logic model information I2, function block information I3, and correspondence information I4 of function blocks and logic blocks. Simulation data 1 in fig. 4 shows a description example of the internal circuit of the semiconductor device 2 shown in fig. 3A and 3B. The simulation data 1 in fig. 4 is text information made of ASCII code, and includes part shape information I1, logical model information I2, function block information I3, and correspondence information I4 of function blocks and logical blocks. In the example of fig. 4, the component shape information I1, the logical model information I2, the functional block information I3, and the correspondence information I4 are described in this order, but the order of description of each information is arbitrary.

The component shape information I1 in fig. 4 includes a row Ln1 describing the coordinates of the external shape of the component, and a row group Ln2 describing the identification IDs "1" to "5" of the terminals T1 to T5 of the component and the coordinates. As shown in fig. 4, the component terminals T1 to T5 have predetermined lengths and widths, respectively, but the center coordinates of the regions of the terminals T1 to T5 are described in the line Ln 2.

The logic model information I2 in fig. 4 includes a row group Ln3 in which connection information and terminal information of the elements 3 in the semiconductor device 2 are sequentially described. Line 1 of logic model information I2 refers to external file "logic. In line 2 AND thereafter, correspondence information between terminal information included in the component shape information I1 of the AND gate 3a AND terminal information in an external file, AND the like are described. Similarly, connection information of the OR gate 3b is described in logic model information I2.

The function block information I3 of fig. 4 has a row group Ln4 in which the coordinate positions of the 2 function blocks 4 shown in fig. 3B are described, and a row group Ln5 in which the names and center coordinates of the respective function blocks 4 are described. The line group Ln5 corresponds to the terminal information included in the part shape information, and describes position information of the functional block.

In the correspondence information line group Ln6 describing the function block 4 and the logical block in fig. 4, the 1 st line refers to the external file "logic. In addition, in line 2 and thereafter, correspondence information between the logical block and the functional block 4 is described.

The integrated file including the simulation data 1 shown in fig. 4 may be stored in a storage unit, not shown, as needed. The simulation data 1 shown in fig. 4 is read out by an arithmetic device 10 such as a simulator, and the contents of the integrated file are interpreted to execute simulation.

Fig. 5 is a block diagram showing an example of the internal configuration of the arithmetic device 10. The arithmetic device 10 shown in fig. 5 includes an input unit 11, a component information storage unit 12, a logical model storage unit 13, an execution unit 14, an output unit 15, and a verification unit 16. The arithmetic device 10 of fig. 5 executes a simulation of the semiconductor device 2. The arithmetic device 10 associates the component shape information I1, the logic model information I2, and the function block information I3 with each other, and uses the simulation data 1 to perform a simulation of the semiconductor device 2.

The input unit 11 inputs the integrated file shown in fig. 3. The operator may input the integrated file of fig. 3 by a keyboard or the like. Alternatively, the integrated file may be electronically acquired from an electrical appliance having a communication function via the input unit 11.

The component information storage section 12 stores various kinds of component information. The part information is information on the external shape, size, number of terminals, terminal position, and the like of the part as shown in fig. 2A.

The logical model storage unit 13 stores an external file of logical model information I2 described in the simulation data 1. In the case where the logical model connection information and operation are described directly in the logical model information I2 without referring to an external file, the logical model storage unit 13 may not be provided.

The execution unit 14 reads and interprets the part shape information I1, the logical model information I2, and the function block information I3 described in the input integrated file, generates a simulation target circuit based on the part shape information I1, the logical model information I2, and the function block information I3, and executes a simulation based on the generated circuit.

As will be described later, the simulation performed by the execution unit 14 includes a plurality of simulations such as a circuit simulation, an electromagnetic field simulation, and a temperature simulation. In the present description, an example is shown in which the same execution unit 14 performs a plurality of simulations, but different simulations may be performed by a plurality of arithmetic devices 10 (simulators). Alternatively, a plurality of execution units 14 may be provided in one arithmetic unit 10, and each execution unit 14 may perform the simulation.

The output unit 15 outputs the simulation result executed by the execution unit 14. The output form of the simulation result is arbitrary.

The verification unit 16 verifies whether or not the circuit or layout arrangement generated based on the integrated file is appropriate based on the simulation result output from the output unit 15, and if not, changes the circuit or layout arrangement.

Fig. 6 is a flowchart showing an example of the processing operation of the arithmetic device 10. First, the integrated file is input via the input unit 11 (step S1). Next, the execution unit 14 reads out and interprets the integration file, and generates a simulation object circuit based on the part shape information I1, the logical model information I2, and the function block information I3 (step S2). The generated analog target circuit is output from the output unit 15.

Next, the execution unit 14 and the verification unit 16 verify the operation of the circuit to be simulated by using the circuit simulator (step S3). Next, the verification unit 16 determines whether there is a problem with the operation of the circuit to be simulated based on the simulation result of the circuit simulator (step S4). If there is a problem in operation, the process from step S2 onward is repeated. In addition, in some cases, when it is determined that there is a problem in step S4, a new integrated file may be newly input. In this case, the process from step S1 onward is repeated. The verification unit 16 verifies at least one of heat and noise generated inside the simulation target circuit during the simulation execution of the simulation target circuit, for example.

If it is determined in step S4 that there is no problem with the operation, the layout arrangement is performed based on the simulation target circuit whose operation has been verified (step S5). Although the arithmetic device 10 of the present embodiment can be laid out, the processing after step S5 may be performed by another arithmetic device 10 or the like. Alternatively, the arithmetic device 10 of the present embodiment may issue a request for layout arrangement processing to another device that performs layout arrangement, retrieve the layout arrangement result, and perform the processing after step S5.

Next, the arithmetic device 10 performs electromagnetic field simulation based on the layout arrangement result (step S6). Next, it is determined whether there is a problem with the result of the electromagnetic field simulation (step S7). For example, when it is determined that electromagnetic Interference (EMI) noise generated in a part of the layout region of the semiconductor device exceeds a predetermined threshold value by electromagnetic field simulation, it is determined that there is a problem.

If a problem is determined in step S7, it is determined whether or not a layout change is to be performed (step S8). If it is determined that the layout change is to be performed, the processing of step S5 and the subsequent steps is repeated. On the other hand, for example, if it is determined that the problem in step S7 is not solved to the extent of the layout change, the processing in steps S2 and thereafter is repeated.

If it is determined in step S7 that there is no problem, the layout arrangement result of step S5 is output via the output unit 15 (step S9).

In the present embodiment, after specifying the positional information in the semiconductor device 2 of the functional block 4 corresponding to the logical model and performing the simulation, the noise distribution and the temperature distribution in the semiconductor device 2 can be verified with high accuracy.

Fig. 7A is a schematic diagram showing the result of thermal simulation of the present embodiment. Fig. 7B is a schematic diagram showing output signal waveforms of the elements 3 corresponding to the functional blocks 4 in the semiconductor device 2. The more rapid the fluctuation cycle of the output signal of the element 3, the more heat is generated. In the present embodiment, each element 3 in the semiconductor device 2 is associated with an arbitrary functional block 4, and since the positional information in the semiconductor device 2 is specified in advance for each functional block 4, if the waveform of the output signal when each element 3 is operated by circuit simulation can be known, the heat generation state of the corresponding functional block 4 can be predicted, and the temperature distribution in the semiconductor circuit can be predicted with high accuracy.

The same applies to noise, and noise is more likely to occur as the output signal waveform of the element 3 fluctuates more rapidly, so that the noise occurrence state can be estimated for each position of the functional block 4 corresponding to each element 3, and the noise distribution in the semiconductor device 2 can be predicted with high accuracy.

Conventionally, a specific excitation source and power source are set in the semiconductor device 2 and simulation is performed. Even if a specific excitation source or power source is set, temporary heat generation and noise generated during actual operation of the semiconductor device 2 cannot be taken into account, and therefore, the temperature distribution and noise distribution of the semiconductor device 2 cannot be predicted with high accuracy. In addition, conventionally, there is no idea of assigning each element 3 in the semiconductor device 2 to an arbitrary functional block 4 and performing simulation on the basis of position information of the functional block 4 which is designated in advance, and it is not possible to grasp the influence of the operating state of the semiconductor device 2 on heat and noise locally generated in the semiconductor device 2.

In the present embodiment, each element 3 in the semiconductor device 2 corresponds to an arbitrary functional block 4 and the positional information in the semiconductor device 2 of each functional block 4 is specified in advance, and therefore, the waveform of the output signal of each element 3 in the semiconductor device 2 is verified by circuit simulation, and it is possible to predict with high accuracy which place in the semiconductor device 2 generates heat and how much noise occurs. Thus, according to the present embodiment, it is possible to verify the heat and noise generated in the semiconductor device 2 with high accuracy under similar operating conditions when the semiconductor device 2 is actually operated.

The simulation data 1 in fig. 1 may be data in the form of a program executable by the arithmetic device 10. That is, the simulation data 1 in fig. 1 may be described in the form of a program in which the part shape information I1, the logic model information I2, and the function block information I3 are different parameters. More specifically, the program may be written with one or more functions executable by the arithmetic device 10, and the component shape information I1, the logical model information I2, and the functional block information I3 may be given as arguments of the functions.

At least a part of the arithmetic device 10 described in the above embodiment may be constituted by hardware or may be constituted by software. In the case of software, a program for realizing at least a part of the functions of the arithmetic device 10 may be stored in a recording medium such as a flexible disk or a CD-ROM, and may be read and executed by a computer. The recording medium is not limited to a removable recording medium such as a magnetic disk or an optical disk, and may be a fixed recording medium such as a hard disk device or a memory.

The program for realizing at least a part of the functions of the arithmetic device 10 may be distributed via a communication line (including wireless communication) such as the internet. Further, the same program may be encrypted and modulated, and distributed in a compressed state via a wired line such as the internet, a wireless line, or stored in a recording medium.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in other forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope equivalent thereto.