阅读说明：本技术 三维记忆体装置制造的方法 (Method for fabricating three-dimensional memory device ) 是由 杨柏峰 杨世海 徐志安 吕俊颉 林佑明 于 2021-01-26 设计创作，主要内容包括：在一实施例中,一种三维记忆体装置制造的方法包括形成包含隔离材料及半导体材料的交替层的多层堆叠；将多层堆叠图案化以在多层堆叠的第一区域中形成第一通道结构,其中第一通道结构包含半导体材料；在第一通道结构上方沉积记忆体薄膜层；蚀刻贯穿多层堆叠的第二区域的第一沟槽以在第二区域中形成第一虚设位元线及第一虚设源极线,其中第一虚设位元线及第一虚设源极线各自包含半导体材料；及用导电材料置换第一虚设位元线及第一虚设源极线的半导体材料以形成第一位元线及第一源极线。(In one embodiment, a method of three-dimensional memory device fabrication includes forming a multi-layer stack including alternating layers of isolation material and semiconductor material; patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, wherein the first channel structure comprises a semiconductor material; depositing a memory thin film layer over the first channel structure; etching a first trench through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, wherein the first dummy bit line and the first dummy source line each comprise a semiconductor material; and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.)

1. A method of fabricating a three-dimensional memory device, comprising the steps of:

forming a multi-layer stack comprising alternating layers of an isolation material and a semiconductor material;

patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, wherein the first channel structure comprises the semiconductor material;

depositing a memory film layer over the first channel structure;

etching a first trench through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, wherein the first dummy bit line and the first dummy source line each comprise the semiconductor material; and

replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

Technical Field

The present disclosure relates to three-dimensional memory devices and methods of fabricating the same.

Background

Semiconductor devices are used in various electronic applications such as, for example, personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited on a semiconductor substrate, and the layers of materials are patterned using photolithography to form circuit features and elements thereon.

The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size in order to allow more components to be integrated into a given area.

Disclosure of Invention

According to some embodiments of the present disclosure, a method of three-dimensional memory device fabrication includes forming a multi-layer stack including alternating layers of isolation material and semiconductor material; patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, wherein the first channel structure comprises a semiconductor material; depositing a memory thin film layer over the first channel structure; etching a first trench through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, wherein the first dummy bit line and the first dummy source line each comprise a semiconductor material; and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line.

Drawings

Aspects of the present disclosure are best understood from the following description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1A illustrates a 3D NOR memory array in accordance with some embodiments;

FIG. 1B illustrates a top down view of a 3D NOR memory array, according to an embodiment;

FIG. 1C illustrates an equivalent circuit of a 3D NOR memory array, according to an embodiment;

1D, 1E, 1F, and 1G illustrate a 3D NOR memory array in accordance with some embodiments;

fig. 2, 3A, 3B, 4, 5, 6, 7, 8, 9A, 9B, 9C, 9D, 9E, 10, 11, 12A, 12B, 12C, 12D, 12E, 12F, 13A, 13B, 13C, 13D, 13E, 13F, and 13G illustrate perspective, cross-sectional, and top views in an intermediate stage of fabricating a 3D NOR memory array according to an embodiment.

[ notation ] to show

56 photoresist

100 memory array

101 base plate

103 isolating layer

105 source line

107 bit line

109 word line

111 memory film

115 gate isolation insert

117 array spacer

120 memory device stack

121 semiconductor channel region

125 memory device

136 structure

1001 metallic filler

1101 word line gap

1301: first step region

1303 second step area

1305 third step area

1307 step contact area

1309 conductive contact

1313 step contact structure

1403: row

1405 conductive word line structure

1407 conducting source line structure

1409 conductive bit line structure

201 multilayer Stack

203 dummy semiconductor layer

204 transistor

205 first area

207 second region

2001 opening

2020 gate dielectric layer

2040 gate electrode

2060 Source/Drain region

2080 gate spacer

2100 first interlayer dielectric layer (ILD)

2120 second interlayer dielectric layer (ILD)

2140 Source/Drain contact

2160 gate contact

2200 interconnect structure

2220 conductive features

2240 dielectric layer

301 gate trench

303 channel region

305 strip of

403 source/bit line region

700 intermetal dielectric (IMD)

701 surrounding word line structure

801 opening (C)

901 source/bit line gap

905 groove

907 region

908 area

BL1 bit line

BL2 bit line

BL3 bit line

D1 depth

SL1 source line

SL2 source line

SL3 source line

V_thThreshold voltage

W1 width

WL1 word line

WL2 word line

WL3 word line

WL4 word line

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below in order to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms, such as "below …," "below …," "below," "above …," "above," and the like, may be used herein to describe one element or feature's relationship to another element or feature or features as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

According to some embodiments, a 3-dimensional (3-dimensional; 3D) memory array (e.g., a NOR memory array) is described that includes a plurality of stacked memory elements, where each memory element may include a Gate All Around (GAA) transistor. Various embodiments include forming a metal-free multilayer stack including a dummy source line and a dummy bit line. The dummy source line and dummy bit line are then replaced with a conductive material to form a source line and a bit line. The use of dummy source lines and dummy bit lines may provide some advantages. Embodiments of the present disclosure may include the use of a metal-free multilayer stack that simplifies subsequent etch processes for patterning a gate structure and allows for a better etch profile than may be achieved when the multilayer structure includes one or more metal layers. In addition, the source lines and bit lines are formed in the same layer, allowing for a reduced height and aspect ratio of the metal-free multilayer stack for the fabrication process. The resulting memory array may also have a reduced height, thereby increasing device density. In addition, embodiments of the present disclosure allow a source line of a first memory device and a bit line of an adjacent second memory device formed in the same layer to be separated from each other so that interference between the first memory device and the second memory device is minimized when a read and/or write operation is performed in the first memory device and the second memory device.

FIGS. 1A and 13A show perspective views of a memory array 100 according to an embodiment. FIGS. 1D, 1E, 1F, and 1G illustrate perspective, cross-sectional, and top views of a memory array 100 according to an embodiment. Fig. 2, 3A, 3B, 4, 5, 6, 7, 8, 9A, 9B, 9C, 9D, 9E, 10, 11, 12A, 12B, 12C, 12D, 12E, 12F, 13B, 13C, 13D, 13E, 13F, and 13G illustrate perspective, cross-sectional, and top views in intermediate stages of fabricating the memory array 100 according to embodiments. FIG. 1B illustrates a top down view of the memory array 100, according to an embodiment. FIG. 1C illustrates an equivalent circuit of the memory array 100 according to an embodiment.

FIGS. 1A-1G illustrate examples of memory arrays according to some embodiments. FIG. 1A illustrates a portion of the memory array 100 in a three-dimensional view, and FIG. 1B illustrates a top-down view of the memory array 100, according to some embodiments. The memory array 100 includes a plurality of memory elements 125, which may be arranged in a grid of rows and columns. The memory elements 125 may further be vertically stacked to provide a three-dimensional memory array, thereby increasing device density. The memory array 100 may be disposed in a back end of line (BEOL) of a semiconductor die. For example, the memory array may be disposed in an interconnect layer of a semiconductor die, such as over one or more active devices (e.g., transistors) formed on a semiconductor substrate.

In some embodiments, the memory array 100 is a flash memory array, such as a NOR flash memory array, or the like. Each memory element 125 (see fig. 1A-1D) may include a transistor 204 (see fig. 1D, which is a cross-sectional view of cut line a-a of fig. 1A). The 3D memory array 100 includes a plurality of vertically stacked source lines 105 adjacent to a plurality of vertically stacked bit lines 107. Each source line 105 and its corresponding bit line 107 are disposed in the same layer, and an isolation layer 103 is disposed between adjacent source lines of the plurality of vertically stacked source lines 105 and adjacent bit lines of the plurality of vertically stacked bit lines 107 therebetween. The source line 105 and bit line 107 extend in a direction parallel to the major surface of the underlying substrate 101. Source line 105 and bit line 107 may have a stepped configuration such that lower source line 105 is longer than upper source line 105 and extends laterally past the end of the upper source line, and lower bit line 107 is longer than upper bit line 107 and extends laterally past the end of the upper bit line. For example, in fig. 1A, a plurality of stacked layers of source lines 105 are shown, with the highest source line 105 being the shortest and the lowest source line 105 being the longest. In addition, a plurality of stacked layers of bit lines 107 are shown, with the highest bit line 107 being the shortest and the lowest bit line 107 being the longest. The respective lengths of the source line 105 and the bit line 107 may increase in a direction towards the underlying substrate 101. In this manner, a portion of each of the source line 105 and the bit line 107 may be accessed from above the memory array 100, and exposed portions of each of the source line 105 and the bit line 107 may create conductive contacts.

FIG. 1A further illustrates the word line 109 of vertically stacked memory elements 125 separated from the corresponding semiconductor channel region 121 of each transistor 204 by a memory film 111 within the 3D memory array 100. Each word line 109 further serves as the gate of a corresponding transistor 204 (see fig. 1D). In addition, FIG. 1A shows gate isolation inserts 115 separating wordlines 109 of stacked memory elements 125 from one another, and array spacers 117 separating adjacent columns of memory elements 125 from one another. Memory devices 125 in the same vertical column of the memory array 100 may share a common word line 109. FIG. 1E shows a top down view of a memory device 125 including word lines 109 separated by gate isolation plugs 115. FIG. 1E further illustrates an array spacer 117 (see FIG. 1A) separating the memory element 125 from an adjacent memory element in another column of the memory array 100. In FIG. 1E, the memory film 111 is also shown in an enlarged top-down view of the memory element 125.

A first source/drain region of each transistor 204 is electrically coupled to a respective bit line 107, and a second source/drain region of each transistor 204 (see fig. 1D and 1F) is electrically coupled to a respective source line 105, which electrically couples the second source/drain region to ground. In some embodiments, memory elements 125 at the same vertical height in a column of the memory array 100 may share a common source line 105 and a common bit line 107. In FIG. 1D, a cross-sectional view of cut line A-A of FIG. 1A is shown, wherein the memory element stack 120 of the 3D memory array 100 includes a common wordline 109 shared by a plurality of transistors 204, according to some embodiments. In addition, FIG. 1D also shows isolation layer 103 separating source lines 105 from each other and bit lines 107 from each other. In addition, FIG. 1D shows the semiconductor channel region 121 separating the source line 105 from the bit line 107 of each transistor 204 of the memory device 125.

The semiconductor channel region 121 (shown in fig. 1D, 1F, and 1G) may provide a channel region for the transistors 204 of the plurality of memory elements 125. In some embodiments, the semiconductor channel region 121 of the transistor 204 comprises a thin film oxide semiconductor material and the memory film 111 comprises a Ferroelectric (FE) material that provides a gate dielectric for the transistor 204. The region of the semiconductor channel region 121 that intersects the word line 109 may allow current to flow from the bit line 107 to the source line 105 when an appropriate voltage (e.g., higher than a corresponding threshold voltage (Vth) of the corresponding transistor 204) is applied via the corresponding word line 109.

In embodiments where the memory thin film 111 comprises a ferroelectric material, it may be polarized in one of two different directions. The polarization direction can be changed by applying a suitable voltage difference across the memory film 111 and generating a suitable electric field. The polarization may be relatively localized (e.g., typically contained within the boundaries of each memory element 125), and a continuous region of the memory film 111 may extend over multiple memory elements 125 in a row of the memory array 100. Depending on the polarization direction of a particular region of the memory film 111, the threshold voltage of the corresponding transistor 204 varies and a digital value (e.g., 0 or 1) may be stored. For example, when a region of the memory thin film 111 has a first electrical polarization direction, the corresponding transistor 204 may have a relatively low threshold voltage, and when a region of the memory thin film 111 has a second electrical polarization direction, the corresponding transistor 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. The larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory element 125.

To perform a write operation to the memory element 125, a write voltage is applied across a portion of the memory film 111 corresponding to the memory element 125. The write voltage may be applied, for example, by applying appropriate voltages to the corresponding word line 109 and the corresponding bit line 107/source line 105). By applying a write voltage across a portion of the memory film 111, the polarization direction of the region of the memory film 111 can be changed. Thus, the corresponding threshold voltage of the corresponding transistor 204 may also be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value may be stored in the memory element 125. Because the word line 109 intersects the source line 105 and the bit line 107, individual memory elements 125 can be selected for a write operation.

To perform a read operation for the memory element 125, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding word line 109. Depending on the polarization direction of the corresponding region of the memory film 111, the transistor 204 of the memory element 125 may or may not be turned on. Thus, bit line 107 may or may not be discharged via source line 105, and the digital value stored in memory element 125 may be determined. Because the word line 109 intersects the source line 105 and the bit line 107, individual memory elements 125 can be selected for read operations.

FIG. 1B illustrates a top down view of the memory array 100 according to some embodiments. In fig. 1B, for ease of illustration, the uppermost layer of the isolation layer 103 is removed in order to allow observation of the underlying structures. The memory array 100 includes a plurality of columns 1403. Column 1403 includes a plurality of vertically stacked source lines 105 adjacent to a plurality of vertically stacked bit lines 107. Each source line 105 and its corresponding bit line 107 serve as a source line and a bit line, respectively, for a plurality of memory elements 125 in a column 1403. Each column 1403 includes a word line 109. Each column 1403 includes one set of stepped contact regions 1307 that includes conductive contacts 1309 that extend to each source line 105 and another set of stepped contact regions 1307 that include conductive contacts 1309 that extend to each bit line 107. Conductive contacts 1309 and 1307 connect source line 105/bit line 107 to overlying source line 105/bit line 107 for additional connections to active devices formed on the underlying substrate 101. Each rung contact region 1307 is associated with a stack of source lines 105 (e.g., SL1, SL2, SL3, see fig. 1C) or bit lines 107 (e.g., BL1, BL2, BL3, see fig. 1C).

FIG. 1B further illustrates memory elements 125 in a row 1403 of the 3D-memory array 100. According to some embodiments, the word lines 109 of the memory elements 125 in adjacent columns 1403 of the memory array 100 are aligned with each other. In other embodiments, the word lines 109 of memory elements 125 in adjacent columns 1403 of the memory array 100 can be offset from each other in a staggered arrangement from one column 1403 to the next. According to some embodiments, conductive word line structures 1405 may be formed to the conductive contacts 1309 in order to connect the word lines 109 to active devices (e.g., control circuitry) on the underlying substrate 101. In the illustrated embodiment, the word lines 109 of adjacent columns 1403 are electrically connected to each other by one of the conductive word line structures 1405 (e.g., WL1, WL2, WL3, WL 4). In embodiments with staggered word lines 109, the conductive word line structures 1405 may connect word lines 109 aligned with other word lines 109 in a staggered arrangement, one to another, within the memory array 100.

FIG. 1C is a schematic diagram of an equivalent circuit of the 3D-NOR memory array 100 shown in FIGS. 1A-1B. Specifically, FIG. 1C shows a plurality of columns 1403, each including a plurality of memory elements 125 and conductive word line structures 1405 associated with a set of word lines 109, referred to as, for example, WL1, WL2, WL3, WL4, of the 3D-memory array 100. FIG. 1C further illustrates conductive source line structures 1407 associated with a stack of source lines 105 (e.g., SL1, SL2, SL3) of the memory array 100 and conductive bit line structures 1409 associated with a stack of bit lines 107 (e.g., BL1, BL2, BL3) of the memory array 100. FIG. 1C further illustrates the memory element 125 of the equivalent circuit associated with the dashed lines of FIGS. 1A and 1B.

1F-1G illustrate perspective cross-sectional views of a portion of memory array 100, according to some embodiments. In FIG. 1F, the isolation layer 103 is transparent to show the source line 105 and the bit line 107 and the memory film 111. Additionally, the word line 109 is also shown in FIG. 1F. In fig. 1G, the isolation layer 103, the source line 105, the bit line 107, the memory film 111 and the word line 109 are shown as transparent in order to illustrate the semiconductor channel region 121 forming the channel region of the transistor 204.

Referring now to FIGS. 2-13G, these figures illustrate intermediate stages of forming the 3D memory array 100, according to some embodiments. In fig. 2, a substrate 101 is provided. The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 101 may be a wafer, such as a silicon wafer. Generally, the SOI substrate layer is a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material substrate 101 may comprise silicon, germanium, compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), alloy semiconductors (including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide), or combinations thereof.

Fig. 2 further illustrates circuitry that may be formed on substrate 101 to form structure 136. The circuit includes active devices (e.g., transistors) at the top surface of the substrate 101. The transistor may comprise a gate dielectric layer 2020 on the top surface of the substrate 101 and a gate electrode 2040 on the gate dielectric layer 2020. Source/drain regions 2060 are disposed on the substrate 101 on opposite sides of the gate dielectric layer 2020 and the gate electrode 2040. Gate spacers 2080 are formed along sidewalls of the gate dielectric layer 2020 and separate the source/drain regions 2060 from the gate electrode 2040 by a suitable lateral distance. In some embodiments, the transistor may be a planar Field Effect Transistor (FET), a fin field effect transistor (FinFET), a nano field effect transistor (nanoFET), or the like.

A first interlayer dielectric layer (ILD)2100 surrounds and separates the source/drain regions 2060, the gate dielectric layer 2020, and the gate electrode 2040 and a second interlayer dielectric layer (ILD)2120 is over the first ILD 2100. A source/drain contact 2140 extends through the second ILD 2120 and the first ILD2100 and is electrically coupled to the source/drain region 2060 and a gate contact 2160 extends through the second ILD 2120 and is electrically coupled to the gate electrode 2040. An interconnect structure 2200 comprising one or more stacked dielectric layers 2240 and conductive features 2220 formed in the one or more dielectric layers 2240 is over second ILD 2120, source/drain contacts 2140, and gate contact 2160. Although fig. 2 illustrates two stacked dielectric layers 2240, it is understood that interconnect structure 2200 may include any number of dielectric layers 2240 having conductive features 2220 disposed therein. Interconnect structure 2200 may be electrically connected to gate contact 2160 and source/drain contacts 2140 to form functional circuitry. In some embodiments, the functional circuitry formed by the interconnect structure 2200 may include logic circuitry, memory circuitry, sense amplifiers, controllers, input/output circuitry, image sensor circuitry, the like, or combinations thereof. Although fig. 2 discusses transistors formed over the substrate 101, other active devices (e.g., diodes or the like) and/or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuitry.

Fig. 3A-3B illustrate the formation of a multi-layer stack 201 over the structure of fig. 2, according to some embodiments. For simplicity and clarity, the substrate 101, transistors, ILD, and interconnect structure 2200 may be omitted from subsequent figures. Although the multi-layer stack 201 is shown as contacting the dielectric layer 2240 of the interconnect structure 2200, any number of intermediate layers may be disposed between the substrate 101 and the multi-layer stack 201. For example, one or more interconnect layers including conductive features in an insulating layer (e.g., a low-k dielectric layer) may be disposed between the substrate 101 and the multi-layer stack 201. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines to active devices on the substrate 101 and/or memory array 100 (see fig. 1A).

The multilayer stack 201 includes alternating layers of isolation layers 103 and dummy semiconductor layers 203. The isolation layer 103 may be a dielectric material (e.g., an oxide such as silicon oxide, SiN, SiON, or the like). The dummy semiconductor layer 203 may be formed of a thin film oxide semiconductor material such as zinc oxide (ZnO), Indium Gallium Zinc Oxide (IGZO), indium tungsten oxide (IWO), Indium Tin Oxide (ITO), Indium Gallium Zinc Tin Oxide (IGZTO), or the like. The isolation layer 103 and the dummy semiconductor layer 203 may be formed using, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), or the like. However, any suitable material and deposition process may be used to form the dummy semiconductor layer 203.

The multi-layer stack 201 may be formed by initially depositing a first one of the isolation layers 103 over the structure of fig. 2. According to an embodiment, the isolation layer 103 may be formed by depositing an overall layer (e.g., oxide) using a CVD process or an ALD process. However, any suitable material and/or suitable deposition process may be used. Once deposited, an optional annealing process (e.g., rapid thermal annealing, oxidation densification, or the like) and/or an optional planarization process (e.g., chemical mechanical planarization) may be performed to harden and/or planarize the first of the isolation layers 103.

Once the first of the isolation layers 103 is formed, a first of the dummy semiconductor layers 203 may be formed over the first of the isolation layers 103. According to an embodiment, the dummy semiconductor layer 203 may be formed by depositing a thin film oxide semiconductor material (e.g., zinc oxide (ZnO), or the like) in an ALD, CVD, PVD process, or the like.

Once the first of the dummy semiconductor layers 203 is formed, further isolation layers 103 and further dummy semiconductor layers 203 may be formed one above the other in the multilayer stack 201 in an alternating manner until the desired highest layer of the dummy semiconductor layers 203 and the highest layer of the isolation layers 103 are formed. Any suitable number of isolation layers 103 and any suitable number of dummy semiconductor layers 203 may be formed in the multilayer stack 201.

Fig. 3A further illustrates a first region 205 of the multi-layer stack 201. According to some embodiments, the first region 205 may be designated for forming the 3D memory array 100. Additionally, a second region 207 of the multi-layer stack 201 is adjacent to the first region 205 and may be designated for forming connectors that connect the memory array 100 to underlying active devices and/or signal, power, and ground lines in a semiconductor die.

Fig. 4 illustrates the formation of a gate trench 301 within a channel region 303 of a multi-layer stack 201, according to some embodiments. Channel region 303 may also be referred to herein as a wordline region. The gate trench 301 may be formed by initially forming photoresist (not shown) over the multi-layer stack 201. The photoresist may be formed using spin-on techniques and may be patterned using acceptable lithography techniques. The photoresist may be patterned so as to expose the surface of the highest layer of the multi-layer stack 201 in the desired location of the gate trench 301. The gate trench 301 may be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. In general, double patterning or multiple patterning processes combine lithography with self-alignment processes, allowing for the generation of patterns, for example, with pitches smaller than those otherwise obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the multi-layer stack 301 and patterned using a lithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process, and the sacrificial layer is removable.

Once formed, the spacers may be used as a mask in order to etch the material of the isolation layer 103 and the material of the dummy semiconductor layer 203 exposed through the mask. The etch may be one or more of any acceptable etch process, such as wet or dry etch, Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or combinations thereof. The etching may be anisotropic. In some embodiments, the mask may be used for multiple separate etching processes in order to remove exposed material of the isolation layer 103 and to remove exposed material of the dummy semiconductor layer 203. However, the mask may also be used in a single etching process to simultaneously etch through the isolation layer 103 and the material of the dummy semiconductor layer 203.

According to some embodiments, a first etch chemistry that is selective to the isolation layer 103 and relatively non-selective to the dummy semiconductor layer 203 may be used to form a gate trench 301 that passes through the isolation layer 103 and terminates on the dummy semiconductor layer 203. A second etch chemistry that is selective to the dummy semiconductor layer 203 and relatively non-selective to the isolation layer 103 may be used to form a gate trench 301 that passes through the dummy semiconductor layer 203 and terminates on the isolation layer 103. For example, a chlorine or fluorine based gas such as chlorine (Cl 2) or Hydrogen Fluoride (HF), or the like, may be used to selectively etch the dummy semiconductor layer 203 without substantially removing the material of the isolation layer 103. The isolation layer 103 may be selectively etched using a wet etch chemistry including phosphorous, such as H3PO4, or the like, without substantially removing material of the dummy semiconductor layer 203. In other embodiments, a single etch process may be used to remove both the isolation layer 103 and the material of the dummy semiconductor layer 203, such as using an etch process that is selective for the multilayer stack 201.

According to some embodiments, a timed etch process may be used to terminate the etching of the gate trench 301 after the trench reaches a desired depth. For example, the timed etch process may be timed to terminate at the surface of structure 136, but the timed etch process may be timed to etch into structure 136 to a desired depth. An optional contact etch stop layer (not shown) may be provided at the interface between the structure 136 and the multilayer stack 201, according to some embodiments. The optional contact etch stop layer may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying layers of the multilayer stack 201. In these embodiments, prior to forming multilayer stack 201, an optional contact etch stop layer is formed over structure 136 via a suitable deposition process (e.g., atomic layer deposition, chemical vapor deposition, physical vapor deposition, or the like), and multilayer stack 201 is formed over the optional contact etch stop layer. Furthermore, an additional etch process may be used to remove material that optionally contacts the etch stop layer such that the structure 136 is exposed at the bottom of the gate trench 301.

Once patterned, the remaining portions of the multi-layer stack 201 between the gate trenches 301 form a plurality of strips 305. Thus, the gate trenches 301 are separated by stripes 305. Although the embodiment shown in FIG. 4 shows each of the stripes 305 having the same width, the width of the stripes 305 of the memory array 100 located in one area of the multi-layer stack 201 may be larger or thinner than the stripes 305 of the memory array 100 located in another area of the multi-layer stack 201. Further, although according to some embodiments, each of the gate trenches 301 is shown to have a uniform width throughout. In other embodiments, the gate trenches 301 and thus the strips 305 may have tapered sidewalls such that the width of each of the strips 305 continuously increases in a direction toward the substrate 101. In these embodiments, each of the isolation layer 103 and the dummy semiconductor layer 203 may have different widths in a direction perpendicular to the sidewalls of the strips 305.

Fig. 5 illustrates a wire releasing process of forming the semiconductor channel region 121 from the dummy semiconductor layer 203. Once the gate trenches 301 are formed, according to some embodiments, the spacers and/or photoresist used to form the gate trenches 301 of fig. 4 may be removed and a masking layer (not shown) for the wire release process may be formed and patterned over the multi-layer stack 201 so as to expose the channel regions 303. In other embodiments, the spacer and/or photoresist layer used to form the gate trench 301 may be retained and a mask layer for the wire release process formed over the spacer and photoresist layer. In these embodiments, a masking layer may be formed over the photoresist and/or spacers and then patterned so as to expose portions of the photoresist and/or spacers that cover the gate trenches 301 and/or stripes 305 in the channel regions.

According to some embodiments, the mask layer may be a conductive or non-conductive material and may be selected from the group consisting of silicon nitride, silicon oxynitride, amorphous silicon, poly-crystalline silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The mask layer may be deposited by Physical Vapor Deposition (PVD), CVD, ALD, sputter deposition, or other techniques for depositing the selected material. Once the material of the mask layer has been deposited, the material may be patterned using, for example, a photolithographic mask and etching process. Once the mask layer is patterned, the exposed portions of the photoresist and/or spacers are removed using one or more suitable removal processes (e.g., ashing, selective etching, combinatorial, or the like).

Once the mask layer is formed and patterned, the sidewalls of the gate trench 301 and thus the sidewalls of the strips 305 are exposed. Thus, in a wire release process step, the material of the isolation layer 103 of the strip 305 may be removed between the substrate 101 and the dummy semiconductor layer 203. Thus, the remaining material of the strips 305 (e.g., the dummy semiconductor layer 203) forms semiconductor channel regions 121 between the source/bit line regions 403 of the multilayer stack 201. The semiconductor channel region 121 may be referred to herein as a wire, nanowire, sheet, or nanosheet. In one embodiment, the isolation layer 103 of the stripes 305 may be removed using a wet etch process that selectively removes material of the isolation layer 103 without significantly removing material of the semiconductor channel region 121 within the channel region 303 and without significantly removing material of the isolation layer 103 and material of the dummy semiconductor layer 203 of the source/bit line regions 403 of the multi-layer stack 201. However, any other suitable removal process may be utilized.

For example, in one embodiment, a phosphorus-containing etch chemistry, such as H3PO4, may be used to selectively remove material of the isolation layer 103, such as silicon oxide, without substantially removing material of the semiconductor channel region, such as zinc oxide (ZnO), and/or material of the substrate 101. However, in other embodiments any other suitable etchant may be used to selectively remove the material of the isolation layer 103 (e.g., silicon oxide) without substantially removing the material of the semiconductor channel region 121 (e.g., zinc oxide) and/or the material of the substrate 101.

By removing the material of the isolation layer 103, the sides of the semiconductor channel region 121 are exposed and separated from each other in the channel region 303. The semiconductor channel region 121 forms a channel structure between opposite regions of the source/bit line region 403. In some embodiments, the tuning selectivity of the etching process used to form the semiconductor channel region 121 may be adjusted such that the semiconductor channel region 121 is formed to have a smooth surface or to include multiple end surface surfaces. Accordingly, the semiconductor channel region 121 may be formed to have different outline shapes (e.g., a circle, a square, a rectangle, a hexagon, an octagon, or the like, as shown later in fig. 12B to 12D). In the illustrated embodiment, the semiconductor channel region 121 is formed to have a square profile with a channel width about the same as the original thickness of the dummy semiconductor layer 203, although an etching process may also be used to reduce the thickness.

Once the semiconductor channel region 121 has been formed, any remaining portions of the masking layer, remaining spacers, and/or remaining photoresist may be removed using one or more suitable removal processes (e.g., wet etching, dry etching, or the like) utilizing one or more etchants selective to the material of the masking layer, remaining spacers, and/or remaining photoresist. However, any suitable removal process may be utilized.

Fig. 6 shows the formation of the memory film 111 on the top surface of the multi-layer stack 201, the sidewalls of the source/bit line regions 403 in the channel region 303 of the multi-layer stack 201, and the exposed surface of the semiconductor channel region 121 between the sidewall source/bit line regions 403 in the channel region 303 of the multi-layer stack 201. The memory film 111 is formed as a conformal film. According to some embodiments, the memory film 111 may be formed using one or more layers of acceptable dielectric materials suitable for storing digital values, such as a multilayer dielectric (e.g., oxide-nitride-oxide (ONO), nitride-oxide-nitride (NON), or the like); other dielectrics (e.g., silicon oxynitride; SiON), silicon nitride (SiN), or the like); ferroelectric (FE) materials such as hafnium zirconium oxide (HfNium zirconium oxide; HfZrO); zirconium oxide (zirconia oxide; ZrO); undoped hafnium oxide (HfO); doped hafnium oxide (e.g., HfLaO using lanthanum (lanthanum; La) as a dopant, HfSiO using silicon (silicon; Si) as a dopant, HfAlO using aluminum (Al) as a dopant, or the like); combining; or the like. The material of the memory thin film 111 may be formed by an acceptable deposition process such as ALD, CVD, PVD, or the like. Once deposited, the material of the memory film 111 can be planarized relative to the uppermost layer of the isolation layer 103 using a process such as chemical mechanical planarization, etch back process, combinations thereof, or the like.

FIG. 7 illustrates the formation of a surrounding word line structure 701 formed over the memory film 111 in the channel region 303 of the multi-layer stack 201 and subsequent chemical mechanical planarization. The surrounding wordline structure 701 may include one or more layers such as adhesion layers, barrier layers, diffusion layers, and fill layers, and the like. . In some embodiments, the surrounding wordline structure 701 includes an adhesion layer and a conductive layer. The adhesion layer may be formed of a metal nitride such as titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, or the like. The conductive layer may be formed of a metal such as tungsten, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. The material of the adhesive layer is a material having good adhesion to the material of the memory thin film 111, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer. In embodiments where the memory film 111 is formed of an oxide, such as an oxide-nitride-oxide (ONO) film, the adhesion layer may be titanium nitride and the conductive layer may be tungsten. The adhesion layer and the conductive layer may each be formed by an acceptable deposition process such as ALD, CVD, or the like. The material surrounding wordline structure 701 may fill and overfill the remaining opening in the channel region 303 and may be formed over the top surface of the multi-layer stack 201 outside the channel region 303. The conductive layer fills the remaining region of the gate trench 301. Once deposited, the material surrounding the word line structures 701 and the memory film 111 may be planarized relative to the uppermost layer of the isolation layer 103 using a process such as chemical mechanical planarization, an etch back process, a combination thereof, or the like.

Fig. 8 illustrates the formation of an opening 801 in the multi-layer stack 201. The openings 801 may be referred to herein as vertical slots, vertical trenches, or vertical arrays of openings. In the illustrated embodiment, opening 801 extends through multilayer stack 201 and exposes structure 136. The array slits 301 may be formed by initially forming photoresist (not shown) over the multi-layer stack 201. The photoresist may be formed using spin-on techniques and may be patterned using acceptable lithography techniques. The photoresist may be patterned so as to expose the surface of the highest layer of the multi-layer stack 201 in the desired location of the opening 801. The opening 801 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine lithography with self-alignment processes, allowing for the generation of patterns, for example, with pitches smaller than those otherwise obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed on the multi-layer stack 201 and patterned using a lithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process, and the sacrificial layer is removable.

Once formed, the spacers may be used as a mask in order to etch the material of the isolation layer 103 and the material of the dummy semiconductor layer 203 exposed through the mask. The etch may be one or more of any acceptable etch process, such as wet or dry etch, Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or combinations thereof. The etching may be anisotropic. In some embodiments, the mask may be used for multiple separate etching processes in order to remove exposed material of the isolation layer 103 and to remove exposed material of the dummy semiconductor layer 203. However, the mask may also be used in a single etching process to simultaneously etch through the isolation layer 103 and the material of the dummy semiconductor layer 203. In some embodiments, the opening 801 may be formed using any lithography and anisotropic etch techniques suitable for forming the gate trench 301, as set forth above in fig. 4. However, other suitable lithography and etching techniques may be used to form the opening 801. According to some embodiments, the opening 801 may be formed to have a first width W1.

The opening 801 is formed to divide the multi-layer stack 201 and to separate a region of the multi-layer stack 201 from an adjacent region of the multi-layer stack 201. In some embodiments, adjacent regions of the multi-layer stack 201 may be subsequently used to form adjacent memory elements, although other structures may be formed in one or more adjacent regions.

FIG. 9A illustrates the formation of a source/bit line gap 901 in the multi-layer stack 201. Once the opening 801 is formed, the dummy semiconductor layer 203 is exposed at the sidewall of the opening 801. Thus, source/bit line gap 901 may be formed by any acceptable etch process, such as a process that is selective to the material of dummy semiconductor layer 203 (e.g., selectively etches the material of dummy semiconductor layer 203 at a faster rate than the material of isolation layer 103). In some embodiments, a chlorine or fluorine based gas such as chlorine (chlorine; Cl2) or Hydrogen Fluoride (HF), or the like, may be used to selectively etch the dummy semiconductor layer 203 without substantially removing the material of the isolation layer 103 to form the source/bit line gap 901. The etch process may be a timed etch process or may alternatively be terminated using an endpoint detection process.

Fig. 9B further illustrates a region 907 of one of the openings 801. The region 907 is indicated by a dashed line and the region 907 is also shown in an enlarged view in fig. 9C. As shown, the sidewalls of the semiconductor channel region 121 and the memory film 111 are exposed through the source/bit line gap 901 between the spacers 103. In fig. 9B to 9C, the dummy semiconductor layer 203 is etched in a timing process not substantially removing the material of the isolation layer 103 to form the source/bit line gap 901 so that the sidewall of the semiconductor channel region 121 and the sidewall of the memory thin film 111 are flush with each other.

FIG. 9D further illustrates another embodiment including a region 908 in one opening 801 after forming a source/bit line gap 901 (previously shown in FIG. 9A) in the multi-layer stack 201. Region 908 is indicated by dashed lines and region 908 is also shown in an enlarged view in fig. 9E. As shown, the sidewalls of the semiconductor channel region 121 and the memory film 111 are exposed through the source/bit line gap 901 between the spacers 103. The recess 905 in the semiconductor channel region 121 opposite the sidewall of the memory film 111 is also shown in the enlarged view of region 908 of FIG. 9E. According to some embodiments, during the formation of the source/bit line gap 901, the semiconductor channel region 121 may be recessed relative to sidewalls of the memory thin film 111 during a timed etch process that removes the dummy semiconductor layer 203 and further etches the semiconductor channel region 121 in a lateral direction without substantially removing material of the isolation layer 103.

Fig. 10 illustrates the formation of a metal fill material 1001 in the opening 801 (see, e.g., fig. 8) and the source/bit line gap 901 (see, e.g., fig. 9A-9E). The metal fill material 1001 may include one or more layers such as adhesion layers, barrier layers, diffusion layers, and fill layers, and the like, and may be formed using any materials and processes suitable for forming the surrounding word line structures 701. For example, the material used to form the metallic fill material 1001 may be the same as the material used to form the surrounding word line structure 701, but it may be different. In some embodiments, the metallic fill material 1001 includes an adhesion layer and a conductive layer. The adhesion layer may be formed of a metal nitride (e.g., titanium nitride, tantalum nitride, zirconium nitride, hafnium nitride, or the like) suitable for forming the surrounding word line structures 701. The conductive layer may be formed of a metal (e.g., tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or the like) suitable for forming the surrounding word line structures 701. The material of the adhesive layer is a material having good adhesion to the material of the isolation layer 103 and/or the memory film 111, and the material of the conductive layer is a material having good adhesion to the material of the adhesive layer.

In some embodiments, the adhesion layer may be formed of titanium nitride (TiN) and the conductive layer may be formed of tungsten (W). The adhesion layer and the conductive layer may each be formed by an acceptable deposition process such as atomic layer deposition, chemical vapor deposition, or the like. The material of the metal fill material 1001 may be formed so as to fill and overfill the opening 801 and the source/bit line gap 901 and may be formed outside the opening 801, over the top surface of the uppermost layer of the isolation layer 103. Once deposited, the material metal fill material 1001 may be planarized with respect to the uppermost layer of the isolation layer 103, the memory film 111, and the surrounding word line structures 701 using a process such as chemical mechanical planarization.

Fig. 11 illustrates forming a wordline gap 1101 and removing the metal fill material 1001 to form an opening 2001, according to some embodiments. The wordline gaps 1101 may be formed using any lithography and etching technique suitable for etching the material surrounding the wordline structures 701. The etching may be anisotropic. In some embodiments, wordline gaps 1101 and openings 2001 may be formed by a series of suitable etches (e.g., dry etches and/or wet etches). According to some embodiments, the dry etching is performed using a fluorine-based gas (e.g., C4F6) mixed with hydrogen (hydrogen; H2) or oxygen (oxygen; O2) gas for removing the conductive layer surrounding the word line structures 701 and the wet etching is performed using a nitric acid (nitric acid; HNO3) and hydrofluoric acid (HF) solution for removing the adhesion layer surrounding the word line structures 701. However, other suitable removal processes may be used to remove material from the wordline gap 1101 and the opening 2001. According to some embodiments, forming wordline gaps 1101 divides surrounding wordline structure 701 into wordlines 109.

FIG. 11 further illustrates that an opening 2001 separates a bit line 107 of a memory element 125 from a source line 105 of an adjacent memory element in another row of the memory array 100. In addition, opening 2001 separates source line 105 of memory element 125 from bit line 107 of an adjacent memory element in another row of memory array 100. The opening 2001 may be filled with a dielectric material (described subsequently in fig. 12A) so as to allow separation of the source line 105 of the memory element 125 from the source line 105 of an adjacent memory element formed in the same layer of the bit line 107, allowing for minimal interference between the memory element 125 and the adjacent memory element when performing read and/or write operations in the memory element 125 and the adjacent memory element. Additionally, the opening 2001 may be filled with a dielectric material (described subsequently in FIG. 12A) so as to allow separation of the source line 105 of an adjacent memory element formed in the same layer of the bit line 107 and the source line 105 of the memory element 125, thereby allowing for minimal interference between the memory element 125 and the adjacent memory element when performing read and/or write operations in the memory element 125 and the adjacent memory element.

Figure 12A illustrates the formation of spacers 117, gate isolation inserts 115, source lines 105, bit lines 107, and word lines 109, according to some embodiments. Specifically, FIG. 12A shows a portion of the 3D memory array 100 in perspective view, with gate isolation inserts 115 and array spacers 117 formed in the wordline gaps 1101 and openings 2001 of FIG. 11. The array spacers 117 and gate isolation inserts 115 are formed of a dielectric material. Acceptable dielectric materials include, but are not limited to, oxides such as silicon oxide; nitrides such as silicon nitride; carbides such as silicon carbide; similarly, the following are mentioned; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, or the like. In some embodiments, the array spacers 117 and the gate isolation inserts 115 are formed using the same material and the same deposition process. The materials of the gate isolation inserts 115 and the array spacers 117 may be formed by an acceptable deposition process such as ALD, CVD, flowable CVD (fcvd), or the like, in order to fill and/or overfill the wordline gaps 1101 and openings 2001, respectively.

In other embodiments, the material used to form the gate isolation inserts 115 may be different from the material used to form the array spacers 117. In these embodiments, separate removal processes may be used to form the opening 2001 and to form the wordline gap 1101. Furthermore, separate deposition processes may be used to form the gate isolation inserts 115 and the array spacers 117. Furthermore, the array spacers 117 may be formed before the gate isolation inserts 115, but the array spacers 117 may be formed after the gate isolation inserts 115. All such removal processes, deposition processes, and sequencing of such processes are within the scope of the embodiments.

Fig. 12B-12D show cross-sectional views of cut lines D-D of fig. 12A after formation of array spacers 117, gate isolation inserts 115, source lines 105, bit lines 107, and word lines 109, according to some various embodiments. The tuning selectivity of the etching process (previously described in fig. 5) used to form the semiconductor channel region 121 may be adjusted such that the semiconductor channel region 121 is formed to have a smooth surface or to include multiple end surface surfaces. Accordingly, the semiconductor channel region 121 may be formed to have different outline shapes (e.g., a circle, a square, a rectangle, a hexagon, an octagon, or the like, as shown in fig. 12B to 12D). Since the memory thin film 111 is formed as a conformal thin film on the exposed surface of the semiconductor channel region 121 (previously described in fig. 6), the memory thin film is formed to have a similar outline shape (e.g., a circle, a square, a rectangle, a hexagon, an octagon, or the like) as the semiconductor channel region 121.

In fig. 12E, a cross-sectional view is shown along lines similar to B-B of fig. 9C after formation of the array spacers 117, gate isolation inserts 115, source lines 105, bit lines 107, and word lines 109 (as described above in fig. 12A), according to some embodiments. FIG. 12E shows the semiconductor channel region 121 between the source line 105 and the bit line 107. FIG. 12E also shows the memory film 111 surrounding and encircling the semiconductor channel region 121 and the word lines 109 over and encircling the memory film 111. The gate isolation plug 115 separates the word line 109 of the memory device 125 from the word line 109 of an adjacent memory device. Due to the timed etch process (as described above in fig. 9A to 9C), in fig. 12E, the sidewalls of the semiconductor channel region 121 and the sidewalls of the memory film 111 are shown to be flush with each other.

In fig. 12F, a cross-sectional view is shown along lines similar to C-C of fig. 9E after formation of the array spacers 117, gate isolation inserts 115, source lines 105, bit lines 107, and word lines 109 (as described above in fig. 12A), according to some embodiments. FIG. 12F shows the semiconductor channel region 121 between the source line 105 and the bit line 107. FIG. 12F also shows the memory film 111 surrounding and encircling the semiconductor channel region 121 and the word lines 109 over and encircling the memory film 111. The gate isolation plug 115 separates the word line 109 of the memory device 125 from the word line 109 of an adjacent memory device. Fig. 12F further illustrates the semiconductor channel region 121 recessed relative to the sidewalls of the memory film 111 as a result of a timed etch process (previously described in fig. 9A, 9D, and 9E) that etches both ends of the semiconductor channel region 121 to the first depth D1 in the lateral direction. According to some embodiments, the first depth D1 may be in a range between about 5nm to about 30 nm. However, any suitable depth may be used. Source line 105 and bit line 107 extend into and fill recesses 905 to contact the ends of semiconductor channel region 121. Furthermore, the tuning selectivity of the etching process may be adjusted to shape the distal end of the semiconductor channel region 121 into a desired shape (e.g., concave, convex, flat, circular, including multiple end faces, or the like). In the illustrated embodiment, the distal end of the semiconductor channel region 121 is concave.

It is observed that forming a 3-dimensional (3-dimensional) memory array 100 comprising a plurality of stacked memory elements 125, wherein each memory element may comprise a gate-around (GAA) transistor, and comprising forming a metal-free multilayer stack 201 comprising a dummy semiconductor layer 203 as a dummy source line and a dummy bit line in the same layer, and subsequently replacing the dummy semiconductor layer 203 by a conductive material to form source lines 105 and bit lines 107 of memory elements 125 separated from adjacent memory elements 125, may have some advantages. For example, forming the multi-layer stack 201 with one or more metal layers instead of the dummy semiconductor layer 203 may complicate subsequent etching processes for patterning the gate structure and may result in a worse etch profile than would be possible if the multi-layer stack 201 did not include one or more metal layers. In addition, forming source lines 105 and bit lines 107 corresponding to each memory element 125 in different layers results in an increase in the height and aspect ratio of the multi-layer stack 201, resulting in a decrease in device density. In addition, insufficient isolation between the source line 105 and the bit line 107 of the memory element 125 and the adjacent memory elements may result in minimal interference between the memory element 125 and the adjacent memory elements when read and/or write operations are performed in the memory element 125 and the adjacent memory elements.

FIG. 13A illustrates a portion of a 3D-NOR memory array 100 in accordance with some embodiments. The memory array 100 includes a stepped contact structure 1313 formed within the second region 207 of the multi-layer stack 201 according to some embodiments. The step contact structure 1313 may be formed by initially disposing photoresist 56 (shown in fig. 13B) over the multi-layer stack 201 after forming the array spacers 117, gate isolation inserts 115, source lines 105, bit lines 107, and word lines 109 (as described above in fig. 12A). 13B-13F illustrate cross-sectional views of the second region 207 of the memory array 100 along line E-E of FIG. 13A. The photoresist 56 may be formed using spin-on techniques and may be patterned using acceptable lithography techniques. Patterning the photoresist 56 may expose a portion of the multi-layer stack 201 in the first step region 1301 (shown in fig. 13B) while masking the remaining portion of the multi-layer stack 201.

Once the first step region 1301 is exposed, the exposed portion of the multi-layer stack 201 in the first step region 1301 is etched using the photoresist 56 as a mask during the step etching process. The step etch process may be any acceptable etch process, such as wet or dry etch, Reactive Ion Etch (RIE), Neutral Beam Etch (NBE), the like, or combinations thereof. The etching may be anisotropic. Etching may remove the highest level of the isolation layer 103, the highest level of the source line 105, and a portion of the highest level of the bit line 107 in the first step region 1301 (shown in fig. 13C) so that the isolation layer 103 under the highest level of the source line 105 and the highest level of the bit line 107 is exposed in the first step region 1301. Since the uppermost layer of the isolation layer 103 and the uppermost layers of the source line 105 and the bit line 107 have different material compositions, the etchant for removing the exposed portions of these layers may be different. In some embodiments, the source lines 105 and bit lines 107 act as an etch stop while the overlying layers of the isolation layer 103 are etched. Once the uppermost layer of the isolation layer 103 has been removed, the uppermost layer of the source line 105 and the uppermost layer of the bit line 107 are exposed in the first step region 1301. Thus, the underlying isolation layer 103 acts as an etch stop when etching the overlying source line 105 and bit line 107. Thus, without removing the remaining layers of the multi-layer stack 201, the highest layer of the isolation layer 103 and portions of the highest layers of the source line 105 and the bit line 107 may be selectively removed, and the pattern of the photoresist 56 may extend into the first step region 1301 of the multi-layer stack 201 to a desired depth. Alternatively, a timed etch process may be used to terminate the etch after reaching a desired depth in the first step region 1301 of the multilayer stack 201. Accordingly, the next layer of the isolation layer 103 under the highest layer of the source line 105 and the highest layer of the bit line 107 is exposed in the first step region 1301.

Once the next layer of isolation layer 103 is exposed, photoresist 56 (shown in fig. 13D) may be trimmed to expose another portion of multilayer stack 201 in second step region 1303 while masking the remaining portion of multilayer stack 201 outside of first step region 1301 and second step region 1303. Once the second stepped region 1303 is exposed, the exposed portions of the multi-layer stack 201 in the first and second stepped regions 1301, 1303 are etched by repeating the stepped etch process using the trim photoresist 56 as a mask (shown in fig. 13D). The etching may remove the highest layer of the isolation layer 103 and portions of the highest layer of the source line 105 and the bit line 107 exposed in the second step region 1303 and the first step region 1301 so that a next layer of the isolation layer 103 in the multi-layer stack 201 is exposed in each of the first step region 1301 and the second step region 1303.

Once the next layer of isolation layer 103 in multi-layer stack 201 is exposed in each of first step region 1301 and second step region 1303, photoresist 56 (shown in fig. 13E) may be trimmed again to expose another portion of multi-layer stack 201 in third step region 1305 while masking the remaining portion of multi-layer stack 201. The trimming of the photoresist 56 and the step etch process may be repeated until the desired number of step areas are exposed. In the illustrated embodiment, three step areas are exposed and the last trim of the photoresist 56 exposes a third step area 1305. However, fewer stepped regions may be formed. For example, in a multi-layer stack 201 including a smaller number of source lines 105 or bit lines 107 (e.g., two), fewer step areas (e.g., two) may be formed. As another example, in a multi-layer stack 201 including a greater number of source lines 105 or bit lines 107 (e.g., four, five, six, …, etc.), more rung areas (e.g., four, five, six, …, etc.) may be formed.

Once a desired number (e.g., three) of the step areas are exposed, step contact area 1307 is exposed by using trim photoresist 56 as a mask and etching the exposed portions of isolation layer 103 (shown in fig. 13F) in the step areas. Etching may remove portions of the uppermost layer of the isolation layer 103 such that the next layer of the metal fill material 1001 forming the source line 105 and the bit line 107 in the multi-layer stack 201 is exposed in each of the first step region 1301, the second step region 1303, and the third step region 1305. These exposed portions of the metallic fill material 1001 can act as step contact regions 1307.

In addition, fig. 13A-13G illustrate the formation of conductive contacts 1309 over the landing contact regions 1307 and word lines 109, according to some embodiments. FIG. 13G shows a cross-sectional view of the memory array 100 and an underlying substrate along line F-F of FIG. 13A. The conductive contacts 1309, the step contact regions 1307, and the isolation layer 103 may be collectively referred to as a step contact structure 1313. The step contact structures 1313 of adjacent memory elements 125 may be separated by a width equal to the first width W1 of the array spacer 117.

Conductive contacts 1309 can be electrically connected to conductive source line structures 1407, conductive bit line structures 1409, or conductive word line structures 1405, which connect the memory array 100 to underlying active devices and/or signal, power, and ground lines in the semiconductor die. For example, the conductive vias 1180 may extend through the inter-metal dielectric (IMD)700 in order to electrically connect the conductive source line structures 1407 and conductive bit line structures 1409 to the underlying circuitry of the interconnect structure 2200 and active devices on the substrate 101. In alternative embodiments, routing and/or power lines to and from the memory array may be provided by interconnect structures formed above the memory array 100 in addition to or in place of the interconnect structure 2200. Thus, the memory array 100 is completed.

In an embodiment in which the conductive contacts 1309 are conductive pillars (e.g., tungsten, copper, aluminum, titanium, alloys, combinations, or the like), the conductive contacts 1309 may be formed by initially forming the IMD 700 over the first and second regions 205, 207 of the multi-layer stack 201. Once formed, IMD 700 is patterned using suitable photolithography and etch processes to form openings through the interlayer dielectric layer and exposed areas of the word lines 109 and/or landing contact regions 1307 in desired locations of the conductive contacts 1309. Once the openings have been formed, the openings may be filled and/or overfilled with a conductive fill material (e.g., W, Al, Cu, or the like) using a suitable deposition process (e.g., Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or the like). Once deposited, a planarization process can be performed to planarize the top surface of the conductive contacts 1309 so as to be coplanar with the surface of the interlayer dielectric layer. According to some embodiments, once the conductive contacts 1309 have been formed, an interlayer dielectric layer (not shown) may be retained so as to allow further processing of the first 3D-NOR memory array 100.

Although the embodiment of fig. 13A-13G show a particular pattern of the step contact structure 1313, other configurations are possible. For example, in the illustrated embodiment, source line 105 and bit line 107 in the same column of the array are both aligned with each other, and the step contact region 1307 of bit line 107 is formed on the same side of 3D memory array 100 as source line 105. However, in other embodiments, the stepped contact region 1307 of the bit line 107 may be formed on the opposite side of the 3D memory array 100 from the stepped contact region 1307 of the source line 105. In addition, the word lines 109 of adjacent memory devices can be aligned with the word lines 109 of the memory devices 125, but the word lines 109 of one memory device 125 can also be offset from the word lines 109 of an adjacent memory device such that the word lines 109, and thus the conductive contacts 1309 connected to the word lines 109, have a staggered arrangement from the memory device 125 to the adjacent memory device.

Embodiments of the present disclosure have some advantageous features. Forming a 3-dimensional (3-dimensional; 3D) memory array (e.g., a NOR memory array) that includes a plurality of stacked memory devices and includes forming a metal-free multilayer stack including dummy source lines and dummy bit lines, and subsequently replacing the dummy source lines and dummy bit lines with a conductive material to form source lines and bit lines may allow for simplifying subsequent etching processes for patterning the gate structure and allow for better etch profiles than may be achieved when the multilayer structure includes one or more metal layers. In addition, the source and bit lines corresponding to each memory element are formed in the same layer, allowing the height and aspect ratio of the metal-free multi-layer stack for the fabrication process to be reduced. The resulting memory array may also have a reduced height, thereby increasing device density. In addition, embodiments of the present disclosure allow a source line of a first memory device and a bit line of an adjacent second memory device formed in the same layer to be separated from each other so that interference between the first memory device and the second memory device is minimized when a read and/or write operation is performed in the first memory device and the second memory device.

According to an embodiment, a method of three-dimensional memory device fabrication includes forming a multi-layer stack including alternating layers of isolation material and semiconductor material; patterning the multi-layer stack to form a first channel structure in a first region of the multi-layer stack, wherein the first channel structure comprises a semiconductor material; depositing a memory thin film layer over the first channel structure; etching a first trench through a second region of the multi-layer stack to form a first dummy bit line and a first dummy source line in the second region, wherein the first dummy bit line and the first dummy source line each comprise a semiconductor material; and replacing the semiconductor material of the first dummy bit line and the first dummy source line with a conductive material to form a first bit line and a first source line. In one embodiment, forming the multi-layer stack includes depositing a dielectric material as an isolation material; and depositing an oxide semiconductor material as the semiconductor material. In one embodiment, replacing the semiconductor material of the first dummy bit line and the first dummy source line includes etching the semiconductor material through the first trench. In one embodiment, etching the semiconductor material includes selectively etching the semiconductor material using a chlorine or fluorine based etchant. In an embodiment, patterning the multi-layer stack to form the first channel structure includes selectively etching the isolation material in the first region of the multi-layer stack using an etch chemistry including phosphorous. In one embodiment, displacing the semiconductor material includes etching sidewalls of the first channel structure so as to define the recess. In one embodiment, displacing the semiconductor material further comprises filling the recess with a conductive material. In one embodiment, the method further comprises forming a conductive structure around the memory thin film layer; etching an opening through the conductive structure in a location between the first channel structure and an adjacent second channel structure; and depositing a dielectric material in the opening.

According to an embodiment, a method of three-dimensional memory device fabrication includes forming a multi-layer stack including alternating layers of a first material and a second material; forming a plurality of trenches in a first region of the multilayer stack, the strips being between adjacent ones of the trenches; etching a first material from the strip to form a plurality of channel structures, wherein the channel structures comprise a second material; depositing a memory thin film layer over the channel structure; forming a plurality of first openings in the multilayer stack on opposite sides of the first region; etching the exposed second material along sidewalls of the first openings to form a plurality of second openings connected to the first openings; and filling the first opening and the second opening connected to the first opening with a conductive material to form a first source line and a first bit line on a first side of the first region and a second source line and a second bit line on a second side of the first region opposite to the first side. In one embodiment, the first source line, the first bit line, the second source line, and the second bit line are formed in the same layer. In one embodiment, a first memory element of a memory array includes a first source line and a second bit line, a second memory element of the memory array adjacent to the first memory element includes the first bit line and a third memory element of the memory array adjacent to the first memory element includes the second source line. In one embodiment, the second material includes an oxide semiconductor film. In an embodiment, etching the first material from the strips to form the channel structures results in each of the channel structures having a circular, square, rectangular, hexagonal, or octagonal profile shape. In an embodiment, the method further comprises etching the conductive material to form a plurality of third openings in the multilayer stack; and filling the third opening with a dielectric material.

According to an embodiment, a three-dimensional memory device includes a semiconductor substrate; a first memory element over the semiconductor substrate, the first memory element including a first channel region; a second memory element over the first memory element, the second memory element including a second channel region over the first channel region; a memory thin film layer surrounding the first channel region and the second channel region; surrounding word lines surrounding the memory thin film layer; a first source line on a first side of the first channel region; and a first bit line on a second side of the first channel region opposite the first side, wherein a sidewall of the first channel region facing the first bit line is biased from a sidewall of the memory film layer facing the first bit line. In one embodiment, the device further comprises a stack of source lines and a stack of bit lines, wherein the stack of source lines comprises a first source line, and wherein the stack of bit lines comprises a first bit line. In an embodiment, the device further includes a plurality of first isolation layers between adjacent source lines in the stack of source lines; and a plurality of second isolation layers between adjacent bit lines in the stack of bit lines. In an embodiment, a length of a source line in the stack of source lines increases in a direction towards the semiconductor substrate, and a length of a bit line in the stack of bit lines increases in a direction towards the semiconductor substrate. In one embodiment, the first and second channel regions include an oxide semiconductor film. In one embodiment, each of the first and second channel regions has a circular, square, rectangular, hexagonal, or octagonal profile shape.

The foregoing outlines features of various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.