阅读说明：本技术 印刷布线板 (Printed wiring board ) 是由 木村隼一 新田耕司 酒井将一郎 曾我部万里 坪仓光隆 土子哲 岩本昌 于 2020-05-15 设计创作，主要内容包括：本公开的印刷布线板具备：具有绝缘性的基材层；第一导电层,直接地或间接地层叠于上述基材层的表面,并包括铜箔；第二导电层,直接地或间接地层叠于上述基材层的背面,并包括铜箔；以及通孔用层叠体,层叠于在厚度方向上贯通上述第一导电层和上述基材层的连接孔的内周及底,并将上述第一导电层和上述第二导电层之间电连接,上述通孔用层叠体具有层叠在上述连接孔的内周及底上的非电解镀铜层和层叠在上述非电解镀铜层表面上的电解镀铜层,上述铜箔含有沿(100)面方向进行取向的铜晶粒,上述铜箔中铜的平均晶粒直径为10μm以上,上述非电解镀铜层包含钯和锡,上述铜箔表面的每单位面积的上述钯的层叠量为0.18μg/cm～(2)以上且0.40μg/cm～(2)以下。(The disclosed printed wiring board is provided with: a base material layer having an insulating property; a first conductive layer directly or indirectly laminated on the surface of the substrate layer and including a copper foil; a second conductive layer directly or indirectly laminated on the back surface of the substrate layer and including a copper foil; and a through-hole laminate which is laminated on the inner periphery and bottom of a connection hole penetrating the first conductive layer and the base material layer in the thickness direction and electrically connects the first conductive layer and the second conductive layer, wherein the through-hole laminate has an electroless copper plating layer laminated on the inner periphery and bottom of the connection hole and an electroless copper plating layer laminated on the inner periphery and bottom of the connection holeAn electrolytically plated copper layer on a surface of the electroless plated copper layer, the copper foil containing copper crystal grains oriented in a (100) plane direction, the copper foil having an average crystal grain diameter of 10 [ mu ] m or more, the electroless plated copper layer containing palladium and tin, and a stacking amount of the palladium per unit area of the surface of the copper foil being 0.18 [ mu ] g/cm 2 Above and 0.40. mu.g/cm 2 The following.)

1. A printed wiring board is provided with:

a base material layer having an insulating property;

the first conducting layer is directly or indirectly laminated on the surface of the substrate layer and comprises copper foil;

the second conducting layer is directly or indirectly laminated on the back surface of the substrate layer and comprises copper foil; and

a through-hole laminate which is laminated on the inner periphery and bottom of a connection hole penetrating the first conductive layer and the base material layer in the thickness direction and electrically connects the first conductive layer and the second conductive layer,

the laminated body for a through hole has an electroless copper plating layer laminated on the inner periphery and bottom of the connection hole and an electrolytic copper plating layer laminated on the surface of the electroless copper plating layer,

the copper foil contains copper crystal grains oriented in the (100) plane direction, the average crystal grain diameter of copper in the copper foil is more than 10 mu m,

the electroless copper plating layer comprises palladium and tin,

the amount of the palladium laminated per unit area of the surface of the copper foil was 0.18. mu.g/cm²Above and 0.40. mu.g/cm²The following.

2. The printed wiring board of claim 1,

the laminated amount of the tin per unit area of the surface of the copper foil is 0.05 [ mu ] g/cm²Above and 1.20. mu.g/cm²The following.

3. The printed wiring board according to claim 1 or claim 2,

the ratio of the area of copper crystal grains oriented in the (100) plane direction existing on the surface of the copper foil to the area of the surface of the copper foil is 50% or more.

4. The printed wiring board according to claim 1, claim 2, or claim 3, wherein,

the amount of the palladium laminated per unit area of the surface of the copper foil was 0.18. mu.g/cm²Above and 0.35. mu.g/cm²The following.

5. The printed wiring board according to any one of claim 1 to claim 4,

the ratio of the area of copper crystal grains oriented in the (100) plane direction existing on the surface of the copper foil to the area of the surface of the copper foil is 60% or more.

6. The printed wiring board according to any one of claim 1 to claim 5,

the electroless copper-plated layer 8 has an average thickness of 0.01 to 1.0 [ mu ] m.

Technical Field

The present disclosure relates to a printed wiring board.

The present application claims priority from japanese application No. 2019-092388 filed on 15/5/2019 and incorporates all the contents described in the above japanese application.

Background

In recent years, miniaturization of electronic devices has progressed, and high-density wiring of printed wiring boards used in electronic devices has been demanded. In response to such a demand, a multilayer printed wiring board having a plurality of patterned conductive layers is mostly used. In order to connect patterns of different conductive layers, a multilayer printed wiring board includes, for example, through holes penetrating through a base material layer having metal foils laminated as conductive layers on the front and back sides. The through hole has an electroless copper plating layer and an electrolytic copper plating layer formed on the inner peripheral surface of a hole penetrating the base material layer. (see Japanese patent laid-open publication No. 2004-214410).

Documents of the prior art

Patent document

Patent document 1: refer to Japanese patent application laid-open No. 2004-214410

Disclosure of Invention

The disclosed printed wiring board is provided with: a base material layer having an insulating property; a first conductive layer directly or indirectly laminated on the surface of the substrate layer and including a copper foil; a second conductive layer directly or indirectly laminated on the back surface of the substrate layer and including a copper foil; and a laminate for a through-hole which is laminated on an inner periphery and a bottom of a connection hole penetrating the first conductive layer and the base material layer in a thickness direction and electrically connects the first conductive layer and the second conductive layer, wherein the laminate for a through-hole has an electroless copper plating layer laminated on the inner periphery and the bottom of the connection hole and an electrolytic copper plating layer laminated on a surface of the electroless copper plating layer, the copper foil contains copper crystal grains oriented in a (100) plane direction, an average crystal grain diameter of copper in the copper foil is 10 μm or more, the electroless copper plating layer contains palladium and tin, and a lamination amount of the palladium per unit area of a surface of the copper foil is 0.18 μ g/cm²Above and 0.40. mu.g/cm²The following.

Drawings

Fig. 1 is a schematic cross-sectional view illustrating a printed wiring board according to an embodiment.

Fig. 2 is a schematic perspective view illustrating a connection hole of the printed wiring board of fig. 1.

Detailed Description

[ problem to be solved by the present disclosure ]

Copper foil is widely used as the wiring layer of the via hole, and further improvement of mechanical properties such as bendability is required for the copper foil. For example, in copper foil, in order to improve mechanical properties, studies have been made on the orientation of copper crystals, the grain size, and the like. However, when electroless copper plating is performed on the surface of a copper foil having a crystal orientation and a crystal grain diameter within a specific range and then electrolytic copper plating is performed, the crystal of copper in the electrolytic copper plating layer may locally grow abnormally. If the crystal of copper locally grows abnormally in this way, unevenness occurs on the surface of the electrolytic copper plating layer, and thus, the crystal may be erroneously detected as a defect when an appearance Inspection is performed by an automatic Optical Inspection system (AOI). In addition, since a large amount of copper is deposited on the convex portion formed on the surface of the electrolytic copper plating layer, copper is not sufficiently deposited on the bottom portion of the through hole, and as a result, the bottom portion of the through hole may be peeled off from the conductive layer.

The present disclosure has been made in view of the above circumstances, and an object thereof is to provide a printed wiring board capable of suppressing erroneous detection during appearance inspection by an automatic optical inspection apparatus and peeling of the bottom of a through hole.

[ Effect of the present disclosure ]

According to the present disclosure, a printed wiring board capable of suppressing erroneous detection during appearance inspection and peeling of the bottom of a through hole can be provided.

[ description of embodiments of the present disclosure ]

First, embodiments of the present disclosure are explained by way of examples.

The disclosed printed wiring board is provided with: a base material layer having an insulating property; a first conductive layer directly or indirectly laminated on the surface of the substrate layer and including a copper foil; a second conductive layer directly or indirectly laminated on the back surface of the substrate layer and including a copper foil; and a laminate for a through-hole which is laminated on an inner periphery and a bottom of a connection hole penetrating the first conductive layer and the base material layer in a thickness direction and electrically connects the first conductive layer and the second conductive layer, wherein the laminate for a through-hole has an electroless copper plating layer laminated on the inner periphery and the bottom of the connection hole and an electrolytic copper plating layer laminated on a surface of the electroless copper plating layer, the copper foil contains copper crystal grains oriented in a (100) plane direction, an average crystal grain diameter of copper in the copper foil is 10 μm or more, the electroless copper plating layer contains palladium and tin, and a lamination amount of the palladium per unit area of a surface of the copper foil is 0.18 μ g/cm²Above and 0.40. mu.g/cm²The following.

Laminated stampThe copper foil on the surface of the base material layer of the brush wiring board contains copper crystal grains oriented in the (100) plane direction, and the average crystal grain diameter of the copper is 10 [ mu ] m or more. In this case, the orientation of the copper crystal grains of the above copper foil is easily inherited by the copper crystal grains precipitated by electroless copper plating and the copper crystal grains precipitated by electrolytic copper plating. As a result, an electroless copper plating layer and an electrolytic copper plating layer having the same orientation as the copper crystal grains of the copper foil are formed. Further, there is a possibility that the crystal of copper in the electrolytic copper plating layer abnormally grows locally to generate unevenness on the surface of the electrolytic copper plating layer. In this printed wiring board, since the electroless copper plating layer contains palladium as a catalyst, the orientation of the copper crystal grains of the copper foil is suppressed from being inherited by the copper crystal grains precipitated by electroless copper plating. As a result, the formation of irregularities on the surface of the electrolytic copper plating layer due to abnormal growth of copper crystals in the electrolytic copper plating layer is suppressed. Therefore, the printed wiring board can suppress erroneous detection during appearance inspection by an automatic optical inspection device and peeling of the bottom of the through hole. In the printed wiring board, the amount of palladium stacked per unit area on the surface of the copper foil is 0.18. mu.g/cm²Above and 0.40. mu.g/cm²Consequently, the amount of catalyst nuclei generated by electroless copper plating increases, and the growth of plating having a different orientation from the copper crystal grains of the copper foil is promoted. As a result, the effect of suppressing the formation of an electroless copper plating layer having the same orientation as the copper crystal grains of the copper foil can be improved. Therefore, the effect of suppressing erroneous detection and peeling of the bottom of the through hole in the visual inspection by the automatic optical inspection device can be improved. In addition, since the electroless copper plating layer contains tin as a catalyst in addition to palladium, the catalyst is in the form of a tin-palladium colloidal solution. Therefore, the amount of palladium stacked on the copper foil is easily increased, and the effect of suppressing the formation of an electroless copper plating layer having the same orientation as the copper crystal grains of the copper foil can be further improved. Therefore, the effect of suppressing erroneous detection and peeling of the bottom of the through hole in the visual inspection by the automatic optical inspection device can be improved.

Here, the term "grain size" refers to, for example, the grain boundary detected by analyzing the crystal orientation of the surface of the copper foil to be a sample by the EBSD (Electron back scattering Diffraction) method, the region surrounded by the grain boundary is defined as a grain, and the diameter of a circle having the same area as the area of the region is defined as the grain size of each grain. The "average crystal grain diameter" refers to an average value of crystal grain diameters of crystal grains present in a predetermined measurement field. The surface orientation of the copper crystal grains of the copper foil was calculated by measuring the randomly extracted portions of the surface of the copper foil a plurality of times by the EBSD method. The "average thickness" means an average value of thicknesses measured at arbitrary 10 points.

The amount of tin laminated per unit area on the surface of the copper foil is preferably 0.05. mu.g/cm²Above and 1.20. mu.g/cm²The following. Since the amount of tin stacked is within the above range, the amount of palladium stacked on the copper foil can be adjusted to a favorable range, and the effect of suppressing the formation of an electroless copper plating layer having the same orientation as the copper crystal grains of the copper foil can be further improved.

In the printed wiring board, a ratio of an area of copper crystal grains oriented in a (100) plane direction existing on the surface of the copper foil to an area of the surface of the copper foil is preferably 50% or more. Since the ratio of the area of the copper crystal grains oriented in the (100) plane direction existing on the surface of the copper foil to the area of the surface of the copper foil is 50% or more, the effect of suppressing local abnormal growth of the copper crystal of the electrolytic copper plating layer is improved.

Here, the "ratio of the area of the copper crystal grains oriented in the (100) plane direction" means a ratio of the area of the region of the copper crystal grains oriented in the (100) plane direction to the area of the entire copper foil surface.

The amount of the palladium layer stacked per unit area on the surface of the copper foil is preferably 0.18. mu.g/cm²Above and 0.35. mu.g/cm²The following. Since the amount of palladium stacked is within the above range, the amount of catalyst nuclei produced by electroless copper plating is within an appropriate range. As a result, it is considered that it is further difficult to form an electroless copper-plated layer and an electrolytic copper-plated layer having the same orientation as the copper crystal grains of the copper foil。

The ratio of the area of the copper crystal grains oriented in the (100) plane direction present on the surface of the copper foil to the area of the surface of the copper foil is preferably 60% or more. Since the ratio of the area of the copper crystal grains oriented in the (100) plane direction existing on the surface of the copper foil is within the above range, the effect of suppressing local abnormal growth of the copper crystal of the electrolytic copper plating layer is improved.

The average thickness of the electroless copper plating layer is preferably 0.01 to 1.0 μm. Since the average thickness of the electroless copper plating layer is within the above range, the electrolytic copper plating layer can be formed uniformly, and the orientation of the copper crystal grains of the copper foil can be suppressed from being inherited by the copper crystal grains precipitated by electroless copper plating.

[ details of embodiments of the present disclosure ]

Hereinafter, embodiments of the printed wiring board according to the present disclosure will be described in detail with reference to the drawings.

< printed Wiring Board >

Fig. 1 shows a printed wiring board according to an embodiment of the present disclosure. The printed wiring board 20 includes: a substrate layer 1 having an insulating property; a first conductive layer 2 directly or indirectly laminated on the surface of the substrate layer 1 and including a copper foil; a second conductive layer 3 directly or indirectly laminated on the back surface of the substrate layer 1 and including a copper foil; and a through-hole laminate 10 that is laminated on the inner periphery and bottom of a connection hole 5 penetrating the first conductive layer 2 and the base material layer 1 in the thickness direction, and electrically connects the first conductive layer 2 and the second conductive layer 3. The via hole 4 for connecting between the patterns of different conductive layers is formed by laminating a through-hole laminate 10 on the connection hole 5.

The components of the printed wiring board will be described in detail below.

[ base Material layer ]

Examples of the material of the base layer 1 include polyamide, polyimide, polyamideimide, and polyester. Among them, for example, polyamide, polyimide, and polyamideimide are preferably used from the viewpoint of mechanical strength such as heat resistance. The printed wiring board may not necessarily have flexibility.

The lower limit of the average thickness of the base material layer 1 is preferably 5 μm, and more preferably 10 μm. On the other hand, the upper limit of the average thickness of the base material layer 1 is preferably 100 μm, and more preferably 50 μm. If the average thickness of the base material layer 1 is less than the lower limit, the strength of the base material layer 1 may be insufficient. Conversely, when the average thickness of the base material layer 1 exceeds the above upper limit, there is a concern that the flexibility is insufficient.

[ conductive layer ]

The first conductive layer 2 and the second conductive layer 3 are formed by patterning a copper foil laminated on the base material layer 1. The copper foil contains copper crystal grains oriented in the (100) plane direction, and the average crystal grain diameter of copper in the copper foil is 10 [ mu ] m or more. Since the copper foil has a copper crystal grain in the plane direction and an average crystal grain diameter within the above ranges, the copper foil is excellent in mechanical properties such as flexibility.

In general, the patterning of the conductors forming the first conductive layer 2 and the second conductive layer 3 is performed after the formation of the through holes 4. In order to increase the wiring density, the first conductive layer 2 and the second conductive layer 3 may have a pad to which the via hole 4 is connected and a wiring pattern having a smaller width than the pad and extending linearly.

The copper foil contains copper crystal grains oriented in the (100) plane direction. The lower limit of the average grain size of copper in the copper foil is 10 μm, preferably 12 μm. The upper limit of the average grain size of copper in the copper foil is not particularly limited, and may be, for example, 100 μm, preferably 80 μm, and more preferably 55 μm. When the average crystal grain size of copper in the copper foil is less than 10 μm, the appearance of the surface of the electrolytic copper plating layer is not always good, and the effects of the printed wiring board cannot be sufficiently exhibited.

In the printed wiring board, the lower limit of the ratio of the area of the copper crystal grains oriented in the (100) plane direction present on the surface of the copper foil to the area of the surface of the copper foil is preferably 40%, more preferably 60%, and still more preferably 80%. Since the ratio of the area of the copper crystal grains oriented in the (100) plane direction existing on the surface of the copper foil to the area of the surface of the copper foil is in the above range, the effect of suppressing local abnormal growth of the copper crystal of the electrolytic copper plating layer is improved. When the area ratio is less than 40%, the appearance of the surface of the electrolytic copper plating layer is not likely to be deteriorated, and the effects of the printed wiring board cannot be sufficiently exhibited.

The ratio of the area of the copper crystal grains oriented in the (100) plane direction present on the surface of the copper foil to the area of the surface of the copper foil is not particularly limited, but may be achieved by, for example, controlling the element content, controlling the rolling conditions, performing heat treatment, or the like.

From the viewpoint of ensuring sufficient conductivity, the lower limit of the average thickness of the first conductive layer 2 and the second conductive layer 3 is preferably 2 μm, and more preferably 5 μm. On the other hand, from the viewpoint of circuit formability, the upper limit of the average thickness of the first conductive layer 2 and the second conductive layer 3 is preferably 100 μm, and more preferably 50 μm.

[ laminate for Via hole ]

The via-hole laminate 10 includes an electroless copper-plated layer 8 laminated on the inner periphery and bottom of the connection hole 5, and an electrolytic copper-plated layer 7 laminated on the surface of the electroless copper-plated layer 8. The through-hole laminate 10 is laminated on the inner periphery and bottom of the via hole 5 penetrating the first conductive layer 2 and the base material layer 1 in the thickness direction. The via laminate 10 electrically connects the first conductive layer 2 and the second conductive layer 3. More specifically, the through-hole laminate 10 may have a structure including an electroless copper plating layer 8 laminated on the inner periphery of the via hole 5, the surface of the first conductive layer 2 opposite to the base material layer 1, and the surface (i.e., the bottom) of the second conductive layer 3 exposed to the inside of the via hole 5, and an electrolytic copper plating layer 7 further laminated on the electroless copper plating layer 8.

Fig. 2 shows a state before forming the via hole 4 and patterning the first conductive layer 2 and the second conductive layer 3 to show the shape of the connection hole 5. The connection hole 5 penetrates the base material layer 1 and the first conductive layer 2 in the thickness direction, and is defined by a cylindrical surface on which the connection hole 5 is formed. Then, the via-hole laminated body 10 is laminated on the connection hole 5, thereby forming a via hole 4 for connecting between the patterns of the first conductive layer 2 and the second conductive layer.

(electroless copper plating layer)

The electroless copper-plated layer 8 is a thin layer having conductivity, and is used as an adherend when the electrolytic copper-plated layer 7 is formed by electrolytic copper plating. The electroless copper plating layer 8 may be formed of copper laminated by electroless copper plating. Copper plating is suitable for printed wiring boards because of its flexibility, thickening ability, good adhesion to electroplated copper, and high conductivity. The electroless copper plating is a treatment for precipitating a metal having catalytic activity by the reduction action of a catalyst, and can be performed by applying various commercially available electroless copper plating solutions. By using electroless copper plating in this way, the electroless copper plating layer 8 can be easily laminated, and the electrolytic copper plating layer 7 can be further reliably laminated.

The lower limit of the average thickness of the electroless copper plating layer 8 is preferably 0.05 μm, and more preferably 0.10 μm. On the other hand, the upper limit of the average thickness of the electroless copper plating layer 8 is preferably 1.0 μm, and more preferably 0.5 μm. If the average thickness of the electroless copper plating layer 8 is less than the lower limit, the continuity of the electroless copper plating layer 8 may not be ensured, and the electrolytic copper plating layer 8 may not be formed uniformly. If the average thickness is less than the lower limit, the orientation of the copper crystal grains of the copper foil may be easily inherited by the copper crystal grains deposited by electroless copper plating. On the other hand, when the average thickness of the electroless copper plating layer 8 exceeds the above upper limit, there is a concern that the cost will increase unnecessarily. Since the average thickness of the electroless copper plating layer is within the above range, the electrolytic copper plating layer can be formed uniformly, and the orientation of the copper crystal grains of the copper foil can be suppressed from being inherited by the copper crystal grains precipitated by electroless copper plating.

The electroless copper plating layer 8 contains palladium and tin as catalysts. Palladium and tin are given as catalysts before an electroless copper plating layer lamination step described later, and an electroless copper plating layer is laminated thereon. Thus, palladium and tin are present in the electroless copper plating layer at high contents in the vicinity of the interface with the conductive layer. In the printed wiring board 20, since the electroless copper plating layer 8 contains palladium, the orientation of the copper crystal grains of the copper foil is suppressed from being inherited by the copper crystal grains precipitated by electroless copper plating. As a result, the formation of irregularities on the surface of the electrolytic copper plating layer 7 due to abnormal growth of copper crystals in the electrolytic copper plating layer 7 is suppressed. Therefore, the printed wiring board 20 can suppress erroneous detection during appearance inspection by an automatic optical inspection apparatus and peeling of the bottom of the through hole 4 from the second conductive layer 3. In addition, since the electroless copper plating layer contains tin in addition to palladium, the catalyst is in the form of a tin-palladium colloidal solution. Therefore, the amount of palladium stacked on the copper foil is easily increased, and the effect of suppressing the formation of an electroless copper plating layer having the same orientation as the copper crystal grains of the copper foil can be further improved. Therefore, the effect of suppressing erroneous detection and peeling of the bottom of the through hole in the visual inspection by the automatic optical inspection device can be improved.

The lower limit of the amount of palladium laminated per unit area on the surface of the copper foil is 0.18. mu.g/cm²More preferably 0.20. mu.g/cm². The upper limit of the amount of the palladium layer to be stacked is 0.40. mu.g/cm²Preferably 0.35. mu.g/cm². Since the amount of palladium stacked is within the above range, the amount of catalyst nuclei produced by electroless copper plating is within an appropriate range. As a result, it is considered that it is further difficult to form the electroless copper plating layer 8 and the electrolytic copper plating layer 7 having the same orientation as the copper crystal grains of the copper foil. If the amount of palladium stacked exceeds the upper limit, the connection strength between the copper foil included in the second conductive layer 3 and the electroless copper-plated layer 8 and the electrolytic copper-plated layer 7 at the bottom of the through hole 4 may be weakened, and the bottom of the through hole 4 may be peeled off.

The lower limit of the amount of tin laminated per unit area on the surface of the copper foil is preferably 0.05. mu.g/cm²More preferably 0.08. mu.g/cm²More preferably 0.15. mu.g/cm². The upper limit of the amount of tin stacked is preferably 1.20. mu.g/cm²More preferably 0.50g/cm². If the amount of tin lamination exceeds the upper limit, the amount of palladium that can function as a catalyst decreases, and therefore electroless copper plating may not be further advanced. Since the amount of tin stacked is within the above range, the copper foil can be covered with the tin-containing compositionThe amount of palladium to be stacked is adjusted to a good range, and the effect of suppressing the formation of an electroless copper plating layer having the same orientation as the copper crystal grains of the copper foil can be further improved.

(electrolytic copper plating layer)

The electrolytic copper-plated layer 7 is laminated on the surface of the electroless copper-plated layer 8 by electrolytic copper plating. By forming the electroless copper plated layer 8 in this manner and then providing the electrolytic copper plated layer 7 on the inner periphery and the bottom thereof, the through hole 4 having excellent conductivity can be formed easily and reliably. As described above, copper is inexpensive and has high conductivity, and therefore, copper is suitably used as the metal for forming the electrolytic copper plating layer.

The lower limit of the average thickness of the electrolytic copper plating layer 7 is preferably 1 μm, and more preferably 5 μm. On the other hand, the upper limit of the average thickness of the electrolytic copper plating layer 7 is preferably 50 μm, and more preferably 30 μm. When the average thickness of the electrolytic copper-plated layer 7 is less than the lower limit described above, there is a concern that the through-hole 4 is broken due to bending or the like of the printed wiring board 20 and the electrical connection between the first conductive layer 2 and the second conductive layer 3 is disconnected. If the average thickness is less than the lower limit, the orientation of the copper crystal grains of the copper foil may be easily inherited by the copper crystal grains precipitated by electrolytic copper plating. On the other hand, when the average thickness of the electrolytic copper plating layer 7 exceeds the above upper limit, there is a concern that the printed wiring board 20 becomes excessively thick, and the manufacturing cost unnecessarily increases.

[ method for manufacturing printed Wiring Board ]

The method for manufacturing the printed wiring board comprises the following steps: a conductive layer laminating step of laminating a first conductive layer including a copper foil on a surface of a base material layer and laminating a second conductive layer including a copper foil on a back surface of the base material layer; a connection hole forming step of forming a connection hole penetrating the first conductive layer and the base material layer in a thickness direction; an electroless copper plating pretreatment step of performing pretreatment before electroless copper plating on the inner periphery and the bottom of the connection hole; an electroless copper plating layer laminating step of laminating electroless copper plating layers on the inner periphery and the bottom of the connection hole subjected to the electroless copper plating pretreatment; and an electrolytic copper plating layer laminating step of laminating an electrolytic copper plating layer on the surface of the electroless copper plating layer.

(conductive layer lamination Process)

In the conductive layer laminating step, the copper foil is laminated on the surface of the base layer, thereby forming a first conductive layer. The copper foil is laminated on the back surface of the base layer, thereby forming a second conductive layer. In the conductive layer laminating step, a conductive pattern is formed on the surface of the base material layer by a known method.

The method of laminating the copper foil constituting the first conductive layer and the second conductive layer on the base material layer is not particularly limited, and for example, an adhesive method of bonding copper foils with an adhesive; a casting method of coating a resin composition as a material of a base material layer on a copper foil; a sputtering/plating method of forming a copper foil by plating on a thin conductive layer (seed layer) having a thickness of several nm formed on a base material layer by a sputtering method or an evaporation method; and a lamination method in which a copper foil is attached to a base material layer by hot pressing.

(Process for Forming connecting hole)

The method for forming the hole for electrically connecting the first conductive layer and the second conductive layer is not particularly limited, and for example, a method of forming a hole in the first conductive layer and the base layer by a micro drill or a laser to expose the copper foil of the second conductive layer can be used.

(electroless copper plating pretreatment step)

The electroless copper plating pretreatment step is a step of performing pretreatment before electroless copper plating is performed on the inner periphery and bottom of the connection hole. In this step, for example, a cleaning step, an acid treatment step, a preliminary immersion step, a catalyst treatment step, a reduction step, and the like are performed.

The preliminary immersion step is a step of immersing the catalyst solution in a liquid obtained by removing the catalyst from the catalyst solution, or the like, before immersing the catalyst solution. In the pre-dipping step, water adhering to the surface of the conductive pattern is replaced, and the surface of the base material layer is brought into a state in which the catalyst is easily adhered, whereby the occurrence of unevenness in the dispersion state of the catalyst in the catalyst treatment step of the next step can be suppressed.

In the catalyst treatment step, a laminate including a base layer and a conductive layer is immersed in a solution containing a colloid of palladium and tin. The catalyst treatment step is followed by a water washing step. As described above, the catalyst treatment step using palladium and tin is performed after the conductive layer lamination step and before the electroless copper plating layer lamination step. Thus, palladium and tin are present in the electroless copper plating layer at high contents in the vicinity of the interface with the conductive layer.

In the reduction step, the catalyst is reduced. Specifically, palladium ion (Pd) is generated in the reduction step²⁺) Is reduced to palladium (Pd)⁰) And formed on the surface to become a catalyst core, and a palladium catalyst is supported on the surface of the conductive pattern. The reduction step is followed by a water washing step.

(step of laminating electroless copper plating layer)

In the electroless copper plating layer laminating step, electroless copper plating is performed on the inner periphery and the bottom of the connection hole to form an electroless copper plating layer. In the electroless copper plating step, a laminate including a base material layer and a conductive layer is immersed in an electroless copper plating solution in which a plating reaction is activated by heating, and copper is laminated on the surface of the conductive pattern. The electroless copper plating solution is preferably an alkaline bath.

The lower limit of the heating temperature of the electroless copper plating solution is preferably 20 ℃. On the other hand, the upper limit of the heating temperature of the electroless copper plating solution is preferably 40 ℃. If the heating temperature of the electroless copper plating solution is less than the lower limit, the plating reaction may be insufficient. On the other hand, when the heating temperature of the electroless copper plating solution exceeds the above upper limit, there is a concern that it is not easy to adjust the thickness of the formed electroless copper plating layer.

The lower limit of the immersion time in the electroless copper plating solution is preferably 1 minute, and more preferably 2 minutes. On the other hand, the upper limit of the immersion time in the electroless copper plating solution is preferably 30 minutes, and more preferably 20 minutes. If the immersion time in the electroless copper plating solution is less than the lower limit, there is a concern that a sufficient thickness of the electroless copper plating layer may not be formed. On the other hand, if the immersion time in the electroless copper plating solution exceeds the above upper limit, there is a concern that corrosion of the conductive pattern due to the local battery action cannot be sufficiently prevented.

(step of laminating electrolytic copper plating layer)

In the electrolytic copper plating layer laminating step, an electrolytic copper plating layer is laminated on the surface of the electroless copper plating layer by electrolytic copper plating. In this electrolytic copper plating step, the thickness of the through-hole laminate is increased to a desired thickness.

In the electrolytic copper plating layer laminating step of forming the electrolytic copper plating layer, the electrolytic copper plating layer in contact with the inner periphery and bottom of the electroless copper plating layer is formed by electrolytic copper plating of the laminated metal using the electroless copper plating layer as an adherend, and a through hole having a sufficient thickness can be formed.

According to the printed wiring board, when a copper foil in which copper crystal grains are oriented in the (100) plane direction and the average crystal grain diameter is 10 μm or more is used for the conductive layer, the formation of irregularities on the surface of the electrolytic copper plating layer of the laminate for via holes is suppressed. Therefore, the printed wiring board can suppress erroneous detection during appearance inspection by an automatic optical inspection device and peeling of the bottom of the through hole. Therefore, the printed wiring board is particularly suitable for use as a flexible printed wiring board used in small-sized portable electronic devices and the like.

[ other embodiments ]

The embodiments disclosed herein are illustrative in all respects and not restrictive. The scope of the present disclosure is not limited to the configuration of the above-described embodiments, but is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

In this printed wiring board, the first conductive layer and the second conductive layer are opposed to each other, and the conductive layer serving as the first conductive layer in one through hole may be the second conductive layer in the other through hole.

The printed wiring board may be a multilayer wiring board in which a base layer and a conductive layer are further laminated. The printed wiring board may also include other layers such as a cover lay, a solder resist, and a shield film. In addition, when the printed wiring board is a multilayer wiring board, the through-hole may be a through-hole penetrating through the multilayer.

Examples

Hereinafter, the present disclosure will be described in detail based on examples, but the present disclosure should not be construed restrictively based on the description of the examples.

[No.1～No.8]

As the substrate, ESPANEX (copper 12 μm/polyimide 12 μm/copper 12 μm) produced by Nissian chemical company was used. A copper foil oriented mainly in the (100) plane direction and having an average crystal grain diameter of 50 μm is laminated on the front and back surfaces of the base material to form conductive layers on the front and back surfaces of the base material (conductive layer laminating step). The copper and polyimide on the surface layer of the sample thus obtained were removed by UV laser to form a through hole (connection hole forming step). Next, electroless copper plating pretreatment is performed on substantially the entire surface of the conductive layer (electroless copper plating pretreatment step). In this electroless copper plating pretreatment step, as a catalyst treatment, a sample was immersed in a colloidal solution of palladium and tin (catalyst). The conditions of the electroless copper plating pretreatment steps of Nos. 1 to 8 are as follows.

(conditions of electroless copper plating pretreatment Process)

(1)No.1

Cleaning → soft etching (30 seconds) → pickling → presoaking → a catalyst (normal palladium concentration 0.13g/L, tin concentration 6g/L) → electroless copper plating was carried out.

(2)No.2

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (palladium concentration 1.5 times: 0.2g/L, tin concentration 9g/L in the solution) → electroless copper plating was carried out.

(3)No.3

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (normal palladium concentration: 0.13g/L, tin concentration 6g/L) → electroless copper plating was carried out.

(4)No.4

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (palladium concentration in solution 3 times: 0.4g/L, tin concentration 18g/L) → electroless copper plating.

(5)No.5

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (normal palladium concentration: 0.13g/L, tin concentration 6g/L) → electroless copper plating was carried out.

(6)No.6

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (palladium concentration 1.5 times: 0.2g/L, tin concentration 9g/L in the solution) → electroless copper plating was carried out.

(7)No.7

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (normal palladium concentration: 0.13g/L, tin concentration 6g/L) → electroless copper plating was carried out.

(8)No.8

Cleaning → soft etching (60 seconds) → pickling → presoaking → a catalyst (palladium concentration 1.5 times: 0.2g/L, tin concentration 9g/L in the solution) → electroless copper plating was carried out.

Electroless copper plating was performed at 23 ℃ for 15 minutes to laminate an electroless copper plating layer having an average thickness of 0.10 μm (electroless copper plating layer lamination step). Next, the current density was adjusted to 2A/dm relative to the exposed area of the conductive layer²Electrolytic copper plating was performed at 25 ℃ for 28 minutes. Thus, an electrolytic copper plating layer having an average thickness of 12 μm was laminated (electrolytic copper plating layer laminating step).

[ evaluation ]

(measurement of the amount of Stacking of Palladium and tin)

Regarding the amount of palladium and tin laminated on the copper foil, the printed wiring boards of Nos. 1 to 8 were cut into 20 mm. times.20 mm, dissolved in a mixed solution of nitric acid and hydrochloric acid, and the dissolved solution was measured by Inductively coupled plasma mass spectrometry (ICP-MS).

(degree of false detection in appearance inspection by automatic optical inspection apparatus)

100 printed wiring boards of nos. 1 to 8 were prepared, and these printed wiring boards were subjected to appearance inspection using an automatic optical inspection apparatus. Next, the printed wiring boards of nos. 1 to 8, in which the appearance defects were detected by the automatic optical inspection apparatus, were visually inspected by an optical microscope for the presence of accurate appearance defects. The percentage of false detection in the appearance inspection of the printed wiring boards of nos. 1 to 8 was calculated by an automatic optical inspection apparatus, and the printed wiring boards evaluated as a and B were judged to be acceptable by evaluation on three levels as follows.

A: the false detection rate is more than 0 percent and less than 6 percent

B: the false detection rate is more than 6 percent and less than 16 percent

C: the false detection rate is more than 16 percent

(occurrence of peeling at the bottom of through-hole)

The bottom of the through-hole was visually inspected by an optical microscope for peeling. Regarding the occurrence of peeling at the bottom of the through hole in each of the printed wiring boards of nos. 1 to 8, the ratio of the printed wiring boards in which peeling at the bottom of the through hole was observed among the 100 printed wiring boards of each test No. was calculated and evaluated on the following two scales. The printed wiring board evaluated as a was judged as passed according to the evaluation result.

A: the peeling rate is more than 0% and less than 3%

B: a peeling rate of 3% or more

The evaluation results are shown in table 1.

[ Table 1]

As shown in Table 1, the copper foil had an average crystal grain size of 10 μm or more and the amount of palladium stacked per unit area of the surface of the copper foil was 0.18. mu.g/cm²Above and 0.40. mu.g/cm²The following test nos. 1 to 2, 6 and 8 are excellent in the effect of suppressing erroneous detection and peeling of the bottom of the through hole in the visual inspection by the automatic optical inspection apparatus. In particular, among them, test nos. 1 to 2 and 6, in which the ratio of the area of copper crystal grains oriented in the (100) plane direction present on the surface of the copper foil to the area of the surface of the copper foil is 50% or more, are excellent in the effect of suppressing erroneous detection at the time of appearance inspection by an automatic optical inspection apparatus and peeling of the bottom of the through hole.

On the other hand, the amount of palladium laminated per unit area on the surface of the copper foil is less than 0.18. mu.g/cm²Test Nos. 3, 5 and 7 for the test using the automatic lightThe chemical examination device has a poor effect of suppressing erroneous detection during the appearance examination. Further, the amount of the palladium layer per unit area on the surface of the copper foil exceeds 0.40. mu.g/cm²Test No.4 (a) had a poor effect of suppressing the peeling of the bottom of the through-hole.

Description of the reference numerals

1 base material layer

2 first conductive layer

3 second conductive layer

4 through hole

5 connecting hole

7 electrolytic copper plating layer

8 electroless copper plating layer

Laminate for 10-via hole

20 printed wiring board.