阅读说明：本技术 在集成电路器件中传输信号的电路和方法 (Circuit and method for transmitting signal in integrated circuit device ) 是由 S·R·G·阿加瓦尔 R·K·塔尼克拉 于 2020-04-28 设计创作，主要内容包括：描述了一种用于在集成电路器件中传输信号的电路。所述电路包括：第一裸片(501)；堆叠在第一裸片(501)上的第二裸片(502)；以及在第一裸片(501)和第二裸片(502)之间传输数据的缓冲器(513)；其中缓冲器(513)的第一反相器(512)在第一裸片(501)上,缓冲器(513)的第二反相器(514)在第二裸片(513)上。还描述了一种在集成电路器件中传输信号的方法。(A circuit for transmitting signals in an integrated circuit device is described. The circuit comprises: a first die (501); a second die (502) stacked on the first die (501); and a buffer (513) to transfer data between the first die (501) and the second die (502); wherein a first inverter (512) of the buffer (513) is on the first die (501) and a second inverter (514) of the buffer (513) is on the second die (513). A method of transmitting signals in an integrated circuit device is also described.)

1. A circuit for transmitting signals in an integrated circuit device, the circuit comprising:

a first die;

a second die stacked on the first die; and

a buffer to transfer data between the first die and the second die;

wherein a first inverter of the buffer is on the first die and a second inverter of the buffer is on the second die.

2. The circuit of claim 1, wherein the first inverter is configured to receive a reference voltage and the second inverter is configured to receive a gated reference voltage based on the reference voltage.

3. The circuit of claim 2, further comprising a third inverter on the second die, wherein the third inverter is configured to receive an output of the first inverter and the reference voltage.

4. The circuit of claim 3, further comprising a third die stacked on the second die, wherein the third inverter is configured to transfer the data from the first die to the third die.

5. The circuit of claim 2, wherein the second die comprises interconnect elements configured to receive a second gated reference voltage.

6. The circuit of claim 5, wherein the interconnect element comprises a selection circuit having a selection input configured to receive a control signal from a memory element configured to receive the second gated reference voltage.

7. The circuit of claim 1, wherein the first inverter comprises a tri-state inverter and is configured to receive a tri-state signal, and wherein the second inverter is configured to receive a gated reference voltage.

8. The circuit of claim 7, wherein the first inverter and the second inverter are coupled to a pillar connection extending between the first die and the second die.

9. The circuit of claim 1, further comprising a power gating circuit coupled to a second inverter of the buffer, wherein the power gating circuit is configured to apply a gated reference voltage to the second inverter.

10. The circuit of claim 1, wherein the first inverter is associated with an input/output block of the first die and the second inverter is associated with an input/output block of the second die.

11. A method of transmitting signals in an integrated circuit device, the method comprising:

providing a first die;

stacking a second die on the first die; and

transferring data between the first die and the second die through a buffer;

wherein a first inverter of the buffer is on the first die and a second inverter of the buffer is on the second die.

12. The method of claim 11, further comprising configuring the first inverter to receive a reference voltage and configuring the second inverter to receive a gated reference voltage based on the reference voltage.

13. The method of claim 12, further comprising implementing a third inverter on the second die, wherein the third inverter is configured to receive the reference voltage.

14. The method of claim 13, further comprising stacking a third die on the second die, wherein the third inverter is configured to transfer the data from the first die to the third die.

15. The method of claim 12, further comprising configuring interconnect elements of the second die to receive a second gated reference voltage, wherein configuring interconnect elements comprises configuring a selection circuit having a selection input coupled to receive a control signal from a storage element configured to receive the second gated reference voltage.

Technical Field

The present invention relates generally to integrated circuit devices, and more particularly, to circuits and methods for transmitting signals in integrated circuit devices.

Background

The implementation of integrated circuit devices is constantly changing, striving to reduce the size, reduce power, and improve performance of integrated circuit devices. For any product, there is always an effort to improve the yield of integrated circuit devices during the manufacturing process. Recently, integrated circuit devices have been developed having multiple dies (die) that may be placed on an interposer that enables signal communication between the multiple dies. Other embodiments of the integrated circuit device include multiple dies stacked on top of each other, wherein circuitry on the stacked dies can transmit signals through the interconnection units between the dies, such as through-silicon vias (TSVs).

However, during the fabrication of stacked integrated circuit devices, there may be defects at the die or at the connections between the dies, which may reduce yield and impact performance.

Accordingly, there is a need for a circuit and method for transmitting signals in an integrated circuit device having multiple dies that reduces the problems associated with conventional devices.

Disclosure of Invention

A circuit for transmitting signals in an integrated circuit device is described. The circuit may include a first die, a second die stacked on the first die, and a buffer to transfer data between the first die and the second die, wherein a first inverter of the buffer is on the first die and a second inverter of the buffer is on the second die.

In some embodiments, the first inverter may be configured to receive a reference voltage, and the second inverter may be configured to receive a gated reference voltage (gated reference voltage) based on the reference voltage.

In some implementations, the circuit can further include a third inverter on the second die, where the third inverter is configured to receive an output of the first inverter and the reference voltage.

In some embodiments, the circuit may further include a third die stacked on the second die, wherein the third inverter is configured to transmit data from the first die to the third die.

In some embodiments, the second die may include an interconnect unit configured to receive a second gated reference voltage.

In some embodiments, the interconnect unit may include a selection circuit having a selection input configured to receive a control signal from a memory cell configured to receive a second gated reference voltage.

In some embodiments, the first inverter may comprise a tri-state inverter and may be configured to receive a tri-state signal, and the second inverter may be configured to receive a gated reference voltage.

In some embodiments, the first inverter and the second inverter may be coupled to a pillar connection (pillar connection) extending between the first die and the second die.

In some implementations, the circuit may further include a power gating circuit coupled to the second inverter of the buffer, wherein the power gating circuit is configured to apply a gated reference voltage to the second inverter.

In some embodiments, the first inverter may be associated with an input/output block of the first die and the second inverter may be associated with an input/output block of the second die.

A method of transmitting signals in an integrated circuit device is also described. The method may include providing a first die, stacking a second die to the first die, and transferring data between the first die and the second die through a buffer, wherein a first inverter of the buffer is on the first die and a second inverter of the buffer is on the second die.

In some embodiments, the method may further include configuring the first inverter to receive a reference voltage, and configuring the second inverter to receive a gated reference voltage based on the reference voltage.

In some embodiments, the method may further include implementing a third inverter on the second die, wherein the third inverter is configured to receive the reference voltage.

In some embodiments, the method may further include stacking a third die on the second die, wherein the third inverter is configured to transmit data from the first die to the third die.

In some embodiments, the method may further include configuring an interconnect unit of the second die to receive a second gated reference voltage.

In some embodiments, configuring the interconnect unit may include configuring a selection circuit having a selection input coupled to receive a control signal from a memory unit configured to receive a second gated reference voltage.

In some embodiments, the first inverter may comprise a tri-state inverter and may be configured to receive a tri-state signal.

In some embodiments, the method may further include coupling the first inverter and the second inverter to a pillar connection extending between the first die and the second die.

In some implementations, the method can further include coupling a power gating circuit to a second inverter of the buffer, wherein the power gating circuit is configured to apply a gating reference signal to the second inverter.

In some embodiments, the first inverter may be associated with an input/output block of the first die and the second inverter may be associated with an input/output block of the second die.

Brief Description of Drawings

FIG. 1 is a block diagram of an exemplary stacked integrated circuit device;

FIG. 2 is a cross-sectional view of a portion of an exemplary stacked integrated circuit device (e.g., the integrated circuit device of FIG. 1);

FIG. 3 is a block diagram of a portion of an integrated circuit having a region that receives a power gated reference voltage;

FIG. 4 is a block diagram of a portion of an integrated circuit having a circuit block that receives a power gated reference voltage;

FIG. 5 is a block diagram of a portion of a circuit for transmitting signals between dies of an integrated circuit device;

FIG. 6 is another block diagram of a portion of a circuit for transmitting signals between dies of an integrated circuit device;

FIG. 7 is a block diagram of an exemplary gating circuit that may be implemented in the circuits of FIGS. 5 and 6;

FIG. 8 is a timing diagram illustrating the operation of the gate control circuit of FIG. 7;

FIG. 9 is a flow chart illustrating a method of transmitting signals in an integrated circuit device; .

FIG. 10 is a block diagram of a programmable logic device that may implement the circuits and methods for transmitting signals in an integrated circuit device; and

fig. 11 is a block diagram of a configurable logic cell of the programmable logic device of fig. 10.

Detailed Description

Implementing multiple integrated circuit dies in an integrated circuit package may increase density and improve performance. However, a portion of the die that encapsulates the integrated circuit device may be defective or may be unused. For example, in active-on-active (AOA) devices, the stacking of the dies may bring the circuitry in the Integrated Circuit (IC) package closer together, thereby improving performance. Stacked die used in integrated circuit packages may be formed by stacking wafers (wafers), referred to as wafer-to-wafer bonding, and then dicing the stacked wafers to form individual stacked die implemented in the integrated circuit package. However, during the manufacturing process, it is not possible to stack "known good die" in a stacked die architecture, since the wafer-to-wafer stacking is performed before dicing the stacked wafers. That is, there may be defects between dies in the die stack or within the dies themselves that cannot be identified until after the stacked wafers are diced. Therefore, defect tolerance and redundancy are beneficial. The circuits and methods set forth below for transmitting data in an integrated circuit device are advantageous for redundancy schemes implemented in stacked-die architectures.

The circuits and methods described below enable power gating to turn off current on a defective die or portion of a defective die in a multi-die integrated circuit device, such as a stacked Field Programmable Gate Array (FPGA) subsystem formed using wafer-to-wafer bonding. According to some embodiments, the circuits and methods provide a 3D stacked die with a dual power gated supply, e.g., a higher voltage (e.g., VGG) for the memory device and a lower voltage (e.g., VCCINT) for the circuit, such as logic circuits that do not require a higher voltage. Power gating reduces static leakage of unused chips. However, since in some embodiments the powered and non-powered gating regions may coexist on the same die, there may be a parasitic current path between the non-gated and gated regions. The use of isolation cells between the non-gated and gated regions can prevent these parasitic current paths. A circuit and method of separating inverters of a buffer provides isolation, where a first inverter is on an un-gated power supply region of the circuit and a second inverter is on a gated power supply that shares power with the gated region.

According to some embodiments, the inverters of the driver may be separated across the two dies, wherein one of the inverters (e.g., the second inverter of the buffer) may be provided with a gated reference voltage. Thus, the power-gated inverter acts as an isolation unit between the gated and non-gated power supplies and isolates the drivers in the active die from the source/drain loads in the defective die. The circuit arrangement has no effect on area, but improves the implementation of die-to-die connections. That is, because two inverters of a buffer are required on the same die of a conventional device, the inverters of the buffer are divided between the two dies, where the second inverter of the die of the conventional buffer arrangement would occupy the inverter area moved to the next die. Thus, there is no area effect because the inverter used has actually moved to another die.

While the specification concludes with claims defining the features of one or more embodiments of the invention that are regarded as novel, it is believed that the circuits and methods will be better understood from a consideration of the following description in conjunction with the figures. While various circuits and methods are disclosed, it is to be understood that these are merely exemplary of the inventive arrangements, which can be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed manner. Further, the terms and phrases used herein are not intended to be limiting but rather to provide an understandable description of the circuit and method.

Turning first to fig. 1, a block diagram of an exemplary stacked integrated circuit device 100 is shown. More specifically, the substrate 102 (shown here as a package substrate by way of example) is configured to receive a plurality of dies electrically connected by an interconnect unit, as will be described in more detail in fig. 2. Alternatively, the substrate may include an interposer located on a package substrate, or any other means for receiving a die of an integrated circuit device. As shown in fig. 1, the first die stack includes a first substrate 106 having a corresponding interconnect layer 108, where the interconnect layer 108 includes interconnect units capable of routing signals to a package substrate. The interconnect units may include pads, hybrid interconnect technologies, or any other conductive units for routing signals to and from the die. The second substrate 110 has a corresponding interconnect layer 112, the interconnect layer 112 including interconnect cells capable of routing signals. The third substrate 114 has a corresponding interconnect layer 116, which interconnect layer 116 also includes interconnect cells capable of routing signals. A package lid 118 may be included to cover the substrate 114 or to package the plurality of dies. The substrate and interconnect layer pairs (106 and 108, 110 and 112, and 114 and 116) as shown form 3 dies and are configured to route signals between the dies, as will be described in more detail below with reference to fig. 2. It should be understood that the arrangement of fig. 1 is intended to show, by way of example, a general arrangement of stacked dies, wherein a particular arrangement of dies may have different configurations of face-to-face dies (also referred to as work-face-to-face dies) and back-to-back dies (wherein the face represents the metal layer side of the back-end-of-line (BEOL) and the back represents the substrate). Depending on the configuration of the die, the interconnect unit may include TSV or BEOL metal layers of the die. For face-to-back bonding, the interconnections between the dies are implemented in the substrate (i.e., where the TSVs are located). According to an example, the interconnect layer 112 may include a metal layer (i.e., on one side) of the substrate 110 (i.e., the back side), wherein the interconnect layer 112 and the die 110 together constitute one die layer. The interconnections from one die to another or between the substrate package and the die may include metal layers or TSVs, depending on the orientation of the die. It should be noted that stacked IC devices may include different types of TSVs: for example, through-first vias TSV fabricated before devices (such as transistors, capacitors, or resistors) generated during the previous process; a middle via TSV fabricated after the transistor, capacitor or resistor device is patterned but before a metal layer formed in a back-end process; and a final via TSV fabricated during or after a back-end process. The middle via TSV is currently a common option for advanced 3D integrated circuits and interposer stacks.

The integrated circuit device may include additional die sets, including a second set of dies 120, which may be implemented in a similar manner as the die set 104, with the substrate 102 enabling signal communication between the first set of dies and the second set of dies. Although the exemplary stacked integrated circuit device 100 is shown by way of example, it should be understood that other arrangements of die may be implanted, including die positioned adjacent to each other at the level of the package substrate. Further, while examples of the circuits and methods are described with reference to stacked dies of an integrated circuit device, it should be understood that the circuits and methods may be implemented in dies that are adjacent to each other in the horizontal plane of the package substrate, where the dies of the first set of dies 104 may communicate with the dies of the second set of dies 120. According to one embodiment, inverters of a buffer capable of transferring signals between dies are separated between dies, wherein a first inverter of the buffer is located on a first side of a boundary between the first die and the second die and a second inverter of the buffer is located on a second side of the boundary between the first die and the second die. The boundary may be, for example, the top and bottom surfaces of two stacked dies. Alternatively, for an unstacked die arrangement (e.g., a die located on a level of a substrate or interposer, or a die stacked with a different set of dies on a level), the boundary may include, for example, one of the top or bottom of one of the dies. For example, the circuit and method of separating the inverters of the buffer between two dies may include an inverter of the buffer in a die of one die stack and another inverter of the buffer in a die of another die stack, wherein the boundary includes at least one of a top or a bottom of one of the dies.

Turning now to fig. 2, a cross-sectional view of a portion of an exemplary stacked integrated circuit device 200 is shown, which may be a cross-section of the integrated circuit device of fig. 1, but with 5 dies. Stacked integrated circuit device 200 includes a plurality of dies, here illustrated as die 1-die 5. Each die may typically include the same type of elements, such as active elements (active elements), metal traces, and vias formed in silicon, with the same reference numbers in each die. For example, each die may include a substrate 202 having active cells 204, shown here as transistors by way of example, that include a source 206 and a drain 208 in a well region 209, and a gate region 210.

The active cells of the substrate of the die are connected to each other or to cells of other dies by interconnect cells, wherein the active cells may comprise metal traces and vias of metal layers separated by non-conductive layers, wherein the vias connect through portions of the metal layers of the non-conductive layers. More specifically, as shown, the interconnect cells 212 are coupled together by vias 214. A via 216 extending through the substrate, commonly referred to as a through-silicon-via (TSV), extends from a contact unit 218 on the backside of the substrate, which contact unit 218 may be coupled to a contact unit 220, which contact unit 220 is capable of connecting to a contact pad 222 extending through an insulating layer 224 to provide an external connection. Other contact units may also be implemented to provide electrical connections between the dies. For example, a first contact unit 226 of a first die may be electrically coupled to a second contact unit 228 of a second die, where the contact units 226 and 228 may be part of a hybrid contact unit 230. The example of fig. 2 is provided to illustrate an example of a device in which the circuits of fig. 3 and 4, as described in more detail below, may be implemented.

The circuit of fig. 2 is shown by way of example and may include any number of dies, which may be implemented in any orientation. While a face-to-face arrangement of the dies is shown between die 1 and die 2 and a face-to-back arrangement is shown in the connection of the other die, it is understood that other orientations of the dies may be implemented. Some or all of the dies may be the same type of device, such as a Programmable Logic Device (PLD), or may have specific functions, such as memory or logic, in different dies.

Turning now to fig. 3, a block diagram of a portion 300 of an integrated circuit is shown with regions receiving power-gated reference voltages. The circuit and method for transmitting signals may be implemented in any type of integrated circuit device. However, the circuit and method are beneficial in integrated circuit devices having circuit cells that are dedicated to certain functions and duplicated, such as in the PLDs shown and described by way of example in fig. 10 and 11 below.

According to the example of fig. 3, the circuit may be divided into 4 regions, including a first circuit region 302 with corresponding power gating circuitry 303, a second circuit region 304 with corresponding power gating circuitry 305, a third circuit region 306 with corresponding power gating circuitry 307, and a second circuit region 308 with corresponding power gating circuitry 309. For each circuit region, a first reference voltage (first Vref) is coupled to a first input 310 and an input 312 of the respective power gating circuit, the gated output of which is coupled to a second input 314 of the circuit region. As will be described in greater detail below, the gated reference voltage corresponding to the first reference voltage is coupled to the circuit region in response to corresponding control signals (designated control 1-control 4 in fig. 3). A second reference voltage (second Vref) is coupled to input 316.

Although the second reference voltage is not coupled to the respective power gating circuit, the second power gating circuit may be implemented between the second reference voltage and the input 316. According to one embodiment, the first reference voltage may be a lower voltage (e.g., VCCINT) and the second reference voltage may be a higher voltage (e.g., VGG). Although 4 regions are shown by way of example, it should be understood that any number of regions may be implemented and that any number of gated and ungated reference voltages may be used. Further, a single reference voltage or more than two reference voltages may be implemented.

Turning now to fig. 4, a block diagram of a portion 400 of an integrated circuit arrangement is shown with a circuit block receiving a power gated reference voltage. The circuit arrangement of fig. 4 comprises configurable logic Cells (CLE)402 with corresponding power gating circuitry 403, blocks 404 of interconnected cells with corresponding power gating circuitry 405, and Configuration Random Access Memory (CRAM)406 with corresponding power gating circuitry 407. Details of the CLE, the interconnecting cell blocks and the CRAM will be described in more detail with reference to FIGS. 10 and 11.

According to the embodiment of fig. 4, some CLEs 402 are configured to receive a first reference voltage (e.g., VCCINT) at input 410, while other CLEs may be configured to receive a gated first reference voltage at input 410. More specifically, for gating the first reference voltage, the first reference voltage is coupled to an input 412 of the power gating circuit 403, which is also coupled to receive a CLE gating control signal (e.g., cc1.. CCn) at a control input 414. Although the CLE 402 receives only one gated or non-gated reference voltage, it should be understood that CLEs can be configured to each receive gated and non-gated voltages, as well as more than one gated and non-gated voltage.

The circuit arrangement of fig. 4 further comprises a plurality of interconnected cell blocks 404, shown by way of example as each receiving a first reference voltage and gating the first reference voltage. More specifically, a first reference voltage is provided to an input 420 of interconnect block 404. The corresponding power gating circuit is also configured for each of the interconnected cell blocks 404 to receive the reference voltage at the input 422 and to generate a gated reference voltage coupled to the input 424 of the interconnected cell blocks 404 in response to a corresponding control interconnect signal (CI1-CIn) coupled to the control input 426.

The circuit arrangement of fig. 4 further comprises a plurality of CRAM blocks 406, shown by way of example as each receiving a second reference Voltage (VGG) and a gated second reference voltage (gated VGG). More specifically, a corresponding power gating circuit 407 is configured for each CRAM block 406 to receive the second reference voltage (e.g., VGG) at input 432 and generate a gated second reference voltage coupled to input 430 of CRAM 406 in response to a respective CRAM control signal (CC1-CCn) at control input 434. Although the circuit arrangement of fig. 4 includes 3 types of circuit blocks having different power gating arrangements, it should be understood that the arrangement of fig. 4 is provided as an example and that different types of circuit blocks may be implemented with different power gating configurations.

In an integrated circuit device such as a programmable logic device with a dual voltage supply (e.g., a higher voltage supply (VGG) may be provided for the memory cells while a nominal Voltage (VCCINT) may be provided for the cores), power gating of VCCINT may be beneficial. Power gating of higher voltage VGG may also be beneficial because certain circuits, such as Configuration Random Access Memory (CRAM) cells that receive higher voltages, may have leakage in 7nm technology, which may be up to 15% of the total integrated circuit device power. Thus, as will be described in more detail below, it may be beneficial to gate both voltages on a bad die, not only to save static power, but also to improve yield.

It should be noted that although gated power is beneficial, some circuits require the use of ungated power to service normally open modules. For example, in 3D integrated circuits, such as the integrated circuit devices of fig. 1 and 2, when the power supply of one of the defective chips is power gated, it is still necessary for the active signal to propagate through the defective power gated die, which may have a power-gated load on the defective die (where the signal between the dies is typically referred to as a z-signal (i.e., extending in the z-direction between stacked dies)). Transferring signals to a defective die may create parasitic leakage paths from the ungated power supply to the gated power supply and also result in indeterminate floating capacitances on the power gated die due to parasitic leakage on the paths, which can have a significant impact on performance. Therefore, isolation circuitry is necessary in conventional devices, which is often expensive and undesirable in FPGA interconnect blocks where area is limited. The isolation circuit arrangement of fig. 5 and 6 overcomes the drawbacks of conventional isolation circuits by separating the inverters of the buffer between 2 dies, thus eliminating the need for additional circuitry.

Active z-signals (i.e., signals in a vertical direction between two stacked dies) can be coupled to different types of loads, including loads on adjacent dies and loads across multiple dies. The circuits and methods set forth in fig. 5 and 6 overcome the problems of conventional devices by dividing the dual inverter of the buffer (i.e., driver) of the die interconnect unit into two inverting stages, where the first inverter is located on one die that includes the signal driver and the second inverter is located on the second die that is the load die. The first inverter may be implemented using a non-power gated supply to enable signal transmission across multiple dies, while the second inverter may be on the power gated supply. The second inverter receiving the power-gated supply serves as an isolation unit. Unlike conventional isolation cells, which require unnecessary circuitry, the circuit and method of separating drivers provides limited load capacitance and improves the performance of shared connections between dies, such as shared z-connections between dies.

That is, the circuit and method provide an inverter connected to a power gated supply, can be implemented without additional circuit footprint due to the separation technique, and improves the performance of non-power gated solutions. While the circuit and method also achieve full power gating of the VGG (which helps improve product yield and save additional power), the strategy of splitting inverters across die can also be used regardless of power gating to improve interconnect performance on 3D integrated circuits.

Turning now to fig. 5, a block diagram of a portion of a circuit 500 for transmitting signals between stacked dies of an integrated circuit device is shown. The circuit of fig. 5 includes a unit that is part of 2 dies, and more specifically, a unit that includes buffers associated with drivers on the first die 501 and the second die 502. The circuit 500 may comprise a first selection circuit 503, here shown as a multiplexer adapted to receive input signals (input _1 and input _2) at a first input 504 and a second input 506, by way of example, wherein selected values (of the input _1 and input _2 signals) can be generated at an output 510 provided at the inputs and in response to a control signal generated by a storage unit 509. It should be noted that memory cell 509 may be part of a CRAM and receive a reference voltage (e.g., VGG), as described above with reference to fig. 4. It should be noted that although the selection circuit 503 is configured to receive a selection signal at input 508 for selecting an input of the selection circuit, and the selection circuit 530 is configured to receive a selection signal at input 537 through a memory cell receiving a VGG reference voltage, it should be understood that a memory cell may receive a different reference voltage that is not gated. That is, selection circuits 503 and 530 are controlled by select input signals that are always on to enable signal transfer between dies, e.g., die 1 and die 3, even if, for example, die 2 or a portion of die 2 is defective. Although the control signal is provided to the control input of the selection circuit via the memory cell, it should be understood that the control signal may be provided by other circuit cells that are capable of rendering the selection circuits 503 and 530 conductive at all times.

The output signal generated at the output 510 is coupled to a first inverter 512 of a buffer 513, the output of the first inverter 512 being coupled to a second inverter 514 through an interconnection unit 516. The first inverter 512 and the second inverter 514 are part of a buffer that is divided between the first die and the second die. The interconnect unit 516 may be any type of contact unit capable of transmitting signals between a first inverter on a first die and a second inverter on a second die. For example, the interconnect cells 516 may include cells of two dies, such as cells of contact pads, TSVs, metal traces, or hybrid bonding cells.

The second inverter 514 may be coupled to the selection circuit 518 at a first input 520 of the plurality of inputs. In response to the input at select input 523, the output signal of select circuit 518 is generated at output 522. According to some embodiments, select input 523 receives the outputs of storage units 524 and 526. Memory cells 524 and 526 may be part of a CRAM that receives a gated reference voltage (e.g., a gated VGG voltage). By providing gating of the second inverter 514, leakage current/parasitic current from the not-gated to the gated circuit region may be reduced. There are many leakage paths in the circuitry of an integrated circuit device. For example, a leakage path may exist in the drive path of die 2, such as in the transistors of selection circuit 518 coupled to input 520. More specifically, there may be leakage current in the transmission gate including the P-channel transistor coupled to input 520, where current may leak from the source of the P-channel transistor to the body of the transistor. There may also be leakage in the path between input 520 and input 521 that includes the P-channel transistor. By providing isolation between the interconnect cells 516 transmitting signals to the inverters 514 using the gated reference voltage to the inverters 514, current leakage in die 2, such as in the selection circuit 518, may be reduced. It should be noted that current leakage is generally between the non-gated and gated regions. In addition to current leakage, the actively-turned-on paths result in current paths from the non-gated to the gated regions, where the isolation provided by the gated supply will turn off these current paths.

In order to be able to transmit the signal from the inverter 512 to other parts of the integrated circuit device (including other parts of the die 2) or to the die 3 of the stacked die arrangement of the integrated circuit device via the interconnect unit 516, additional units are provided in the die 2. For example, an inverter 528 that receives a reference voltage (e.g., VCCINT) instead of a gated reference voltage (e.g., gated VCCINT) is provided to ensure that signals provided to die 2 through interconnect 516 can be provided to other portions of die 2 and die 3. Inverter 528 receives the signal generated at interconnect element 516 and provides the signal to other circuit elements for routing the signal. For example, other circuit elements may include a multiplexer 530 having an input 532 and an input 534 configured to receive a signal that may be selected as a signal provided to an output 536 in response to a signal received at a select input 537, which may be received from a memory element, which may be a CRAM memory element 538 that receives a reference signal. Output 536 is coupled to inverter 540, and inverter 540 receives reference voltage Vref and provides the output to other portions of the integrated circuit device, such as die 2 or die 3, through interconnect unit 542 (which enables transmission of signals to die 3). By providing inverter 528 and other means for enabling signals to be transmitted from interconnect means 516 to other parts of the integrated circuit, signals from die 1 may be transmitted to other parts of the integrated circuit, which allows inverter 514 to be controlled by a gated reference voltage to avoid defective parts of the integrated circuit and to prevent current leakage in devices that may not be used, such as selection circuit 518.

The circuit and method provide the benefit of the presence of shorts, such as vcint-gnd shorts on a die. If there is no power gating, the die must be discarded. However, by power gating, the short circuit will translate into a virtual vcint-gnd short circuit, and thus it is used to avoid a vcint-gnd short circuit. Vccint is a global power supply that may be common to all die in the stack, while virtual Vccint is the local power supply for that particular die. Any short-circuiting of the local power supply can be isolated from the global external power supply. Yield is improved by avoiding the use of defective die. For example, if there is a stack of 3 dies and there is a vcint-gnd short on one chip, it is necessary to discard devices with multiple dies, one of which is defective and has no power gating. With power gating, the stack of 2 dies can still function properly.

Turning now to fig. 6, another block diagram of a portion of a circuit 600 for transmitting signals between stacked dies of an integrated circuit device is shown. The circuit of figure 6 is similar to that of figure 5 except that a stud connection 603 extends between the dies 601 and 602 and a tri-state inverter is adapted to provide and receive tri-state signals to and from the stud connection. As shown in fig. 6, the inverter 604 of the buffer 605 is configured to receive an input signal and is controlled by a tri-state signal so that the output of the tri-state inverter may be floating if no signal is sent to the column connection. The output of tri-state inverter 604 is coupled to post connection 603 and post connection 603 is also coupled to inverter 606 to receive a signal from post connection 603. Inverter 606 is controlled by a gated reference voltage and, together with inverter 604, forms a buffer divided between die 1 and die 2. The output of inverter 606 is coupled to selection circuit 608 at input 610. A select input of the select circuit 608 is generated at an output 612 in response to a signal received at a control signal input 613. According to some embodiments, the signal provided to the control signal input may come from memory cells 614 and 616, and memory cells 614 and 616 may be CRAM cells that receive a gating voltage (e.g., a gated VGG). Other tri-state inverters, such as tri-state inverter 618, may be coupled to the stud connection 603 to enable data to be transferred from the inverter 604 to other parts of the die or to die 3. Using split inverters with deterministic inverter loading can also better control delay and provide lower delay than non-split solutions, with the strut connection.

Turning now to fig. 7, a block diagram of an exemplary gating circuit 700 that may be implemented in the circuits of fig. 5 and 6 is shown. The gated reference voltage may be generated using a series of transistors coupled between the reference voltage Vref and ground. The p-channel transistor 702 has a source configured to receive a reference voltage and a drain coupled to the drain of the n-channel transistor 704. The first control signal (control _1) is coupled to the gate 706 of the transistor 702 and the second control signal (control _2) is coupled to the gate 708 of the transistor 704. A gated reference voltage (gated Vref) may be generated at a node between the drains of transistors 702 and 704 in response to a control signal. A specific example of generating the gated VGG signal will be described with reference to fig. 8.

Turning now to fig. 8, a timing diagram illustrates the operation of the gate control circuit of fig. 7 in generating a gated VGG signal. For a non-defective die, the control _1 signal remains low to keep the transistor 702 on. The control _2 signal remains high until VGG is turned on and then goes low, allowing the gated VGG signal to follow VGG. For a defective die, the control _2 signal remains high, the hold transistor 704 is turned on, and the gated VGG signal remains low. The control _1 signal follows the VGG signal.

In the case where there is a defective die, control _1 and control _2 are both pulled low. The control _2 signal remains at Vccint and control _1 rises with Vgg. Pull-down circuitry is provided on the gated Vref signal (e.g., the gated VGG signal) during startup to ensure wake-up in a known state. This may be achieved by an N-channel transistor 704 controlled by Vccint. During the start-up sequence, transistor 704 initially remains on. Then, the Vgg pass-gate switch (transistor 704) will remain off or will be on, depending on whether the device is defective or not.

Full VGG gating with isolation as described in fig. 5 and 6 is beneficial in that without these isolated inverters it is not possible to perform VGG power gating because the PMOS transistor in the selection multiplexer will be turned on and there will be a current path if there are no isolated inverters. Furthermore, better yield can be achieved in the event that a short circuit between the gated VGG and ground is overcome.

Turning now to fig. 9, a flow diagram illustrates a method of transferring circuitry in an integrated circuit device; at block 902, a first die, such as die 1 of fig. 5 and 6, is provided. At block 904, a second die is coupled to a first die, such as die 2 of fig. 5 and 6. At block 906, a first inverter of a buffer is provided on a first side of a boundary between the first die and the second die, as described above. At block 908, a second inverter of the buffer is provided on a second side of a boundary between the first die and the second die. For example, the first and second inverters may be inverters 512 and 514 of fig. 5 or inverters 604 and 606 of fig. 6. At block 910, data is transferred between the first die and the second die through a buffer. At block 912, power gating is provided for an inverter, such as a second inverter of the buffer.

According to some embodiments, the second inverter may be configured to receive a gated reference voltage based on a reference voltage, wherein the first inverter is configured to receive the reference voltage. A third inverter may be implemented on the second die, wherein the third inverter is configured to receive a reference voltage. According to some embodiments, the first inverter may comprise a tristate inverter and be configured to receive a tristate signal. For example, as shown in FIG. 6, the use of a tri-state inverter may be advantageous for use with a pillar connection. The power gating circuit may be implemented according to various embodiments, wherein the power gating circuit may be coupled to a first inverter of the buffer, and wherein the power gating circuit is configured to apply a gating reference signal to the first inverter. The second die may also include an interconnect unit configured to receive a second gated reference voltage. The interconnect unit may include a selection circuit having a selection input configured to receive a control signal from the memory unit, the memory unit configured to receive a second gated reference voltage. The first inverter may be associated with an input/output block of the first die and the second inverter is associated with an input/output block of the second die.

The method of fig. 9 may be implemented using the circuits described in fig. 1-8 and 10-11, or using some other suitable circuit. While specific features of the method are described, it will be appreciated that additional features of the method, or additional details related to the features, may be implemented in accordance with the disclosure of fig. 1-9.

Turning now to fig. 10, a block diagram of a programmable logic device is shown. Although the device with programmable resources may be implemented in any type of integrated circuit device, such as an Application Specific Integrated Circuit (ASIC) with programmable resources, other devices include application specific Programmable Logic Devices (PLDs). One type of PLD is a Complex Programmable Logic Device (CPLD). The CPLD includes two or more "function blocks" that are connected together and to input/output (I/O) resources by a matrix of interconnected switches. Each functional block of the CPLD contains two levels and/or structures similar to those used in Programmable Logic Array (PLA) or Programmable Array Logic (PAL) devices. Another type of PLD is a Field Programmable Gate Array (FPGA). In a typical FPGA, an array of Configurable Logic Blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs and programmable routing resources are customized by loading a configuration bitstream (typically from off-chip memory) into configuration memory cells of the FPGA. For both types of programmable logic devices, the function of the device is controlled by configuration data bits of a configuration bitstream (or configuration data bits sent during partial reconfiguration) provided to the device for this purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), non-volatile memory (e.g., flash memory, as in some CPLDs), or any other type of memory cell.

The device of fig. 10 includes an FPGA architecture 1000 having a number of different programmable blocks, including multi-gigabit transceivers (MGTs) 1001, CLBs 1002, random access memory Blocks (BRAMs) 1003, input/output blocks (IOBs) 1004, configuration and clock logic (CONFIG/CLOCKS)1005, digital signal processing blocks (DSPs) 1006, dedicated input/output blocks (I/O)1007 (e.g., configuration ports and clock ports), and other programmable logic 1008 such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. For example, some FPGAs also include dedicated processor blocks (PROC)1010, which may be used to implement software applications.

In some FPGAs, each programmable block includes a programmable interconnect element (INT)1011 having standardized connections with corresponding interconnect elements in each adjacent block. Thus, the programmable interconnect elements together implement the programmable interconnect structure of the illustrated FPGA. The programmable interconnect element 1011 also includes connections to and from programmable logic elements within the same block, as shown in the example included at the top of FIG. 10.

For example, CLB 1002 may include configurable logic Cells (CLE)1012 that may be programmed to implement user logic plus a single programmable interconnect cell 1011. In addition to including one or more programmable interconnect units, the BRAM 1003 may also include a BRAM logic unit (BRL) 1013. The BRAM includes dedicated memory separate from the distributed RAM that configures the logic blocks. Generally, the number of interconnected cells contained in a block (tile) depends on the height of the block. In the illustrated embodiment, one BRAM block has the same height as five CLBs, but other numbers may be used. DSP block 1006 may include DSP logic unit (DSPL)1014 in addition to an appropriate number of programmable interconnect units. In addition to one instance of programmable interconnect element 1011, IOB 1004 may include two instances of input/output logic cell (IOL)1015, for example. The circuits and methods may be implemented using an IOL 1015. The location of the connections of the devices is controlled by configuration data bits of a configuration bitstream provided to the devices for this purpose. The programmable interconnect enables connections including interconnect lines to be used to couple various signals to circuits implemented in programmable logic or other circuits such as BRAMs or processors in response to bits of the configuration bitstream.

In the illustrated embodiment, the column area near the center of the die is used for configuration, clock, and other control logic. Configuration/clock distribution regions 1009 extending from the column are used to distribute the clock and configuration signals across the width of the FPGA. Some FPGAs utilizing the architecture shown in fig. 10 include additional logic blocks that disrupt the conventional columnar structure making up much of the FPGA. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, the processor block PROC1010 shown in fig. 10 spans several columns CLB and BRAM.

It should be noted that FIG. 10 is merely illustrative of an exemplary FPGA architecture. The number of logic blocks in a column, the relative width of the columns, the number and order of columns, the types of logic blocks included in the columns, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top of fig. 10 are purely exemplary. For example, in an actual FPGA, more than one column of adjacent CLBs is typically included anywhere the CLBs appear to facilitate efficient implementation of user logic. Although the embodiment of fig. 10 relates to an integrated circuit having programmable resources, it should be understood that the above described circuits and methods may be implemented in any type of device having a combination of programmable resources and hard blocks.

Turning now to fig. 11, a block diagram of a configurable logic cell of the programmable logic device of fig. 10 is shown. In particular, fig. 11 illustrates, in simplified form, configurable logic cells of the configuration logic block 1002 of fig. 10 as an example of programmable logic. In the embodiment of FIG. 11, slice M1101 includes four look-up tables (LUTM)1101A-1101D, each driven by six LUT data inputs A1-A6, B1-B6, C1-C6, and D1-D6, each providing two LUT output signals O5 and O6. The O6 outputs from LUTs 1101A-1101D drive slice outputs A-D, respectively. The LUT data input signals are provided by the FPGA interconnect fabric via input multiplexers, which may be implemented by programmable interconnect unit 1111, and the LUT output signals are also provided to the interconnect fabric. The slice M further includes: the output selection multiplexers 1111A-1111D of the drive output ends AMUX-DMUX; multiplexers 1112A-1112D driving the data inputs of memory cells 1102A-1102D; combined multiplexers 1116, 1118, and 1119; bounce multiplexer circuit 1122-1123; a circuit represented by inverter 1105 and multiplexer 1106 (which together provide optional inversion on the input clock path); and carry logic with multiplexers 1114A-1114D, 1115A-1115D, 1120-1121 and XOR gates 1113A-1113D. All of these units are coupled together as shown in fig. 11. For the case where the select input is not shown in the multiplexer shown in FIG. 11, the select input is controlled by the configuration memory cell. That is, the configuration bits of the configuration bit stream stored in the configuration memory cells are coupled to the select inputs of the multiplexers to select the correct inputs of the multiplexers. These well-known configuration memory cells are omitted from FIG. 11 and from other selected figures herein for clarity.

In the illustrated embodiment, each memory cell 1102A-1102D can be programmed to function as a synchronous or asynchronous flip-flop or latch. The selection between synchronous and asynchronous functions for all four memory cells in a slice is made by programming the synchronous/asynchronous selection circuit 1103. The REV input provides a reset function when the memory cell is programmed such that the S/R (set/reset) input signal provides a set function. The REV input provides a set function when the memory cell is programmed so that the S/R input signal provides a reset function. The memory cells 1102A-1102D are clocked by a clock signal CK, which may be provided, for example, by a global clock network or interconnect structure. Such programmable memory cells are well known in the field of FPGA design. Each memory cell 1102A-1102D provides a registered output signal AQ-DQ to the interconnect fabric. Since each LUT 1101A-1101D provides two output signals O5 and O6, the LUTs may be configured as two 5-input LUTs having five shared input signals (IN1-IN5), or one 6-input LUT having input signals IN1-IN 6.

In the implementation of FIG. 11, each of the LUTMs 1101A-1101D may function in any of several modes. IN the look-up table mode, each LUT has six data input signals IN1-IN6 that are provided by the FPGA interconnect fabric through input multiplexers. One of the 64 data values is programmably selected from the configuration memory cells based on the value of the signals IN1-IN 6. In RAM mode, each LUT functions as a single 64-bit RAM or two 32-bit RAMs with shared addressing. The RAM write data is supplied to either a 64-bit RAM through input terminal DI1 (through multiplexers 1117A-1117C for LUTs 1101A-1101C), or to two 32-bit RAMs through inputs DI1 and DI 2. The RAM write operation in the LUT RAM is controlled by a clock signal CK from the multiplexer 1106 and a write enable signal WEN from the multiplexer 1107, and the multiplexer 1107 can selectively pass either the clock enable signal CE or the write enable signal WE. In shift register mode, each LUT functions as two 16-bit shift registers, or two 16-bit shift registers are coupled in series to create a single 32-bit shift register. The shifted-in signal is provided through one or both of the inputs DI1 and DI 2. The 16 bit and 32 bit shifted out signals may be provided through the LUT output, and the 32 bit shifted out signal may also be provided more directly through the LUT output MC 31. The 32-bit shift-out signal MC31 of LUT 1101A may also be provided to the general interconnect structure for the shift register chain through output select multiplexer 1111D and CLE output DMUX. Thus, the circuits and methods set forth above may be implemented in devices such as the devices of fig. 10 and 11 or in any other suitable device.

It will thus be appreciated that a new circuit and method for transmitting signals in an integrated circuit device has been described. It will be appreciated by those skilled in the art that there are numerous alternatives and equivalents to the disclosed invention. Accordingly, the invention is not to be limited by the foregoing embodiments, but only by the following claims.