阅读说明：本技术 一种基于wqe反压的qp的流控方法 (QP flow control method based on WQE back pressure ) 是由 陈昌明 陈绪金 李志宏 于 2021-06-25 设计创作，主要内容包括：本发明涉及流量控制方法相关领域,具体为一种基于WQE反压的QP的流控方法,包括计时器、QP仲裁模块、QP管理模块、WQE-FIFO储存器、包发送模块、QP寄存器模块、QP2受控寄存器、QP3正常寄存器、SQ2基地址寄存器和SQ3基地址寄存器,本发明通过计时器和QP仲裁模块的配合来精确控制调度时间,从而控制WQE中数据包的发送间隔,实现基于QP流量的精确控制；通过WEQ-FIFO储存器的自查,将QP2受控寄存器的所有WQE从FIFO中清除,保留QP3正常寄存器中非受控QP的WQE,使非受控QP的操作不受影响；将QP2受控寄存器当前执行WQE的指针回写对应的QP寄存器的WQE当前指针寄存器中,进行反压操作,从而使得该WQE可以被不断的重复调用,直到按照流控的要求完成数据发送为止,实现基于WQE反压的流控。(The invention relates to the related field of flow control methods, in particular to a flow control method of QP based on WQE back pressure, which comprises a timer, a QP arbitration module, a QP management module, a WQE _ FIFO storage, a packet sending module, a QP register module, a QP2 controlled register, a QP3 normal register, an SQ2 base address register and an SQ3 base address register, wherein the invention accurately controls the scheduling time by matching the timer and the QP arbitration module, thereby controlling the sending interval of data packets in WQE and realizing accurate control based on QP flow; through self-checking of WEQ _ FIFO storage, all WQEs of the QP2 controlled register are cleared from the FIFO, and WQEs of uncontrolled QP in a QP3 normal register are reserved, so that the operation of the uncontrolled QP is not influenced; and writing the pointer of the currently executed WQE of the QP2 controlled register into the WQE current pointer register of the corresponding QP register, and performing backpressure operation, so that the WQE can be continuously and repeatedly called until data transmission is completed according to the requirement of flow control, and flow control based on the WQE backpressure is realized.)

1. A flow control method of QP based on WQE back pressure comprises a timer (1), a QP arbitration module (2), a QP management module (3), a WQE _ FIFO storage (4), a packet sending module (5), a QP register module (6), a QP2 controlled register (7), a QP3 normal register (8), an SQ2 base address register (9) and an SQ3 base address register (10), and the flow control method comprises the following steps:

step 1, selecting a QP according to a QP arbitration module (2), reading the QP information from a QP register (6) by the QP management module (3) according to the selected result, reading a WQE to be executed from a corresponding SQ2 base address register (9), and writing the WQE into a WQE _ FIFO storage (4);

step 2, a packet sending module (5) reads a WQE2_1 in an SQ2 base address register (9) from a WQE _ FIFO memory (4), and calculates the total number n of data packets needing to be sent separately according to the data length specified in the WQE2_ 1;

step 3, the packet sending module (5) calculates the number m of the data packets sent this time according to the preset flow of the QP2 controlled register (7), sends the m data packets out, and triggers the flow control mark by the packet sending module (5);

step 4, the flow control mark in the step 3 is sent to a WQE _ FIFO storage (4), the received WQE _ FIFO storage (4) of the flow control mark clears all WQEs 2_1 and WQEs 2_2 of a QP2 controlled register (7) through self-checking, and meanwhile, the WQEs of a QP3 normal register (8) are set at the top according to the original sequence;

step 5, after the flow control flag in the step 3 is sent to the QP management module (3), the QP management module (3) writes the packet count value m back to the WQE current pointer register of the QP2 controlled register (7) for back pressure;

step 6, after the flow control flag in the step 3 is sent to the timer (1), the timer (1) calculates the time interval for sending m data packets at intervals according to the preset flow of the QP2 controlled register (7), and performs timing;

step 7, after the timer (1) starts to count in the step 6, the packet sending module (5) continues to read WQE3_1 and WQE3_2 to execute the operation of a QP3 normal register (8);

step 8, after the timer (1) finishes timing in step 6, the QP arbitration module (2) reselects the QP2 controlled register (7), and then the QP management module (3) reads out the WQE2_1 again and writes the read WQE2_1 into the WQE _ FIFO memory (4);

step 9, a packet sending module (5) reads the WQE2_1 in the WQE _ FIFO storage (4) in the step 8, sends m data packets and triggers a flow control mark again;

and step 10, repeating the operations from the step 3 to the step 9, scheduling WQE2_1 at equal intervals and sending m data packets each time until all n data packets are sent, and clearing a WQE packet counting register of a QP2 controlled register (7).

2. The flow control method for QP based on WQE back pressure as claimed in claim 1, wherein: the maximum data length of the data packet in the step 2 is 4096 bytes.

3. The flow control method for QP based on WQE back pressure as claimed in claim 1, wherein: the QP2 controlled register (7) needs the Send tasks WQE2_1, WQE2_2 and WQE2_3 to be executed, and the QP3 normal register (8) needs the Send tasks WQE2_1 and WQE2_2 to be executed.

4. The flow control method for QP based on WQE back pressure as claimed in claim 1, wherein: the First packet of the m data packets sent in the step 3 is marked as First, the subsequent m-1 packets are marked as Middle, the m data packets sent in the step 9 are all marked as Middle, and the Last data packet sent in the step 10 is marked as Last.

Technical Field

The invention relates to the field of flow control methods, in particular to a QP flow control method based on WQE back pressure.

Background

With the maturation of the technology of RoCEv2(RDMA over Converged Ethernet v2), RDMA can be deployed on the existing network facilities of a data center, and RoCEv2 is deployed in a large-scale data center, and the problem to be faced first is how to ensure reliable transmission of RDMA. Once packet loss occurs, the sending rate is generally exponentially slowed down punishably, and the dropped data packet is retransmitted, so that the user feels sudden performance degradation. The flow control can effectively reduce the packet loss probability and ensure the reliable transmission.

Therefore, in order to exert the real performance of RDMA and break through the network performance bottleneck of a large-scale distributed system of a data center, a set of lossless network environment without packet loss is built for RDMA, and the key point of realizing the packet loss prevention is to solve the network congestion. Flow control is used to prevent frame dropping in the event of port blocking.

The existing flow control method is to place a buffer at the sending end of each controlled QP, buffer the data packet to be sent in the buffer, and then send the data according to the flow configuration of each QP, thereby implementing flow control based on QP. However, this method has some disadvantages, such as: a data packet buffer is added at each controlled QP sending end, so that extra sending delay is increased, extra buffer management and scheduling logic are added, the negative complexity of the system is increased, the consumption of the memory is increased, and the cost is also increased; due to the limitation of the size of the cache region, the number of the controlled QPs is limited, and the method cannot be used in the application with large number of the controlled QPs; in the RDMA data transmission, the number of QPs theoretically supported is 24 times of 2, and in actual use, the number of QPs is usually at a megalevel or more, so that the method cannot become a general solution based on QP stream control in the application of RDMA communication. Aiming at some problems, a QP flow control method based on WQE back pressure is designed.

Disclosure of Invention

The invention aims to provide a QP flow control method based on WQE back pressure, so as to solve the problems in the background technology.

In order to achieve the purpose, the invention provides the following technical scheme: a flow control method of QP based on WQE back pressure comprises a timer, a QP arbitration module, a QP management module, a WQE _ FIFO storage, a packet sending module, a QP register module, a QP2 controlled register, a QP3 normal register, an SQ2 base address register and an SQ3 base address register, and the flow control method comprises the following steps:

step 1, selecting a QP according to a QP arbitration module, reading the QP information from a QP register by the QP management module according to the selected result, reading a WQE to be executed from a corresponding SQ2 base address register, and writing the WQE into a WQE _ FIFO memory;

step 2, the packet sending module reads WQE2_1 in an SQ2 base address register from the WQE _ FIFO memory, and calculates the total number n of data packets needing to be sent separately according to the data length specified in the WQE2_ 1;

step 3, the packet sending module calculates the number m of the data packets sent this time according to the preset flow of the QP2 controlled register, and sends out the m data packets, and the packet sending module triggers a flow control flag;

step 4, the flow control mark in the step 3 is sent to a WQE _ FIFO memory, the WQE _ FIFO memory of the received flow control mark clears all WQE2_1 and WQE2_2 of a QP2 controlled register through self-checking, and meanwhile, the WQE of a QP3 normal register is set to the top according to the original sequence;

step 5, after the flow control flag in the step 3 is sent to the QP management module, the QP management module writes the packet count value m back to the WQE current pointer register of the QP2 controlled register for back pressure;

step 6, after the flow control flag in the step 3 is sent to the timer, the timer calculates the time interval for sending m data packets at intervals according to the preset flow of the QP2 controlled register, and performs timing;

step 7, after the timer starts to count in step 6, the packet sending module continues to read WQE3_1 and WQE3_2 to execute the operation of the normal QP3 register;

step 8, after the timer finishes timing in step 6, the QP arbitration module reselects the QP2 controlled register, and then the QP management module reads out the WQE2_1 again and writes the read WQE2_1 into the WQE _ FIFO memory;

step 9, the packet sending module reads WQE2_1 in the WQE _ FIFO storage in step 8, sends m data packets, and triggers the flow control flag again;

and step 10, repeating the operations from the step 3 to the step 9, scheduling WQE2_1 at equal intervals and sending m data packets each time until all n data packets are sent, and clearing a WQE packet counting register of a QP2 controlled register.

Preferably, the maximum data length of the data packet in step 2 is 4096 bytes.

Preferably, the QP2 controlled registers need to execute send tasks WQE2_1, WQE2_2 and WQE2_3, and the QP3 normal registers need to execute send tasks WQE2_1 and WQE2_ 2.

Preferably, the First packet of the m data packets sent in step 3 is marked as First, the subsequent m-1 data packets are marked as Middle, all the m data packets sent in step 9 are marked as Middle, and the Last data packet sent in step 10 is marked as Last.

Compared with the prior art, the invention has the beneficial effects that: the invention accurately controls the scheduling time through the cooperation of the timer and the QP arbitration module, thereby controlling the sending interval of the data packet in the WQE and realizing accurate control based on QP flow; through self-checking of WEQ _ FIFO storage, all WQEs of the QP2 controlled register are cleared from the FIFO, and WQEs of uncontrolled QP in a QP3 normal register are reserved, so that the operation of the uncontrolled QP is not influenced; and writing the pointer of the currently executed WQE of the QP2 controlled register into the WQE current pointer register of the corresponding QP register, and performing backpressure operation, so that the WQE can be continuously and repeatedly called until data transmission is completed according to the requirement of flow control, and flow control based on the WQE backpressure is realized.

Drawings

FIG. 1 is a schematic flow chart of the present invention;

FIG. 2 is a flow chart of the operation of each module in step 2 of the present invention;

FIG. 3 is a flowchart illustrating the operation of each module in step 7;

fig. 4 is a diagram illustrating the effect of flow control according to the present invention.

In the figure: 1. a timer; 2. a QP arbitration module; 3. a QP management module; 4. a WQE _ FIFO storage; 5. a packet sending module; 6. a QP register; 7. QP2 control register; 8. QP3 Normal register; 9. SQ2 base address register; 10. SQ3 base address register.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-4, the present invention provides a technical solution: a flow control method of QP based on WQE back pressure comprises a timer 1, a QP arbitration module 2, a QP management module 3, a WQE _ FIFO storage 4, a packet sending module 5, a QP register module 6, a QP2 controlled register 7, a QP3 normal register 8, an SQ2 base address register 9 and an SQ3 base address register 10, and the flow control method comprises the following steps:

step 1, selecting a QP according to the QP arbitration module 2, reading the QP information from a QP register 6by the QP management module 3 according to the selected result, reading a WQE to be executed from a corresponding SQ2 base address register 9, and writing the WQE into a WQE _ FIFO storage 4;

step 2, the packet sending module 5 reads the WQE2_1 in the SQ2 base address register 9 from the WQE _ FIFO memory 4, and calculates the total number n of data packets that need to be sent separately according to the data length specified in the WQE2_1, and the state of each module is shown in fig. 2 at this time;

step 3, the packet sending module 5 calculates the number m of the data packets sent this time according to the preset flow of the QP2 controlled register 7, and sends out the m data packets, and the packet sending module 5 triggers a flow control flag;

step 4, the flow control mark in the step 3 is sent to a WQE _ FIFO memory 4, the WQE _ FIFO memory 4 of the received flow control mark clears all WQEs 2_1 and WQE2_2 of a QP2 controlled register 7 through self-checking, and meanwhile, the WQEs of a QP3 normal register 8 are set to the top according to the original sequence;

step 5, after the flow control flag in step 3 is sent to the QP management module 3, the QP management module 3 writes back the packet count value m to the WQE current pointer register of the QP2 controlled register 7 for back pressure;

step 6, after the flow control flag in the step 3 is sent to the timer 1, the timer 1 calculates the time interval for sending m data packets at intervals according to the preset flow of the QP2 controlled register 7, and performs timing;

step 7, after the timer 1 starts counting in step 6, the packet sending module 5 continues reading WQE3_1 and WQE3_2 to execute the operation of the normal register 8 of QP3, and the status of each module is as shown in fig. 3;

step 8, after the timer 1 finishes timing in step 6, the QP arbitration module reselects the QP2 controlled register 7, and then the QP management module 3 reads out the WQE2_1 again and writes the WQE _ FIFO memory 4;

step 9, the packet sending module 5 reads the WQE2_1 in the WQE _ FIFO memory 4 in step 8, and sends m data packets, and triggers the flow control flag again;

and step 10, repeating the operations from the step 3 to the step 9, scheduling WQE2_1 at equal intervals and sending m data packets each time until all n data packets are sent, and clearing the WQE packet counting register of the QP2 controlled register 7.

Further, the maximum data length of the data packet in step 2 is 4096 bytes.

Further, QP2 control registers 7 need to execute send tasks WQE2_1, WQE2_2, and WQE2_3, QP3 normal registers 8 need to execute send tasks WQE2_1 and WQE2_ 2.

Further, the First packet of the m data packets sent in step 3 is marked as First, the subsequent m-1 data packets are marked as Middle, the m data packets sent in step 9 are all marked as Middle, and the Last data packet sent in step 10 is marked as Last.

Wherein RDMA is set to a Maximum transmission length PMTU (Path Maximum Transfer Unit) of 1024 Bytes; the flow of the QP2 controlled register 7 is set to 10Mb/S, and the data packet length sent by the WQE2_1 is 10 Mbit. Through the above premise assumptions and flow control logic, it can be found that the total number n of packets transmitted per second is 10240 (10Mb/1024Byte), 1024 times per second is set (the timer controls to trigger one transmission operation every 976562.5 ns), the number m of packets transmitted each time is 10, and by accurately controlling the interval time, the flow rate of QP can be accurately controlled, and the control effect is shown in fig. 5.

The invention accurately controls the scheduling time through the cooperation of the timer 1 and the QP arbitration module 2, thereby controlling the sending interval of data packets in the WQE and realizing accurate control based on QP flow; through self-checking of WEQ _ FIFO storage 4, all WQEs of the QP2 controlled register 7 are cleared from the FIFO, and WQEs of uncontrolled QP in the QP3 normal register 8 are reserved, so that the operation of uncontrolled QP is not affected; and writing the pointer of the currently executed WQE of the QP2 controlled register 7 into the WQE current pointer register of the corresponding QP register 6 for back pressure operation, so that the WQE can be continuously and repeatedly called until data transmission is completed according to the requirements of flow control, and flow control based on the WQE back pressure is realized.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.