阅读说明：本技术 控制电路及芯片 (Control circuit and chip ) 是由 施明 张涛 刘融 于 2021-09-29 设计创作，主要内容包括：本申请提出了一种控制电路,包括跨阻放大器和至少一个滤波电路,所述跨阻放大器和所述至少一个滤波电路连接,其中,所述滤波电路包括：信号建立子电路及滤波子电路；所述信号建立子电路用于为所述跨阻放大器提供信号建立通道；所述滤波子电路包括第一切换元件和滤波器,所述第一切换元件用于在信号建立期间,断开所述滤波器与所述跨阻放大器的连接通路；以及在信号建立之后,导通所述滤波器与所述跨阻放大器的连接通路。既实现了跨阻放大器信号的快速建立,又达到了好的滤波效果。(The application provides a control circuit, including transimpedance amplifier and at least one filter circuit, transimpedance amplifier with at least one filter circuit connects, wherein, filter circuit includes: a signal establishing sub-circuit and a filtering sub-circuit; the signal establishing subcircuit is used for providing a signal establishing channel for the trans-impedance amplifier; the filtering sub-circuit comprises a first switching element and a filter, wherein the first switching element is used for disconnecting a connection path of the filter and the trans-impedance amplifier during signal establishment; and after the signal is established, the connection path of the filter and the trans-impedance amplifier is conducted. The method and the device realize the rapid establishment of the trans-impedance amplifier signal and achieve a good filtering effect.)

1. A control circuit, comprising:

the transimpedance amplifier is connected with the at least one filter circuit;

wherein the filter circuit comprises: a signal establishing sub-circuit and a filtering sub-circuit;

the signal establishing subcircuit is used for providing a signal establishing channel for the trans-impedance amplifier;

the filtering sub-circuit comprises a first switching element and a filter,

the first switching element is used for disconnecting the connection path of the filter and the transimpedance amplifier during signal establishment; and after the signal is established, the connection path of the filter and the trans-impedance amplifier is conducted.

2. The circuit of claim 1, wherein the signal establishing sub-circuit comprises: a first end of the first capacitive element is connected with the input end of the transimpedance amplifier, a second end of the first capacitive element is connected with the output end of the transimpedance amplifier, and a capacitance value of the first capacitive element is smaller than a capacitance threshold value.

3. The circuit of claim 2, wherein the filter comprises:

a second capacitive element having a capacitance value greater than the capacitance threshold.

4. The circuit of claim 3, wherein the capacitance value of the first capacitive element is substantially less than the capacitance value of the second capacitive element.

5. The circuit of any of claims 1-4, wherein the filtering circuit further comprises:

a charging sub-circuit connected to the filtering sub-circuit for charging a filter in the filtering sub-circuit during the signal setup period.

6. The circuit of claim 5, wherein the filtering circuit further comprises: a second switching element connected to the filtering sub-circuit and the charging sub-circuit, respectively, for disconnecting the charging sub-circuit and the filtering sub-circuit after the signal is established.

7. The circuit of claim 5 or 6, wherein the charging circuit comprises:

an operational amplifier;

the non-inverting input end of the operational amplifier is connected with the input end of the transimpedance amplifier, and the inverting input end and the output end of the operational amplifier are connected with the filter sub-circuit.

8. The circuit of any of claims 5-7, wherein the filtering circuit further comprises:

and the offset cancellation sub-circuit is connected with the charging sub-circuit and is used for carrying out offset cancellation on the charging sub-circuit.

9. The circuit of claim 8, wherein the offset cancellation sub-circuit comprises:

a third capacitive element, a third switching element, a fourth switching element, and a fifth switching element;

a first end of the third capacitive element is connected with the transimpedance amplifier through the third switching element, and a second end of the third capacitive element is connected with an input end of the charging sub-circuit and a first end of the fourth switching element respectively;

a second terminal of the fourth switching element is connected with the filter sub-circuit;

a first end of the fifth switching element is connected to the transimpedance amplifier through the third switching element, and a second end of the fifth switching element is connected to the filter sub-circuit.

10. A chip, characterized in that it comprises a control circuit according to any one of claims 1 to 9.

Technical Field

The application relates to the technical field of transimpedance amplifiers, in particular to a control circuit and a chip.

Background

Trans-impedance amplifiers (TIA for short) have the advantage of high bandwidth, and are therefore widely used in optical-electrical transmission communication systems. The transimpedance amplifier can convert the optical signal into an electrical signal and filter the signal to some extent. In order to obtain a good filtering effect and improve the signal-to-noise ratio of an optical signal, a filter circuit is generally formed by a feedback capacitor with a large capacitance value and a feedback resistor with a large resistance value in the related art, however, the problem of too long circuit signal establishing time is brought, and further, the power consumption of a trans-impedance amplifier is large during the signal establishing period.

Disclosure of Invention

The present application is directed to solving, at least to some extent, one of the technical problems in the related art.

An embodiment of a first aspect of the present application provides a control circuit, including:

the transimpedance amplifier is connected with the at least one filter circuit;

wherein the filter circuit comprises: a signal establishing sub-circuit and a filtering sub-circuit;

the signal establishing subcircuit is used for providing a signal establishing channel for the trans-impedance amplifier;

the filtering sub-circuit comprises a first switching element and a filter, wherein the first switching element is used for disconnecting a connection path of the filter and the trans-impedance amplifier during signal establishment; and after the signal is established, the connection path of the filter and the trans-impedance amplifier is conducted.

Optionally, the signal establishing sub-circuit includes: a first end of the first capacitive element is connected with the input end of the transimpedance amplifier, a second end of the first capacitive element is connected with the output end of the transimpedance amplifier, and a capacitance value of the first capacitive element is smaller than a capacitance threshold value.

Optionally, the filter includes:

a second capacitive element having a capacitance value greater than a capacitance threshold.

Optionally, the capacitance value of the first capacitive element is much smaller than the capacitance value of the second capacitive element.

Optionally, the filter circuit further includes:

a charging sub-circuit connected to the filtering sub-circuit for charging a filter in the filtering sub-circuit during the signal setup period.

Optionally, the filter circuit further includes: a second switching element connected to the filtering sub-circuit and the charging sub-circuit, respectively, for disconnecting the charging sub-circuit and the filtering sub-circuit after the signal is established.

Optionally, the charging sub-circuit includes:

an operational amplifier;

the non-inverting input end of the operational amplifier is connected with the input end of the transimpedance amplifier, and the inverting input end and the output end of the operational amplifier are connected with the filter sub-circuit.

Optionally, the filter circuit further includes:

and the offset cancellation sub-circuit is connected with the charging sub-circuit and is used for carrying out offset cancellation on the charging sub-circuit.

Optionally, the offset canceling sub-circuit includes:

a third capacitive element, a third switching element, a fourth switching element, and a fifth switching element;

a first end of the third capacitive element is connected with the transimpedance amplifier through the third switching element, and a second end of the third capacitive element is connected with an input end of the charging sub-circuit and a first end of the fourth switching element respectively;

a second terminal of the fourth switching element is connected with the filter sub-circuit;

a first end of the fifth switching element is connected to the transimpedance amplifier through the third switching element, and a second end of the fifth switching element is connected to the filter sub-circuit.

An embodiment of a second aspect of the present application provides a chip, where the chip includes the control circuit provided in any embodiment of the first aspect of the present application.

A third aspect of the present application provides a wearable device including the control circuit provided in any of the embodiments of the first aspect of the present application.

In some implementations, the wearable device is a wrist-worn device, a head-worn device, or an in-ear device.

According to the control circuit, firstly, a signal is quickly established by the trans-impedance amplifier through the signal establishing sub-circuit; and then after the signal is established, the filter of the filtering sub-circuit is communicated with the trans-impedance amplifier through the first switching element, so that the signal is filtered. Therefore, the rapid establishment of the trans-impedance amplifier signal is realized, the power consumption of the trans-impedance amplifier during the signal establishment is reduced, and a good filtering effect is achieved.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a circuit schematic of a control circuit provided according to an embodiment of the present application;

FIG. 2 is a circuit schematic of a control circuit provided in accordance with another embodiment of the present application;

FIG. 3 is a circuit schematic of a control circuit provided in accordance with another embodiment of the present application;

FIG. 4 is a circuit schematic of an exemplary control circuit of the present application during a signal setup phase;

FIG. 5 is a circuit schematic of a control circuit in a filtering phase according to an embodiment of the present application;

FIG. 6 is a circuit schematic of a control circuit provided in accordance with another embodiment of the present application;

FIG. 7 is a circuit schematic of a control circuit according to another example of the present application during a signal setup phase;

FIG. 8 is a circuit schematic of a control circuit in an offset cancellation phase according to another example of the present application;

fig. 9 is a circuit schematic of a control circuit in a filtering stage according to another example of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

Fig. 1 shows a circuit schematic of a control circuit of an embodiment of the present application. As shown in fig. 1, the control circuit 100 may include a transimpedance amplifier 110 and at least one filter circuit 120.

The structure of the transimpedance amplifier 110 can be determined according to a specific application scenario. For example, the present invention may include only a single input terminal and a single output terminal, or may include a plurality of input terminals and a plurality of output terminals, which is not limited in the present application.

It should be noted that, when the transimpedance amplifier 110 has a plurality of input terminals and a plurality of output terminals, a set of filtering circuits 120 may be provided for a signal path formed by each input terminal and its corresponding output terminal, so as to filter a signal transmitted by each input terminal and its corresponding output terminal.

In the embodiment of the present application, the filter circuit 120 may include a signal establishing sub-circuit 121 and a filter sub-circuit 122. The signal establishing sub-circuit 121 is configured to provide a signal establishing channel for the transimpedance amplifier 110, and the filtering sub-circuit 122 is configured to filter an input signal of the transimpedance amplifier 110 after the signal establishing.

Specifically, the signal establishing sub-circuit 121 may be connected to the input terminal and the output terminal of the transimpedance amplifier 110, respectively, so as to enable the transimpedance amplifier 110 to establish a signal quickly when the circuit generates an input signal. The filter sub-circuit 122 may be connected to the input terminal and the output terminal of the transimpedance amplifier 110, respectively, so as to filter the input signal of the transimpedance amplifier 110 after the signal is established in the transimpedance amplifier 110.

The filter sub-circuit 122 may include a first switching element 1221 and a filter 1222, among other things. The first switching element 1221 is used to disconnect the connection path of the filter 1222 and the transimpedance amplifier 110 during signal setup; and after the signal is established, the connection path of the filter 1222 and the transimpedance amplifier 110 is turned on.

That is, when the input terminal of the transimpedance amplifier 110 receives the electrical signal output by the previous stage circuit, a signal transmission channel is first formed by the signal establishing sub-circuit 121, that is, the input terminal and the output terminal of the transimpedance amplifier 110 are connected by the signal establishing sub-circuit 121, and at this time, the first switching element 1221 controls the connection path between the filter 1222 and the transimpedance amplifier 110 to be disconnected; after the transimpedance amplifier 110 establishes a signal quickly through the signal establishing sub-circuit 121, the first switching element 1221 controls the connection path between the filter 1222 and the transimpedance amplifier 110 to be turned on, and at this time, the input signal of the transimpedance amplifier 110 is filtered by the filter 1222 and then output, so as to achieve a filtering effect.

The first switching element 1221 may be any type of switching element, and the on and off of the first switching element 1121 may be controlled by a first switching control signal. The first switching control signal may be generated by a separate controller, or may be generated by an overall controller of a circuit module in which the transimpedance amplifier is located, which is not limited in this application.

For example, when the transimpedance amplifier 110 is in the signal setup phase, the switching control signal may be at a low level, so that the first switching element 1221 disconnects the connection path of the control filter 1222 and the transimpedance amplifier 110; when the signal of the transimpedance amplifier 110 is completely established, the switching control signal may be at a high level, so that the first switching element 150 controls the connection path between the filter 1222 and the transimpedance amplifier 110 to be conductive, thereby filtering the input signal. It should be noted that the duration for maintaining the low level and the duration for maintaining the high level of the switching control signal may be determined according to the specific circuit structure and performance parameters of the transimpedance amplifier, which is not limited in this application.

In the control circuit provided in the embodiment of the present application, first, the signal establishing sub-circuit 121 enables the transimpedance amplifier 110 to quickly establish a signal; then, after the signal is established, the filter 1222 of the filtering sub-circuit 122 is connected to the transimpedance amplifier 110 through the first switching element 1221, so as to filter the signal. Therefore, the rapid establishment of the trans-impedance amplifier signal is realized, the power consumption of the trans-impedance amplifier during the signal establishment is reduced, and a good filtering effect is achieved.

Fig. 2 is a schematic circuit diagram of a control circuit according to another embodiment of the present application. As shown in fig. 2, based on the embodiment shown in fig. 1, the filter circuit 120 may further include: a charging circuit 123 and a second switching element 124.

The charging sub-circuit 123 may be connected to the filtering sub-circuit 122, and is configured to charge the filter 1222 of the filtering sub-circuit 122 during signal setup.

Specifically, the charging sub-circuit 123 may be connected to a filter element of the filter 1222 to pre-charge the filter element, and the filter element may be a filter capacitor, which is not limited in this application.

Therein, the second switching element 124 may be connected with the filtering sub-circuit 122 and the charging sub-circuit 123, respectively, for disconnecting the charging sub-circuit 123 and the filtering sub-circuit 122 after the signal is established.

In particular, the second switching element 124 may control a connection path of the charging electronic circuit 123 and the filter 1222 of the filter sub-circuit 122. During the period that the transimpedance amplifier 110 establishes the signal through the signal establishing sub-circuit 121, the second switching element 124 controls the connection path of the charging sub-circuit 123 and the filter 1222 to be conductive, and at this time, the filter 1222 is rapidly charged through the charging sub-circuit 123. After the transimpedance amplifier 110 establishes the signal, the second switching element 124 controls the connection path between the charging electronic circuit 123 and the filter 1222 to be disconnected, and the input signal of the transimpedance amplifier 110 is filtered by the filter 1222 of the filter sub-circuit 122.

The second switching element 124 may be any type of switching element, and the on and off of the second switching element 124 may be controlled by the second switching control signal. The second switching control signal may be generated by a separate controller, or may be generated by an overall controller of a circuit module in which the transimpedance amplifier is located, which is not limited in this application.

The control circuit provided by the embodiment of the present application charges the filter 1222 of the filter sub-circuit 122 through the charging sub-circuit 123 during the signal setup period of the transimpedance amplifier 110, so that the filter 1222 can filter the input signal of the transimpedance amplifier 110 immediately after the signal setup, thereby saving the time from the signal setup to the normal operation of the transimpedance amplifier 110.

Fig. 3 shows a circuit schematic of a control circuit according to an embodiment of the present application. As shown in fig. 3, the control circuit is illustrated by taking a trans-impedance amplifier TIA (trans-impedance amplifier) as an example, which has two input terminals and two output terminals. And a filter circuit with the same structure can be respectively arranged between each input end and the corresponding output end, wherein each filter circuit comprises a signal establishing sub-circuit, a filter sub-circuit, a charging sub-circuit and a second switching element.

In one possible implementation of the embodiment of the present application, as shown in fig. 3, the signal establishing sub-circuit may include a first capacitor C1.

The first end of the first capacitor C1 is connected to the input end of the transimpedance amplifier TIA, the second end of the first capacitor C1 is connected to the output end of the transimpedance amplifier TIA, and the capacitance value of the first capacitor C1 is smaller than the capacitance threshold value.

It should be noted that, in the signal setup phase, the signal setup time of the transimpedance amplifier TIA is determined by the first capacitor C1. In order to ensure that the transimpedance amplifier TIA can establish a signal quickly, the capacitance value of the first capacitor C1 should be as small as possible. Therefore, the capacitance threshold value can be set according to the specific structure of the circuit in which the transimpedance amplifier TIA is located, and the capacitance value of the first capacitor C1 is smaller than the capacitance threshold value.

In one possible implementation manner of the embodiment of the present application, as shown in fig. 3, the signal establishing sub-circuit may further include an enable switch fs.

The first end of the enabling switch fs is connected with the input end of the transimpedance amplifier TIA, the second end of the enabling switch fs is connected with the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected with the output end of the transimpedance amplifier TIA.

Specifically, when the circuit where the transimpedance amplifier TIA is located is in a sleep state, the circuit enable signal may be at a low level, and at this time, the first terminal and the second terminal of the enable switch fs are disconnected. When the circuit where the TIA is located starts to work, the circuit enabling signal jumps to a high level, and at the moment, the first end and the second end of the enabling switch fs are closed under the action of the circuit enabling signal.

In one possible implementation manner of the embodiment of the present application, as shown in fig. 3, the filter of the filtering sub-circuit may include a second capacitor C2.

And a first end of the second capacitor C2 is connected with the input end of the transimpedance amplifier TIA, and a second end of the second capacitor C2 is connected with the output end of the transimpedance amplifier TIA. The capacitance value of the second capacitor C2 is greater than the capacitance threshold.

It should be noted that, in order to achieve a good filtering effect, the capacitance value of the second capacitor C2 should be as large as possible. Therefore, the capacitance threshold value can be set according to the specific structure of the circuit in which the transimpedance amplifier TIA is located, and the capacitance value of the second capacitor C2 is made to be larger than the capacitance threshold value.

It is understood that the signal settling time of the transimpedance amplifier TIA is determined by the first capacitor C1. The signal filtering effect of the transimpedance amplifier TIA is determined by the second capacitor C2. Therefore, in order to ensure that the transimpedance amplifier TIA can quickly establish a signal, the capacitance value of the first capacitor C1 may be much smaller than that of the second capacitor C2. For example, the capacitance of the second capacitor C2 may be set to 195pF, and the capacitance of the first capacitor C1 may be set to 5 pF.

It should be noted that the above examples are only illustrative, and cannot be taken as a limitation on the capacitance values of the first capacitor and the second capacitor in the embodiment of the present application.

In one possible implementation manner of the embodiment of the present application, as shown in fig. 3, the filter of the filtering sub-circuit may further include a first resistance element R1.

The first end of the first resistor element R1 is connected with the input end of the TIA, and the second end of the first resistor element R1 is connected with the output end of the TIA. Specifically, the first resistor element R1 and the second capacitor C2 are connected in parallel to form a filter circuit.

In one possible implementation of the embodiment of the present application, as shown in fig. 3, the first switching element of the filtering sub-circuit may include a first switch f 1.

A first terminal of the first switch f1 is connected to the input terminal of the transimpedance amplifier TIA, and a second terminal of the first switch f1 is connected to a first terminal of the second capacitor C2.

Specifically, the first switch f1 may control a connection path of the second capacitor C2 and the input terminal of the transimpedance amplifier TIA. During the period that the transimpedance amplifier TIA establishes a signal through the first capacitor C1, the first switch f1 disconnects the connection path of the second capacitor C2 and the transimpedance amplifier TIA; after the transimpedance amplifier TIA establishes a signal, the first switch f1 connects the second capacitor C2 with the transimpedance amplifier TIA, so that the second capacitor C2 and the first resistor element R1 form a filter circuit to filter an input signal of the transimpedance amplifier TIA.

In one possible implementation manner of the embodiment of the present application, as shown in fig. 3, the charge sub-circuit may include an operational amplifier opa (operational amplifier).

The non-inverting input end of the operational amplifier OPA is connected with the input end of the transimpedance amplifier TIA, and the inverting input end and the output end of the operational amplifier OPA are connected with the filter sub-circuit.

Specifically, during the period that the transimpedance amplifier TIA establishes a signal through the first capacitor C1, the second capacitor C2 can be rapidly charged through the operational amplifier OPA, so that the potential of the left plate of the second capacitor C2 is the same as the potential of the input signal.

In one possible implementation of the embodiment of the present application, as shown in fig. 3, the second switching element may include a second switch f 2.

A first terminal of the second switch f2 is connected to the output terminal of the operational amplifier OPA, and a second terminal of the second switch f2 is connected to a first terminal of the second capacitor C2.

Specifically, the second switch f2 may control the connection path between the operational amplifier OPA and the second capacitor C2. During the period that the transimpedance amplifier TIA establishes a signal through the first capacitor C1, the second switch f2 connects the operational amplifier OPA and the second capacitor C2, so that the second capacitor C2 is rapidly charged through the operational amplifier OPA, and the potential of the left plate of the second capacitor C2 is the same as the potential of the input signal. After the transimpedance amplifier TIA establishes a signal, the second switch f2 disconnects the connection path between the operational amplifier OPA and the second capacitor C2, and at this time, the second capacitor C2 and the first resistor element R1 form a filter circuit to filter the input signal of the transimpedance amplifier TIA.

The operation principle of the control circuit in different stages according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 4 is a circuit schematic diagram of the control circuit in the signal setup phase according to the embodiment of the present application. At this stage, the enable switch fs and the second switch f2 are closed and the first switch f1 is open. Since the capacitance value of the first capacitor C1 is small, the transimpedance amplifier TIA can quickly establish a signal through the first capacitor C1. Meanwhile, the operational amplifier OPA charges the second capacitor C2 quickly, so that the potential of the left plate of the second capacitor C2 is quickly established as the potential of the input signal.

Fig. 5 is a schematic circuit diagram of a control circuit in the filtering stage according to an embodiment of the present application. At this stage, the second switch f2 is opened to block the OPA from the second capacitor C2, the first switch f1 is closed to switch the second capacitor C2 back to the main path of the TIA, so as to achieve a low filtering bandwidth and obtain a good filtering effect.

It should be noted that, for the on-off timing and the on-off duration of the first switch f1 and the second switch f2, corresponding control signals may be set according to specific circuit parameters. For example, the control signal may be a high level signal or a low level signal which lasts for a certain period of time, and the first switch f1 and the second switch f2 may be switched on or off according to the transition of the high level and the low level, which is not limited in this application.

In addition, since the operational amplifier OPA itself has an offset voltage, when the second capacitor C2 is rapidly charged through the operational amplifier OPA, the potentials of the left plates of the first capacitor C1 and the second capacitor C2 are the sum of the potential of the input signal of the transimpedance amplifier TIA and the offset voltage of the operational amplifier OPA. Additional signal settling time is required when switching the second capacitor C2 back into the main path of the transimpedance amplifier TIA. In order to eliminate the offset voltage, the potential of the left plate of the second capacitor C2 is made to be the same as the potential of the input signal, and fig. 6 shows a circuit schematic diagram of a control circuit according to another embodiment of the present application.

As shown in fig. 6, based on the embodiment shown in fig. 3, the filter circuit may further include an offset canceling sub-circuit, and the offset canceling sub-circuit is connected to the charging sub-circuit and is used for performing offset canceling on the charging sub-circuit.

In some embodiments, the offset cancellation sub-circuit may include a third capacitance C3, a third switching element, a fourth switching element, and a fifth switching element.

The third switching element, the fourth switching element and the fifth switching element may be any type of switch-type devices, and the on and off of the third switching element, the fourth switching element and the fifth switching element may be controlled by a third switching control signal, a fourth switching control signal and a fifth switching control signal, respectively. The different switching control signals may be generated by a separate controller, or may be generated by an overall controller of a circuit module in which the transimpedance amplifier is located, which is not limited in this application.

In one possible implementation manner of the embodiment of the present application, as shown in fig. 6, the third switching element may include a third switch f3, the fourth switching element may include a fourth switch f4, and the fifth switching element may include a fifth switch f 5.

A first end of the third capacitor C3 is connected to the transimpedance amplifier TIA through the third switch f3, and a second end of the third capacitor C3 is connected to the input end of the charging sub-circuit and the first end of the fourth switch f4, respectively. A second terminal of the fourth switch f4 is connected to the filtering sub-circuit. A first terminal of the fifth switch f5 is connected to the transimpedance amplifier TIA via the third switch f3, and a second terminal of the fifth switch f5 is connected to the filter sub-circuit.

It should be noted that, during the period that the transimpedance amplifier TIA establishes a signal through the first capacitor C1, the second switch f2, the third switch f3 and the fourth switch f4 are controlled to be closed, the second capacitor C2 is charged through the operational amplifier OPA, and the potential of the left plate of the second capacitor C2 is quickly established to the offset between the potential VIP of the input signal of the transimpedance amplifier TIA and the potential of the operational amplifier OPAPressure V_osIn addition, the potential of the first terminal of the third capacitor C3 is the potential VIP of the input signal of the transimpedance amplifier TIA.

After the transimpedance amplifier TIA establishes a signal, the third switch f3 and the fourth switch f4 are controlled to be opened, the fifth switch f5 is controlled to be closed, so that the operational amplifier OPA is subjected to offset cancellation, and the potential of the left plate of the second capacitor C2 is equal to the potential of the first end of the third capacitor C3, namely the potential VIP or VIN of an input signal of the transimpedance amplifier TIA.

The operation principle of the control circuit in different stages according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 7 is a circuit schematic diagram of the control circuit in the signal setup phase according to the embodiment of the present application. At this stage, the enable switch fs, the second switch f2, the third switch f3, and the fourth switch f4 are closed, and the first switch f1 and the fifth switch f5 are opened. Since the capacitance value of the first capacitor C1 is small, the transimpedance amplifier TIA can quickly establish a signal through the first capacitor C1. Meanwhile, the operational amplifier OPA charges the second capacitor C2 quickly, so that the potential of the left plate of the second capacitor C2 is quickly established to the potential VIP or VIN of the input signal of the TIA and the offset voltage V of the operational amplifier OPA_osIn addition, the potential of the first terminal of the third capacitor C3 is the potential VIP or VIN of the input signal of the transimpedance amplifier TIA.

Fig. 8 is a schematic circuit diagram of a control circuit in an offset cancellation stage according to an embodiment of the present application. At this stage, the first switch f1, the third switch f3 and the fourth switch f4 are turned off, and the enable switch fs, the second switch f2 and the fifth switch f5 are turned on to perform offset cancellation on the operational amplifier OPA, so that the potential of the left plate of the second capacitor C2 is equal to the potential of the first end of the third capacitor C3, that is, the potential VIP or VIN of the input signal of the transimpedance amplifier TIA.

Fig. 9 is a schematic circuit diagram of a control circuit in the filtering stage according to an embodiment of the present application. At this stage, the second switch f2, the third switch f3, the fourth switch f4 and the fifth switch f5 are turned off to block the OPA and the TIA, thereby achieving the purpose of further saving power. Meanwhile, the enabling switch fs and the first switch f1 are closed, and the second capacitor C2 is switched back to the main path of the TIA, so that low filtering bandwidth is achieved, and a good filtering effect is obtained.

In the control circuit in the embodiment of the application, firstly, a signal establishing sub-circuit is used for enabling a TIA to quickly establish a signal, and a filter of a filter sub-circuit is charged through a charging sub-circuit while the signal is established; after the signal is established, firstly, the offset cancellation sub-circuit is used for carrying out offset cancellation on the charging sub-circuit, and then the charged filter is communicated with the TIA through the first switching element, so that the signal filtering is realized. Therefore, the rapid establishment of the TIA signal of the transimpedance amplifier is realized, the power consumption of the TIA during the signal establishment is reduced, and a good filtering effect is achieved.

The application also provides a chip comprising the control circuit provided by any other embodiment of the application.

The application also provides a wearable device comprising the control circuit provided by any other embodiment of the application.

In some implementations, the wearable device may be a wrist-worn device, a head-worn device, or an in-ear device, among others.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware that is related to instructions of a program, and the program may be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.