阅读说明：本技术 一种接口扩展方法及接口扩展模块 (Interface extension method and interface extension module ) 是由 刘超 刘明 刘丁熙 王婧婧 于 2021-03-11 设计创作，主要内容包括：本发明提供了一种接口扩展方法及接口扩展模块,其中,该接口扩展模块包括：第一CPU、扩展模块,其中,扩展模块设置在被裁剪的第二CPU的位置上,第一CPU通过高速总线与扩展模块连接,扩展模块与第二CPU的接口连接,第一CPU,用于将与第二CPU之间的高速互联总线配置成PCI E功能,并通过扩展模块使用第二CPU的接口资源,可以解决相关技术中双路或多路服务器裁剪成低路服务器时,被裁剪CPU外设资源无法使用的问题,通过扩展模块让低路数的服务器无缝实现高路数服务器的接口资源,扩展能力增强,且增加了系统带宽。(The invention provides an interface extension method and an interface extension module, wherein the interface extension module comprises: the system comprises a first CPU and an extension module, wherein the extension module is arranged at the position of a second CPU to be cut, the first CPU is connected with the extension module through a high-speed bus, the extension module is connected with an interface of the second CPU, the first CPU is used for configuring the high-speed interconnection bus between the first CPU and the second CPU into a PCI E function, and the interface resource of the second CPU is used through the extension module, so that the problem that the peripheral resource of the cut CPU cannot be used when a double-path or multi-path server is cut into a low-path server in the related technology can be solved, the interface resource of the high-path server is seamlessly realized by the low-path server through the extension module, the extension capability is enhanced, and the system bandwidth is increased.)

1. An interface expansion module, comprising: a first CPU and an expansion module, wherein the expansion module is arranged at the position of a second CPU to be cut, the first CPU is connected with the expansion module through a high-speed bus, the expansion module is connected with an interface of the second CPU,

the first CPU is used for configuring a high-speed interconnection bus between the first CPU and the second CPU into a PCIE function, and the interface resource of the second CPU is used through the expansion module.

2. The interface expansion module of claim 1,

and the expansion module is connected with the network interface, the storage interface and the expansion interface of the second CPU.

3. The interface expansion module of claim 2,

the expansion module comprises PCIE SWITCH, wherein the first CPU is connected to the PCIE SWITCH via a high-speed bus, and the PCIE SWITCH is connected to the expansion interface of the second CPU via a PCIE bus.

4. The interface expansion module of claim 3,

the expansion module further comprises a PCIE interface bridge chip, wherein the PCIE interface bridge chip is connected to the PCIE SWITCH, or the PCIE interface bridge chip is connected to the first CPU;

the extension module is used for being connected with the storage interface, the network interface and the extension interface through the PCIE interface bridge piece respectively.

5. The interface expansion module of claim 1,

the first CPU is used for acquiring the identity identification ID of the extension module through an LS interface and matching the identity identification with a preset identification list; and if the matching is successful, continuing to start the system after loading the configuration preset for the identity.

6. Interface expansion module according to one of claims 1 to 5,

the expansion module further comprises: a connector;

the first CPU is used for being connected with the connector through a high-speed bus;

and the expansion module is used for being connected with the service backboard through the connector.

7. The interface expansion module of claim 6,

the expansion module further comprises: PCIE SWITCH or PCIE interface bridge chip;

the first CPU is configured to be connected to the connector through the PCIE SWITCH interface bridge chip or the PCIE interface bridge chip.

8. Interface expansion module according to any of claims 1 to 5, 7, characterized in that the expansion module is the same size as the clipped CPU.

9. The interface expansion module of any one of claims 1 to 5, 7, wherein the expansion module is encapsulated by means of one of: BGA, LGA, PGA.

10. An interface extension method applied to a first CPU includes:

configuring a high-speed interconnection bus between the second CPU and the cut second CPU into a PCIE function;

and using the interface resource of the second CPU through an expansion module, wherein the expansion module is arranged at the position of the second CPU, and the expansion module is connected with the interface of the second CPU.

11. The method of claim 10, further comprising:

reading the identity of the expansion module through an LS bus;

matching the identity with a preset identity list;

and if the matching is successful, continuing to start the system after loading the configuration preset for the identity.

12. An interface expansion module, applied to a first CPU, comprising:

the configuration module is used for configuring a high-speed interconnection bus between the second CPU and the cut second CPU into a PCIE function;

and the using module is used for using the interface resource of the second CPU through the expansion module, wherein the expansion module is arranged at the position of the second CPU, and the expansion module is connected with the interface of the second CPU.

13. A computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to carry out the method as claimed in claim 10 or 11 when executed.

14. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of claim 10 or 11.

Technical Field

The invention relates to the field of image processing, in particular to an interface extension method and an interface extension module.

Background

With the rapid development of information technology, technology and application innovation driven by industries such as artificial intelligence, big data and cloud computing, internet of things and the like are falling on the ground at an accelerated speed, and various industries such as intelligent medical treatment, intelligent traffic, remote education, video conference and the like are favored. Servers, as infrastructures in these fields, face a number of challenges such as insufficient computing power and density. Therefore, a GPU (Graphics Processing Unit) server for improving computing power by using a GPU card is available, and is used for a face analysis comparison server, an intelligent network card for sharing part of services of a CPU by using co-Processing, and the like. The landing and the effect of the technologies have extremely high dependency on the IO expansion quantity and the bandwidth of the server, and usually, each server manufacturer marks the IO expansion capacity as a core product parameter to a user.

Servers are generally divided into one-way, two-way, four-way, eight-way and other servers according to the number of physical CPUs (Central Processing units), a plurality of CPUs in a multi-way server cooperate with each other, and the operation capability of the multi-way server is improved by several times compared with that of a single-way server, and the expansion capability of the server is improved by overlapping of each CPU Peripheral resource (DIMM (Dual-Inline-Memory-Modules), PCIE (Peripheral Component Interconnect Express, Peripheral Component Interconnect standard), USB (Universal Serial Bus), SATA (Serial Advanced Technology Attachment, Serial Bus) and the like). Fig. 1 is a schematic diagram of a two-way CPU server in the related art, and as shown in fig. 1, a CPU0 and a CPU1 are interconnected through a high-speed bus, so as to implement high-speed, high-efficiency, and low-latency communication between CPUs, where different manufacturers define different types, such as the upi (ultra Path interconnect) of Intel, and the HT (Hyper-Transport) of AMD. The CPU0 and the CPU1 are each connected to a plurality of DIMMs (Dual-Inline-Memory-Modules) for data caching of the operating system and the application programs. The CPU0 is connected to the Riser0 (adapter card or expansion card), Riser1, Riser2, and OCP card (Open computer Project) through PCIE bus, so that the user can flexibly insert and expand the functions through PCIE interface; bridging through an NIC (Network interface controller) chip and an RAID (Redundant Array of Independent Disks) card to realize Network card and storage bridging; data storage is realized by interconnection of NVME (Non-Volatile Memory Express)/SATA interface and SSD (Solid-state Drive)/HDD (Hard Disk). The BMC chip (Baseboard management Controller) and the CPU0 are interconnected through interfaces such as PCIE, USB, I2C (Inter-Integrated Circuit), LPC (Low Pin Count Bus), and the like, so as to implement monitoring and remote operation and maintenance of the server system bandwidth. The CPU1 is connected with a Riser3, a Riser4 and a Riser5 through a PCIE bus, so that a user can flexibly insert and expand the functions through the PCIE interface; and data storage is realized by interconnecting the NVME/SATA interface and the SSD/HDD. The USB interfaces of the CPU0 and the CPU1 form a USB physical interface inside or outside the case, and realize functions of a mouse, a USB flash disk and the like.

Due to the reasons of high reliability requirement and long development and test period, the server usually multiplexes hardware of a single-path server and a double-path server, namely, in a scene with low requirement on the performance of the CPU, the CPU1 of the double-path server is not loaded, a low-cost single-path server model is formed, and the Ricers 0, 1 and 2 in the CPU0 are switched to the physical expansion space of the CPU1 through a high-speed cable and a switching card, so that the enhancement of the expansion capability is realized, namely, the positions of the Ricers 3, 4 and 5 in the space. Or directly tailor the expansion capabilities of CPU1 in the dashed box of fig. 1. However, when the two-way server is cut into the one-way server, the problem that the cut CPU peripheral resources cannot be used exists.

In the prior art, the Riser0, 1 and 2 in the CPU0 are switched to the physical expansion space of the CPU1 through a high-speed cable and a switching card, so that the expansion capability is enhanced, namely the positions of the Riser3, 4 and 5 in the space. Since the total bandwidth of the Riser0, 1 and 2 is limited, the number of available expansion slots is increased in the mode, but the total bandwidth is not increased, and the average expansion bandwidth of the Riser is reduced, so that the overall expansion performance is influenced. Secondly, through the switching of the high-speed cable and the switching card, the fixed positions of the switching card and the cable need to be designed, so that multiple times of switching exist, the signal attenuation is more, and the overall reliability is reduced; the inside has increased the cable, and inside pleasing to the eye degree descends.

Aiming at the problem that the peripheral resources of a cut CPU cannot be used when a two-way server or a plurality of servers are cut into low-way servers in the prior art, no solution is provided.

Disclosure of Invention

The embodiment of the invention provides an interface expansion method and an interface expansion module, which are used for at least solving the problem that the peripheral resources of a cut CPU cannot be used when a two-way server or a plurality of servers are cut into low-way servers in the related technology.

According to an embodiment of the present invention, there is provided an interface expansion module including: the system comprises a first CPU and an expansion module, wherein the expansion module is arranged at the position of a second CPU to be cut, the first CPU is connected with the expansion module through a high-speed bus, the expansion module is connected with an interface of the second CPU, the first CPU is used for configuring the high-speed interconnection bus between the first CPU and the second CPU into a PCIE function, and the interface resource of the second CPU is used through the expansion module.

In an exemplary embodiment, the expansion module is connected with the network interface, the storage interface and the expansion interface of the second CPU.

In an exemplary embodiment, the expansion module includes PCIE SWITCH (PCIE switch chip), where the first CPU is connected to the PCIE SWITCH through a high speed bus, and the PCIE SWITCH is connected to the expansion interface of the second CPU through a PCIE bus.

In an exemplary embodiment, the expansion module further includes a PCIE interface bridge, where the PCIE interface bridge is connected to the PCIE SWITCH, or the PCIE interface bridge is connected to the first CPU; the extension module is used for being connected with the storage interface, the network interface and the extension interface through the PCIE interface bridge piece respectively.

In an exemplary embodiment, the first CPU is configured to acquire an identification ID of the expansion module through an LS (Line System) interface, and match the identification with a preset identification list; and if the matching is successful, continuing to start the system after loading the configuration preset for the identity.

In one exemplary embodiment, the expansion module further comprises: a connector; the first CPU is used for being connected with the connector through a high-speed bus; and the expansion module is used for being connected with the service backboard through the connector.

In one exemplary embodiment, the expansion module further comprises: PCIE SWITCH or PCIE interface bridge chip; the first CPU is configured to be connected to the connector through the PCIE SWITCH interface bridge chip or the PCIE interface bridge chip.

In one exemplary embodiment, the expansion module is the same size as the cropped CPU.

In an exemplary embodiment, the expansion module is packaged by a packaging method of one of the following: BGA (Ball Grid Array), LGA (Land Grid Array), PGA (Pin Grid Array).

According to another embodiment of the present invention, there is also provided an interface extension method applied to a first CPU, including: configuring a high-speed interconnection bus between the second CPU and the cut second CPU into a PCIE function; and using the interface resource of the second CPU through an expansion module, wherein the expansion module is arranged at the position of the second CPU, the first CPU is connected with the expansion module through a high-speed bus, and the expansion module is connected with the interface of the second CPU.

In one exemplary embodiment, the method further comprises: reading the identity of the expansion module through an LS bus; matching the identity with a preset identity list; and if the matching is successful, continuing to start the system after loading the configuration preset for the identity.

According to another embodiment of the present invention, there is also provided an interface expansion module applied to a first CPU, including: the configuration module is used for configuring a high-speed interconnection bus between the second CPU and the cut second CPU into a PCIE function; and the using module is used for using the interface resource of the second CPU through the expansion module, wherein the expansion module is arranged at the position of the second CPU, the first CPU is connected with the expansion module through a high-speed bus, and the expansion module is connected with the interface of the second CPU.

In one exemplary embodiment, further comprising: the reading module is used for reading the identity of the expansion module through an LS bus; the matching module is used for matching the identity with a preset identity list; and the processing module is used for continuing to start the system after loading the configuration preset for the identity identification if the matching is successful.

According to a further embodiment of the present invention, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above-described method embodiments when executed.

According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

By the invention, the first CPU and the expansion module are arranged at the position of the second CPU to be cut, the first CPU is connected with the expansion module through a high-speed bus, the expansion module is connected with the interface of the second CPU, the first CPU is used for configuring the high-speed interconnection bus between the first CPU and the second CPU into a PCIE function, and the interface resource of the second CPU is used by the expansion module, so that the problem that the peripheral resource of the cut CPU cannot be used when a two-way or multi-way server is cut into a low-way server in the related technology can be solved, the position of the cut CPU is used for arranging the expansion module, the high-speed bus interconnected among the CPUs is used for connecting the expansion module, the original server design is not required to be changed, the interface resource of the high-way server is seamlessly realized by the low-way server through the expansion module, and the expansion capability is enhanced, and increases the system bandwidth.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:

fig. 1 is a schematic diagram of a two-way CPU server in the related art;

FIG. 2 is a schematic structural diagram of an interface expansion module according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram (one) of an interface expansion module according to an alternative embodiment of the present invention;

fig. 4 is a schematic structural diagram (two) of an interface expansion module according to an alternative embodiment of the present invention;

fig. 5 is a schematic structural diagram (three) of an interface expansion module according to an alternative embodiment of the present invention;

fig. 6 is a schematic structural diagram (iv) of an interface expansion module according to an alternative embodiment of the present invention;

fig. 7 is a schematic structural diagram (five) of an interface expansion module according to an alternative embodiment of the present invention;

fig. 8 is a schematic structural diagram (six) of an interface expansion module according to an alternative embodiment of the present invention;

FIG. 9 is a schematic diagram of the system workflow of an expansion module according to an alternative embodiment of the present invention;

fig. 10 is a block diagram of a hardware configuration of a mobile terminal of an interface expansion method according to an embodiment of the present invention;

FIG. 11 is a flow chart of an interface expansion method according to an embodiment of the present invention;

fig. 12 is a block diagram of an interface expansion module according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail hereinafter with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Example 1

An embodiment of the present invention provides an interface extension module, and fig. 2 is a schematic structural diagram of the interface extension module according to the embodiment of the present invention, as shown in fig. 2, including:

the system comprises a first CPU202 and an expansion module 204, wherein the expansion module is arranged at the position of a second CPU206 which is cut, the first CPU is connected with the expansion module through a high-speed bus, the expansion module is connected with an interface of the second CPU, and the first CPU is used for configuring the high-speed interconnection bus between the first CPU and the second CPU into a PCIE function and using the interface resource of the second CPU through the expansion module.

Through the interface expansion module, the problem that peripheral resources of a cut CPU cannot be used when a double-path or multi-path server is cut into a low-path server in the related technology can be solved, the expansion module is arranged at the position of the cut CPU, the expansion module is connected by using a high-speed bus which is interconnected among the CPUs, the original server design is not required to be changed, the low-path server seamlessly realizes the interface resources of the high-path server through the expansion module, the expansion capability is enhanced, and the system bandwidth is increased.

In an optional embodiment, the expansion module 204 is connected to the network interface, the storage interface, and the expansion interface of the second CPU.

That is, the expansion module 204 requires a plurality of interfaces to which the second CPU is connected.

In an alternative embodiment, the expansion module 204 includes PCIE SWITCH, wherein the first CPU202 is connected to the PCIE SWITCH via a high-speed bus, and the PCIE SWITCH is connected to the expansion interface of the second CPU via a PCIE bus.

That is, the expansion module 204 is connected to the first CPU202 through PCIE SWITCH.

In an optional embodiment, the expansion module 204 further includes a PCIE interface bridge, where the PCIE interface bridge is connected to the PCIE SWITCH, or the PCIE interface bridge is connected to the first CPU; the expansion module 204 is configured to be connected to the storage interface, the network interface, and the expansion interface through the PCIE interface bridge chip.

Namely, the PCIE interface bridge connection PCIE SWITCH, the storage interface, and the network interface of the expansion module 204.

In an optional embodiment, the first CPU202 is configured to obtain an identification ID of the extension module 204 through an LS interface, and match the identification with a preset identification list; and if the matching is successful, continuing to start the system after loading the configuration preset for the identity.

That is, the first CPU202 acquires and verifies the identification ID of the extension module 204 through the LS interface, and continues to start the system after the identification is passed.

In an optional embodiment, the expansion module 204 further includes: a connector; the first CPU202 is configured to be connected to the connector through a high-speed bus; the expansion module 204 is configured to connect with a service backplane through the connector.

That is, the connector of the expansion module 204 connects the high-speed bus of the first CPU202 and the service backplane.

In an optional embodiment, the expansion module 204 further includes: PCIE SWITCH or PCIE interface bridge chip; the first CPU202 is configured to be connected to the connector through the PCIE SWITCH interface bridge chip or the PCIE interface bridge chip.

That is, the first CPU202 is connected to the connector through PCIE SWITCH or a PCIE interface bridge of the expansion module 204.

Optionally, the size of the expansion module 204 is the same as the clipped CPU.

Optionally, the expansion module 204 is packaged in a packaging manner of one of the following: BGA, LGA, PGA.

The expansion module can be composed of 1 or more of PCB board, electronic components, connectors, structural components and the like. The size of the package is the same as that of the CPU, and the package may be BGA, LGA, PGA or the like, and is mounted on the CPU1 position of the server motherboard.

The expansion module may include board identification id information, and the implementation manner includes I/O pull-up and pull-down resistors, false sh, EEPROM, and the like, and after the CPU0 acquires these information through the LS interface, it can identify the module, and load a configuration file for the module, thereby implementing adaptation. The configuration comprises the interface configuration of the cpu and the expansion module, and also comprises the configuration of the expansion module and the downlink interface. LS can be GPIO, IIC, SMBUS, etc.

The expansion module can be PCIE SWITCH, a PCIE interface bridge plate or a combination of the two, and can realize the expansion of any interface of the server, thereby greatly enhancing the flexibility.

The expansion module can comprise a high-speed connector, PCIE or other resources are directly connected to a backboard or other modules through a high-speed cable, the switching times of the connector are reduced, and the quality of high-speed signals is improved.

The expansion module can contain a high-speed signal driving chip, so that the transmission capability of high-speed signals is enhanced, and the reliability is improved.

The expansion module may be a PCB through-line, i.e., CPU0 is directly connected to a riser card or other chip device.

Fig. 3 is a schematic structural diagram (i) of an interface expansion module according to an alternative embodiment of the present invention, as shown in fig. 3, wherein a CPU0 is directly connected to a riser card.

Fig. 4 is a schematic structural diagram (ii) of an interface expansion module according to an alternative embodiment of the present invention, as shown in fig. 4, which increases PCIE SWITCH expansion in the case of insufficient PCIE resources.

Fig. 5 is a schematic structural diagram (iii) of an interface expansion module according to an alternative embodiment of the present invention, and as shown in fig. 5, a Bridge chip (i.e., a Bridge chip) is added in the case of shortage of SATA and USB.

Fig. 6 is a schematic structural diagram (iv) of an interface expansion module according to an alternative embodiment of the present invention, as shown in fig. 6, where a Bridge chip is connected to PCIE SWITCH, and an uplink signal of the Bridge chip may also be PCIE SWITCH downlink.

Fig. 7 is a schematic structural diagram (v) of an interface expansion module according to an alternative embodiment of the present invention, and as shown in fig. 7, an expansion module is assembled with a connector and directly connected to a service module such as a backplane, a Riser card, or the like through a high-speed cable.

Fig. 8 is a schematic structural diagram (vi) of an interface expansion module according to an alternative embodiment of the present invention, and as shown in fig. 8, when PCIE or I/O resources are insufficient, PCIE SWITCH/Bridge chip expansion may be added, and the interface expansion module is directly connected to service modules such as a backplane and a Riser card through a high-speed cable.

A supportable expansion module list is preset in BIOS software, id is used for marking, and different BIOS configurations, such as different combinations of PCIE lane numbers, function selection of SATA, USB and the like, are preset in each different expansion module.

Fig. 9 is a schematic diagram of a workflow of an expansion module system according to an alternative embodiment of the present invention, as shown in fig. 9, including:

step S1, after the expansion module is installed, the system is powered on;

step S2, the central processing unit CPU0 reads the identity information id of the expansion module through the LS bus;

step S3, matching with the BIOS software preset identification list information; if the matching is successful, go to step S4; if the matching fails, go to S7;

step S4, BIOS loads the configuration preset based on the id information;

step S5, the CPU and the expansion module complete the relevant configuration;

step S6, the system continues to start the finishing step;

step S7, feeding back an alarm; and returns to step S2.

After the system is powered on, the central processing unit CPU0 reads the identity information id of the expansion module through the LS bus, and matches the identity information id with the identifier list preset in the BIOS software. If the same id can not be matched, the system does not support the expansion module and feeds back alarm information. And after the system is matched with the valid id and the BIOS loads the preset configuration based on the id information, the system continues to start and finish the steps.

Example 2

The method provided by the embodiment of the application can be executed in a mobile terminal, a computer terminal or a similar operation device. Taking a mobile terminal as an example, fig. 10 is a block diagram of a hardware structure of the mobile terminal of the interface extension method according to the embodiment of the present invention, and as shown in fig. 10, the mobile terminal may include one or more processors 1002 (only one is shown in fig. 10) (the processor 1002 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and a memory 1004 for storing data, and optionally, the mobile terminal may further include a transmission device 1006 for a communication function and an input/output device 1008. It will be understood by those skilled in the art that the structure shown in fig. 10 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG. 10, or have a different configuration than shown in FIG. 10.

The memory 1004 can be used for storing computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the interface extension method in the embodiment of the present invention, and the processor 1002 executes the computer programs stored in the memory 1004 to perform various functional applications and control of telnet, that is, to implement the method described above. The memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 1004 may further include memory located remotely from the processor 1002, which may be connected to the mobile terminal through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 1006 is used for receiving or sending data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 1006 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 1006 can be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.

In this embodiment, an interface extension method operating in the mobile terminal or the network architecture is provided, and is applied to the first CPU, and fig. 11 is a flowchart of the interface extension method according to the embodiment of the present invention, as shown in fig. 11, where the flowchart includes the following steps:

step S1102, configuring a high-speed interconnection bus between the second CPU and the cut second CPU into a PCIE function;

step S1104, using an interface resource of the second CPU through an expansion module, where the expansion module is disposed at a position of the second CPU, and the expansion module is connected to an interface of the second CPU.

Specifically, the first CPU is connected to the expansion module through a high-speed bus.

Configuring a high-speed interconnection bus between the second CPU and the cut second CPU into a PCIE function through the steps S1102 to S1104; the interface resources of the second CPU are used through the expansion module, wherein the expansion module is arranged at the position of the second CPU, the first CPU is connected with the expansion module through a high-speed bus, the expansion module is connected with the interface of the second CPU, the problem that the peripheral resources of the cut CPU cannot be used when a double-path or multi-path server is cut into a low-path server in the related technology can be solved, the expansion module is arranged at the position of the cut CPU, the high-speed bus connected with the expansion module through interconnection among the CPUs is used, the original server design is not required to be changed, the interface resources of the high-path server are seamlessly realized by the low-path server through the expansion module, the expansion capability is enhanced, and the bandwidth is increased.

In an optional embodiment, the method further comprises: reading the identity of the expansion module through an LS bus; matching the identity with a preset identity list; and if the matching is successful, continuing to start the system after loading the configuration preset for the identity.

Namely, the identity identification ID of the extension module is acquired and verified through the LS interface, and the system is continuously started after the identification is passed.

Example 3

An embodiment of the present invention further provides an interface extension module, which is applied to a first CPU, and fig. 12 is a block diagram of the interface extension module according to the embodiment of the present invention, as shown in fig. 12, including:

a configuration module 122, configured to configure a high-speed interconnect bus between the second CPU and the clipped CPU into a PCIE function;

a using module 124, configured to use the interface resource of the second CPU through an extension module, where the extension module is disposed at a location of the second CPU, and the extension module is connected to the interface of the second CPU.

Through the interface expansion module, the problem that peripheral resources of a cut CPU cannot be used when a double-path or multi-path server is cut into a low-path server in the related technology can be solved, the expansion module is arranged at the position of the cut CPU, the expansion module is connected by using a high-speed bus which is interconnected among the CPUs, the original server design is not required to be changed, the low-path server seamlessly realizes the interface resources of the high-path server through the expansion module, the expansion capability is enhanced, and the bandwidth is increased.

In an optional embodiment, further comprising: the reading module is used for reading the identity of the expansion module through an LS bus; the matching module is used for matching the identity with a preset identity list; and the processing module is used for continuing to start the system after loading the configuration preset for the identity identification if the matching is successful.

Namely, the identity identification ID of the extension module is acquired and verified through the LS interface, and the system is continuously started after the identification is passed.

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

Example 4

Embodiments of the present invention also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the above method embodiments when executed.

Alternatively, in the present embodiment, the storage medium may be configured to store a computer program for executing the steps of:

s1, configuring the high-speed interconnection bus between the second CPU and the cut CPU into a PCIE function;

and S2, using the interface resource of the second CPU through an expansion module, wherein the expansion module is arranged at the position of the second CPU, the first CPU is connected with the expansion module through a high-speed bus, and the expansion module is connected with the interface of the second CPU.

Optionally, in this embodiment, the storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Example 5

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

s1, configuring the high-speed interconnection bus between the second CPU and the cut CPU into a PCIE function;

and S2, using the interface resource of the second CPU through an expansion module, wherein the expansion module is arranged at the position of the second CPU, the first CPU is connected with the expansion module through a high-speed bus, and the expansion module is connected with the interface of the second CPU.

Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.

It will be apparent to those skilled in the art that the modules or steps of the present invention described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.