阅读说明：本技术 多通路数据处理电路及系统 (Multi-channel data processing circuit and system ) 是由 徐锦森 于 2019-12-12 设计创作，主要内容包括：本公开涉及一种多通路数据处理电路,该多通路数据处理电路包括多个通路电路模块和多个寄存器。多个通路电路模块联接到数据接口的多个通路,并且包括第一通路电路模块和第二通路电路模块,其中每一个通路电路模块包括第一处理电路和第二处理电路。第一通路电路模块和第二通路电路模块的第一处理电路电联接,并且第一通路电路模块和第二通路电路模块的第二处理电路电联接。多个寄存器包括第一信息寄存器和第二信息寄存器。第一信息寄存器联接到第一通路电路模块和第二通路电路模块的第一处理电路,并且第二信息寄存器联接到第一通路电路模块和第二通路电路模块的第二处理电路。(The present disclosure relates to a multi-pass data processing circuit including a plurality of pass circuit modules and a plurality of registers. The plurality of lane circuit modules are coupled to the plurality of lanes of the data interface and include a first lane circuit module and a second lane circuit module, wherein each lane circuit module includes a first processing circuit and a second processing circuit. The first processing circuits of the first and second via circuit modules are electrically coupled, and the second processing circuits of the first and second via circuit modules are electrically coupled. The plurality of registers includes a first information register and a second information register. The first information register is coupled to the first processing circuitry of the first lane circuit module and the second lane circuit module, and the second information register is coupled to the second processing circuitry of the first lane circuit module and the second lane circuit module.)

1. A multi-pass data processing circuit comprising:

a plurality of lane circuit modules coupled to a plurality of lanes of a data interface and including a first lane circuit module and a second lane circuit module, wherein each lane circuit module includes a first processing circuit and a second processing circuit, the first processing circuit of the first lane circuit module having an output terminal coupled to the first processing circuit of the second lane circuit module and the second processing circuit of the first lane circuit module having an output terminal coupled to the second processing circuit of the second lane circuit module; and

a plurality of registers including a first information register and a second information register, wherein the first information register has an input terminal coupled to the first processing circuit of the second lane circuit module and an output terminal coupled to the first processing circuit of the first lane circuit module, and the second information register has an input terminal coupled to the second processing circuit of the second lane circuit module and an output terminal coupled to the second processing circuit of the first lane circuit module.

2. The multi-pass data processing circuit of claim 1,

wherein the plurality of pass circuit modules further comprises a third pass circuit module;

wherein the first processing circuit of the second pass circuit module has an output terminal coupled to the first processing circuit of the third pass circuit module and the second processing circuit of the second pass circuit module has an output terminal coupled to the second processing circuit of the third pass circuit module;

wherein an input terminal of the first information register is coupled to the first processing circuit of the second pass circuit module through the first processing circuit of the third pass circuit module; and is

Wherein the input terminal of the second information register is coupled to the second processing circuit of the second pass circuit module through the second processing circuit of the third pass circuit module.

3. The multi-pass data processing circuit of claim 2,

wherein the plurality of pass circuit modules further comprises a fourth pass circuit module;

wherein the first processing circuit of the third pass circuit module has an output terminal coupled to the first processing circuit of the fourth pass circuit module and the second processing circuit of the third pass circuit module has an output terminal coupled to the second processing circuit of the fourth pass circuit module;

wherein the input terminal of the first information register is coupled to the first processing circuit of the second pass circuit module through the first processing circuit of the third pass circuit module and the first processing circuit of the fourth pass circuit module; and is

Wherein the input terminal of the second information register is coupled to the second processing circuit of the second pass circuit module through the second processing circuit of the third pass circuit module and the second processing circuit of the fourth pass circuit module.

4. The multi-pass data processing circuit of claim 1,

wherein each of the plurality of pass circuit modules further comprises control circuitry coupled to the first processing circuitry and the second processing circuitry corresponding to the pass circuit module; and is

Wherein the control circuit corresponding to the pass circuit module selectively enables one or more of the first processing circuit and the second processing circuit corresponding to the pass circuit module according to a pass control signal.

5. The multi-lane data processing circuit of claim 4, wherein when the lane control signal indicates to perform a first process, the control circuit of the plurality of lane circuit modules enables the first processing circuit of the plurality of lane circuit modules, couples the first processing circuit of the plurality of lane circuit modules to a plurality of lanes, respectively, and processes different data sets of the plurality of lanes in a parallel manner.

6. A multi-pass data processing system comprising:

a plurality of physical layer circuit modules coupled to a plurality of lanes of the data interface in a parallel manner; and

a multi-channel data processing circuit for processing data,

wherein the multi-channel data processing circuit comprises:

a plurality of lane circuit modules respectively coupled to the plurality of lanes by the plurality of physical layer circuit modules and including a first lane circuit module and a second lane circuit module, wherein each lane circuit module includes a first processing circuit and a second processing circuit, the first processing circuit of the first lane circuit module having an output terminal coupled to the first processing circuit of the second lane circuit module, and the second processing circuit of the first lane circuit module having an output terminal coupled to the second processing circuit of the second lane circuit module; and

a plurality of registers including a first information register and a second information register, wherein the first information register has an input terminal coupled to the first processing circuit of the second lane circuit module and an output terminal coupled to the first processing circuit of the first lane circuit module, and the second information register has an input terminal coupled to the second processing circuit of the second lane circuit module and an output terminal coupled to the first processing circuit of the second lane circuit module.

7. The multi-pass data processing system of claim 6,

wherein the plurality of pass circuit modules further comprises a third pass circuit module;

wherein the first processing circuit of the second pass circuit module has an output terminal coupled to the first processing circuit of the third pass circuit module and the second processing circuit of the second pass circuit module has an output terminal coupled to the second processing circuit of the third pass circuit module;

wherein an input terminal of the first information register is coupled to the first processing circuit of the second pass circuit module through the first processing circuit of the third pass circuit module; and is

Wherein the input terminal of the second information register is coupled to the second processing circuit of the second pass circuit module through the second processing circuit of the third pass circuit module.

8. The multi-pass data processing system of claim 7,

wherein the plurality of pass circuit modules further comprises a fourth pass circuit module;

wherein the first processing circuit of the third pass circuit module has an output terminal coupled to the first processing circuit of the fourth pass circuit module and the second processing circuit of the third pass circuit module has an output terminal coupled to the second processing circuit of the fourth pass circuit module;

wherein the input terminal of the first information register is coupled to the first processing circuit of the second pass circuit module through the first processing circuit of the third pass circuit module and the first processing circuit of the fourth pass circuit module; and is

Wherein the input terminal of the second information register is coupled to the second processing circuit of the second pass circuit module through the second processing circuit of the third pass circuit module and the second processing circuit of the fourth pass circuit module.

9. The multi-pass data processing system of claim 6,

wherein each of the plurality of pass circuit modules further comprises control circuitry coupled to the first processing circuitry and the second processing circuitry corresponding to the pass circuit module; and is

Wherein the control circuit corresponding to the pass circuit module selectively enables one or more of the first processing circuit and the second processing circuit corresponding to the pass circuit module according to a pass control signal.

10. The multi-lane data processing system of claim 9, wherein when the lane control signal indicates to perform a first process, the control circuitry of the plurality of lane circuit modules enables the first processing circuitry of the plurality of lane circuit modules, couples the first processing circuitry of the plurality of lane circuit modules to the plurality of lanes through the plurality of physical layer circuit modules, respectively, and processes different data sets of the plurality of lanes in a parallel manner.

11. The multi-pass data processing system of claim 9, wherein the plurality of physical layer circuit modules are transmitter physical layer circuits.

12. The multi-pass data processing system of claim 9, wherein the plurality of physical layer circuit modules are receiver physical layer circuits.

13. A multi-pass data processing system coupled to N number of passes, the system comprising:

n number of lane circuit modules, each lane circuit module including M number of processing circuits and receiving data from the lanes, respectively, each of N and M being 2 or greater than 2; and

m number of registers;

wherein a pth register among the registers and a pth processing circuit among the processing circuits within each of the pass circuit modules are coupled to form a cascade structure such that the pth register outputs data to a pth processing circuit of a first one of the pass circuit modules and a pth processing circuit of a last one of the pass circuit modules outputs data to the pth register;

wherein each of the processing circuits processes data supplied from a preceding stage and outputs the processed data to a subsequent stage; and is

Wherein each of the processing circuits further receives data from a corresponding one of the paths and outputs the processed data to the outside.

Technical Field

Various embodiments relate generally to a data processing circuit and system, and more particularly, to a multi-pass data processing circuit and system.

Background

To meet the requirement of a data interface with a relatively large transmission frequency bandwidth, most electronic products employ a serializer/deserializer (SerDes) and multiple paths to implement the data interface and related circuits inside or outside the electronic product. For SerDes and multiple lanes, electronics apply corresponding data processing circuitry to perform the necessary processing on data that the data interface is intended to send or receive.

For example, for a multi-channel data processing circuit or a communication device, due to product standards or product development, designers need to design multiple versions of electronic products having data interfaces with different transmission frequency bandwidths. When the multi-path technique is adopted, a designer can arrange a relatively large number of paths based on a data interface circuit of a certain version of an electronic device whose transmission frequency bandwidth is relatively small, thereby easily obtaining a data interface circuit of a version of an electronic product whose transmission frequency bandwidth is relatively high.

However, the total number of lanes has increased from the perspective of the corresponding data processing circuitry. Therefore, the designer needs to reconsider how to set the update of the data processing circuit of the electronic product of the version having the smaller transmission frequency bandwidth, or whether to correct the data processing circuit so as to apply the data processing circuit to the electronic product of the version having the larger transmission frequency bandwidth. Such setup or correction may increase the complexity of the circuit, as it may involve programming of circuit arrangements within an integrated circuit, such as an associated chip. In the worst case, the designer may have to redesign the appropriate data processing circuit. In such a worst case, when developing a relevant version of an electronic product, development efficiency may be affected and development costs may be increased.

Therefore, when applying the multi-pass technique, there is still a need to improve the corresponding data processing circuit used in the electronic product in terms of scalability.

Disclosure of Invention

Various embodiments are directed to a multi-channel data processing circuit and system that can be applied to an electronic device adopting a multi-channel technology and realize a data processing circuit having a relatively low-complexity circuit structure, thereby satisfying the requirements of a plurality of versions of electronic products having data interfaces whose transmission frequency bandwidths are different from each other.

In an embodiment, there is provided a multi-pass data processing circuit comprising: a plurality of lane circuit modules coupled to the plurality of lanes of the data interface and including a first lane circuit module and a second lane circuit module, wherein each lane circuit module includes a first processing circuit and a second processing circuit, the first processing circuit of the first lane circuit module having an output terminal coupled to the first processing circuit of the second lane circuit module and the second processing circuit of the first lane circuit module having an output terminal coupled to the second processing circuit of the second lane circuit module; and a plurality of registers including a first information register and a second information register, wherein the first information register has an input terminal coupled to the first processing circuit of the second pass circuit module and an output terminal coupled to the first processing circuit of the first pass circuit module, and the second information register has an input terminal coupled to the second processing circuit of the second pass circuit module and an output terminal coupled to the second processing circuit of the first pass circuit module.

The plurality of pass circuit modules further includes a third pass circuit module, wherein the first processing circuit of the second pass circuit module has an output terminal electrically coupled to the first processing circuit of the third pass circuit module, and the second processing circuit of the second pass circuit module has an output terminal electrically coupled to the second processing circuit of the third pass circuit module. An input terminal of the first information register is electrically coupled to the first processing circuit of the second pass circuit module through the first processing circuit of the third pass circuit module; and an input terminal of the second information register is electrically coupled to the second processing circuit of the second pass circuit module through the second processing circuit of the third pass circuit module.

The plurality of pass circuit modules further includes a fourth pass circuit module, wherein the first processing circuit of the third pass circuit module has an output terminal electrically coupled to the first processing circuit of the fourth pass circuit module, and the second processing circuit of the third pass circuit module has an output terminal electrically coupled to the second processing circuit of the fourth pass circuit module. An input terminal of the first information register is electrically coupled to the first processing circuit of the second pass circuit module through the first processing circuit of the third pass circuit module and the first processing circuit of the fourth pass circuit module; and an input terminal of the second information register is electrically coupled to the second processing circuit of the second pass circuit module through the second processing circuit of the third pass circuit module and the second processing circuit of the fourth pass circuit module.

Each of the plurality of pass circuit modules further comprises: a control circuit coupled to the first processing circuit and the second processing circuit corresponding to the pass circuit module. The control circuit corresponding to the pass circuit module selectively enables one or more of the first processing circuit and the second processing circuit corresponding to the pass circuit module according to the pass control signal.

When the lane control signal indicates that the first processing is to be performed, the control circuit of the plurality of lane circuit modules enables the first processing circuit of the plurality of lane circuit modules, couples the first processing circuits of the plurality of lane circuit modules to the plurality of lanes, respectively, and processes different data sets of the plurality of lanes in a parallel manner.

In an embodiment, there is provided a multi-pass data processing system comprising: a plurality of physical layer circuit modules coupled to a plurality of lanes of the data interface in a parallel manner; and a multi-pass data processing circuit, wherein the multi-pass data processing circuit comprises: a plurality of via circuit modules respectively coupled to the plurality of vias by the plurality of physical layer circuit modules, and including a first via circuit module and a second via circuit module, wherein each of the via circuit modules includes a first processing circuit and a second processing circuit, the first processing circuit of the first via circuit module having an output terminal coupled to the first processing circuit of the second via circuit module, and the second processing circuit of the first via circuit module having an output terminal coupled to the second processing circuit of the second via circuit module; and a plurality of registers including a first information register and a second information register, wherein the first information register has an input terminal coupled to the first processing circuit of the second lane circuit module and an output terminal coupled to the first processing circuit of the first lane circuit module, and the second information register has an input terminal coupled to the second processing circuit of the second lane circuit module and an output terminal coupled to the first processing circuit of the second lane circuit module.

When the lane control signal indicates that the first processing is to be performed, the control circuit of the plurality of lane circuit modules enables the first processing circuit of the plurality of lane circuit modules and couples the first processing circuit of the plurality of lane circuit modules to the plurality of lanes through the plurality of physical layer circuit modules, respectively, and processes different data sets of the plurality of lanes in a parallel manner.

The plurality of physical layer circuit modules are transmitter physical layer circuits.

The plurality of physical layer circuit modules are receiver physical layer circuits.

In an embodiment, there is provided a multi-pass data processing system comprising: n number of lane circuit blocks, each lane circuit block including M number of processing circuits and respectively configured to receive data from a lane, each of N and M being 2 or greater than 2; and an M number of registers, wherein a pth register among the registers and a pth processing circuit among processing circuits within each of the pass circuit modules are coupled to configure a cascade structure such that the pth register outputs data into a pth processing circuit of a first pass circuit module among the pass circuit modules and a pth processing circuit of a last pass circuit module among the pass circuit modules outputs data to the pth register, wherein each of the processing circuits is configured to process data supplied from a previous stage and output the processed data to a subsequent stage, and wherein each of the processing circuits is further configured to receive data from a corresponding one of the passes and is configured to output the processed data to the outside.

Drawings

FIG. 1 is a block diagram illustrating an embodiment of a multi-pass data processing circuit.

FIG. 2 is a diagram for describing an embodiment of parallel processing of data by the multi-pass data processing circuit of FIG. 1.

FIG. 3 is a block diagram illustrating another embodiment of the multi-pass data processing circuit of FIG. 1.

FIG. 4 is a diagram for describing an embodiment of parallel processing of data by the multi-pass data processing circuit of FIG. 3.

FIG. 5 is a block diagram illustrating another embodiment of the multi-pass data processing circuit of FIG. 1.

FIG. 6 is a diagram for describing an embodiment of parallel processing of data by the multi-pass data processing circuit of FIG. 5.

FIG. 7 is a block diagram illustrating an embodiment for implementing various data processing methods by the multi-pass data processing circuit of FIG. 1.

FIG. 8 is a diagram depicting an embodiment of a protocol data unit processed by the multi-pass data processing circuit of FIG. 7.

FIG. 9 is a signal diagram illustrating an embodiment of implementing a CRC (Cyclic redundancy check) using the multi-pass data processing circuit of FIG. 7

FIG. 10 is a block diagram illustrating an embodiment of an electronic device including a multi-pass data processing system.

Detailed Description

For a sufficient understanding of the objects, features and effects of the present disclosure, the present disclosure will be described in detail by specific embodiments with reference to the accompanying drawings.

Various embodiments of the present invention are described in more detail below with reference to the accompanying drawings. It is to be noted, however, that the present invention may be embodied in different forms and modifications, and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

In the following, various embodiments provide a multi-pass data processing circuit that can be applied to an electronic device that employs a multi-pass technique.

According to an embodiment, a multi-lane data processing circuit includes a plurality of lane circuit blocks and a plurality of registers.

The plurality of lane circuit modules are coupled to a plurality of lanes of the data interface, e.g., first through nth lanes, where N is 2, 3, 4, or greater. The plurality of pass circuit blocks may include first to nth pass circuit blocks for first to nth passes. Each of the first through nth pass circuit blocks may include first through mth processing circuits, where M is an integer greater than or equal to 2. The first to mth processing circuits may have different processing functions.

The plurality of registers may include first to Mth registers. When performing a specific data processing, the pth register may operate using a pth processing circuit within each of the first through nth pass circuit blocks, where P is an integer from 1 through M.

In the circuit arrangement, the first processing circuits within each of the first through nth path circuit blocks for the first through nth paths may be cascaded. Between two adjacent first processing circuits among the first processing circuits of the first to nth path circuit modules, an output terminal of one processing circuit is coupled to an input terminal of the other processing circuit. Among the cascaded first processing circuits of the first through nth pass circuit blocks, the first and last ones are coupled to a first register among the first through mth registers. Similarly, it is also possible to cascade pth processing circuits of the first to nth path circuit blocks for the first to nth paths to realize a circuit arrangement similar to the first processing circuits of the first to nth path circuit blocks.

The above-described embodiments can be applied to an electronic device that employs a multi-pass technology, and implement a data processing circuit having a circuit structure of relatively low complexity, thereby satisfying the requirements of a plurality of versions of electronic devices in which transmission frequency bandwidths of data interfaces are different from each other. When the multi-channel technology is adopted, a designer can arrange a relatively large number of channels according to the data interface circuit of the electronic product of the version with the relatively small transmission frequency bandwidth, so that the data interface circuit of the electronic product of the version with the relatively large transmission frequency bandwidth is obtained. The structure of the multi-channel data processing circuit can be applied to a data processing circuit corresponding to a data interface circuit in an electronic product. The structure of the multi-pass data processing circuit may implement the data processing circuit of the data interface circuit between or among two or more elements or modules within an electronic product.

For example, since an electronic product serving as a data storage device performs necessary processing according to data transmitted or received from a data interface, first to mth processing circuits required for the first to nth path circuit blocks of the respective first to nth paths in the multi-path data processing circuit may be arranged. For example, the electronic product performs processing such as data processing of a physical layer, a data link layer, a network layer, or other layers in the OSI (open system interconnection) model, or other data processing that is randomly necessary by hardware circuits, and the embodiment is not limited thereto.

First to nth path circuit blocks corresponding to first to nth paths in the data interface may be arranged, and a pth processing circuit within each of the first to nth path circuit blocks for the first to nth paths may be cascaded, where P is an integer from 1 to M. The first and last ones of the cascaded pth processing circuits within the respective first through nth pass circuit modules are arranged so as to be coupled to a pth register among the first through mth registers.

Thus, the multi-path data processing circuit may be implemented in an electronic product. In this way, the structure of the multi-path data processing circuit can satisfy the demand for circuit arrangements of a plurality of versions of electronic products having transmission frequency bandwidths of data interfaces whose sizes are different from each other. The multi-channel data processing circuit according to the embodiment not only can have relatively low complexity, but also can have excellent expansibility, thereby being beneficial to improving the development efficiency of electronic products and reducing the development cost of the electronic products.

Hereinafter, a multi-pass data processing circuit will be described with reference to a plurality of embodiments as follows.

FIG. 1 is a block diagram illustrating an embodiment of a multi-pass data processing circuit. As shown in fig. 1, the multi-path data processing circuit 1 includes a plurality of path circuit blocks (e.g., 10 and 20) and a plurality of registers (e.g., 91, 92, and 93). The plurality of lane circuit modules are coupled to a plurality of lanes of the data interface, for example, two lanes LD1 and LD2, and include lane circuit module 10 and lane circuit module 20.

Each of the pass circuit modules includes a first processing circuit (e.g., 101 or 201) and a second processing circuit (e.g., 102 or 202). In an embodiment, each of the pass circuit modules may further include a third processing circuit (e.g., 103 or 203).

Each processing circuit within each of the pass circuit modules has an input terminal and an output terminal, and the present embodiment is not limited to the number and arrangement of the input terminals and the output terminals. For example, the processing circuit may have one or more input terminals arranged to receive data of the respective lanes or to receive an output from another processing circuit, and one or more output terminals arranged to output data to the respective registers among the first to mth registers, or to output data to an input terminal of another processing circuit, or to serve as an output terminal of the respective lane of the pth processing circuit, according to necessity of data processing. Here, P is an integer from 1 to M. As shown in fig. 1, the first processing circuit 101 of the via circuit module 10 has an output terminal coupled to the first processing circuit 201 of the via circuit module 20, the second processing circuit 102 of the via circuit module 10 has an output terminal coupled to the second processing circuit 202 of the via circuit module 20, and the third processing circuit 103 of the via circuit module 10 has an output terminal coupled to the third processing circuit 203 of the via circuit module 20.

The first to mth registers include a first information register 91 and a second information register 92. First information register 91 has an input terminal coupled to first processing circuit 201 of pass circuit module 20, and an output terminal coupled to first processing circuit 101 of pass circuit module 10. Second information register 92 has an input terminal coupled to second processing circuit 202 of pass circuit module 20, and an output terminal coupled to second processing circuit 102 of pass circuit module 10. In an embodiment, the plurality of registers may further include a third information register 93, and the third information register 93 has an input terminal coupled to the third processing circuit 203 of the pass circuit module 20, and an output terminal coupled to the third processing circuit 103 of the pass circuit module 10.

FIG. 2 is a diagram for describing an embodiment of parallel processing of data by the multi-pass data processing circuit of FIG. 1. As shown in fig. 2, Q data sets represented by PA _ PDU0 to PA _ PDUQ-1 are input in parallel to the multi-path data processing circuit 1 of fig. 1 through the two paths LD1 and LD2 of the data interface, thereby processing data in parallel. Here, Q is an integer greater than or equal to 2. Referring to fig. 1 and 2, data sets PA _ PDU0 and PA _ PDU1 of the data sets PA _ PDU0 through PA _ PDUQ-1 are input to the pass circuit modules 10 and 20 in parallel to process data. Then, the data sets PA _ PDU2 and PA _ PDU3 are input to the lane circuit blocks 10 and 20 in parallel to process the data. In this way, the final data sets PA _ PDUQ-2 and PA _ PDUQ-1 are also input to the pass-through circuit modules 10 and 20 in parallel to process the data. By such processing, data processing efficiency can be improved.

FIG. 3 is a block diagram illustrating another embodiment of the multi-pass data processing circuit of FIG. 1. As shown in fig. 3, the multi-pass data processing circuit 1A of fig. 3 may further include a pass circuit block 30, as compared to the multi-pass data processing circuit 1 of fig. 1 including the pass circuit blocks 10 and 20. The multi-path data processing circuit 1A can be applied to an electronic product employing a data interface for three paths.

As shown in fig. 3, the first processing circuit 201 of the pass circuit module 20 has an output terminal coupled to the first processing circuit 301 of the pass circuit module 30, and the second processing circuit 202 of the pass circuit module 20 has an output terminal coupled to the second processing circuit 302 of the pass circuit module 30. In an embodiment, the third processing circuit 203 of the pass circuit module 20 has an output terminal coupled to the third processing circuit 303 of the pass circuit module 30.

As shown in fig. 3, the input terminal of the first information register 91 is coupled to the first processing circuit 301 of the pass circuit module 30. When compared to fig. 1, the input terminal of the first information register 91 is coupled to the first processing circuit 201 of the pass circuit module 20 through the first processing circuit 301 of the pass circuit module 30, and the input terminal of the second information register 92 is coupled to the second processing circuit 302 of the pass circuit module 30. When compared to fig. 1, the input terminal of the second information register 92 is coupled to the second processing circuit 202 of the pass circuit module 20 through the second processing circuit 302 of the pass circuit module 30. In an embodiment, the input terminal of the third information register 93 is coupled to the third processing circuit 303 of the pass circuit module 30. When compared to fig. 1, the input terminal of the third information register 93 is coupled to the third processing circuit 203 of the pass circuit module 20 through the third processing circuit 303 of the pass circuit module 30.

FIG. 4 is a diagram for describing an embodiment of parallel processing of data by the multi-pass data processing circuit of FIG. 3. Referring to fig. 4, Q data sets represented by PA _ PDU0 to PA _ PDUQ-1 are input in parallel to the multi-lane data processing circuit 1A of fig. 3 through three lanes LD1, LD2, and LD3 of the data interface, thereby processing data in parallel. Here, Q is an integer greater than or equal to 3. Referring to fig. 3 and 4, data sets PA _ PDU0 to PA _ PDU2 among the data sets PA _ PDU0 to PA _ PDUQ-1 are input to the pass circuit modules 10, 20, and 30 in parallel to process data. Then, the data sets PA _ PDU3 to PA _ PDU5 are input to the pass circuit modules 10, 20, and 30 in parallel to process the data. In this way, the final data sets PA _ PDUQ-3 and PA _ PDUQ-1 are also input to the pass-through circuit blocks 10, 20 and 30 in parallel to process the data. By such processing, data processing efficiency can be improved.

FIG. 5 is a block diagram illustrating another embodiment of the multi-pass data processing circuit of FIG. 1. As shown in fig. 5, the multi-pass data processing circuit 1B of fig. 5 may further include a pass circuit block 40, as compared to the multi-pass data processing circuit 1A of fig. 3 including the pass circuit blocks 10, 20, and 30. The multi-path data processing circuit 1B can be applied to an electronic product employing a data interface for four paths.

As shown in fig. 5, the first processing circuit 301 of the pass circuit module 30 has an output terminal coupled to the first processing circuit 401 of the pass circuit module 40, and the second processing circuit 302 of the pass circuit module 30 has an output terminal coupled to the second processing circuit 402 of the pass circuit module 40. In an embodiment, the third processing circuit 303 of the pass circuit module 30 has output terminals that are electrically coupled to the third processing circuit 403 of the pass circuit module 40.

As shown in fig. 5, the input terminal of the first information register 91 is coupled to the first processing circuit 401 of the pass circuit module 40. When compared to fig. 1, the input terminal of the first information register 91 is coupled to the first processing circuit 201 of the pass circuit module 20 through the first processing circuit 401 of the pass circuit module 40 and the first processing circuit 301 of the pass circuit module 30, and the input terminal of the second information register 92 is coupled to the second processing circuit 402 of the pass circuit module 40. When compared to fig. 1, the input terminal of the second information register 92 is coupled to the second processing circuit 202 of the pass circuit module 20 through the second processing circuit 402 of the pass circuit module 40 and the second processing circuit 302 of the pass circuit module 30. In an embodiment, an input terminal of the third information register 93 is coupled to the third processing circuit 403 of the pass circuit module 40. When compared to fig. 1, the input terminal of the third information register 93 is coupled to the third processing circuit 203 of the pass circuit module 20 through the third processing circuit 403 of the pass circuit module 40 and the third processing circuit 303 of the pass circuit module 30.

FIG. 6 is a diagram for describing an embodiment of parallel processing of data by the multi-pass data processing circuit of FIG. 5. Referring to fig. 6, Q data sets represented by PA _ PDU0 to PA _ PDUQ-1 are input in parallel to the multi-path data processing circuit 1B of fig. 5 through the four paths LD1 to LD4 of the data interface, thereby processing data in parallel. Here, Q is an integer greater than or equal to 4. Referring to fig. 5 and 6, data sets PA _ PDU0 to PA _ PDU3 among the data sets PA _ PDU0 to PA _ PDUQ-1 are input to the pass circuit modules 10, 20, 30 and 40 in parallel to process data. Then, the data sets PA _ PDU4 to PA _ PDU7 are input to the pass circuit modules 10, 20, 30 and 40 in parallel to process the data. In this way, the final data sets PA _ PDUQ-4 and PA _ PDUQ-1 are also input to the pass-through circuit blocks 10, 20, 30 and 40 in parallel to process the data. By such processing, data processing efficiency can be improved.

FIG. 7 is a block diagram illustrating an embodiment for implementing various data processing methods by the multi-pass data processing circuit of FIG. 1. As shown in fig. 7, the multi-path data processing circuit 1C includes a plurality of path circuit blocks (e.g., 10C and 20C) and a plurality of registers (e.g., 91C, 92C, and 93C). The plurality of lane circuit modules are coupled to a plurality of lanes of the data interface, e.g., two lanes LD1 and LD2, and include lane circuit module 10C and lane circuit module 20C. Each of the pass circuit modules includes a first processing circuit (e.g., 101C or 201C) and a second processing circuit (e.g., 102C or 202C). In an embodiment, each of the pass circuit modules may further include a third processing circuit (e.g., 103C or 203C).

The first processing circuit 101C or 102C includes two or more input terminals. As shown in fig. 7, one input terminal of first processing circuit 101C is for receiving data from path LD1, and the other input terminal of first processing circuit 101C is for receiving an output from first information register 91C. One input terminal of first processing circuit 201C is for receiving data from path LD2 and the other input terminal of first processing circuit 201C is for receiving processed data from first processing circuit 101C.

The first processing circuit 101C or 201C includes two or more output terminals. As shown in fig. 7, one output terminal of the first processing circuit 101C is used to transmit the processed data of the first processing circuit 101C to the first processing circuit 201C, and the other output terminal of the first processing circuit 101C is used to output the processing result (e.g., represented by PU1_ LD1_ R) of the first processing circuit 101C, so that the subsequent circuit of the electronic product uses or processes the processing result.

One output terminal of the first processing circuit 201C is used to output the processed data of the first processing circuit 201C to the first information register 91C, and the other output terminal of the first processing circuit 201C is used to output the processing result (for example, represented by PU1_ LD2_ R) of the first processing circuit 201C, so that the subsequent circuit of the electronic product uses or processes the processing result. The second processing circuit 102C or 202C or the third processing circuit 103C or 203C may also be implemented in a similar manner.

As shown in fig. 7, the processing results of the second processing circuits 102C and 202C are respectively represented by PU2_ LD1_ R and PU2_ LD2_ R, and the processing results of the third processing circuits 103C and 203C are respectively represented by PU3_ LD1_ R and PU3_ LD2_ R.

The plurality of registers 91C to 93C of the multichannel data processing circuit 1C shown in fig. 7 are controlled by a clock signal CLK.

As shown in fig. 7, in an embodiment, each of the pass circuit modules may further include a control circuit (e.g., 111C or 211C), and the control circuit is coupled to the plurality of processing circuits corresponding to the pass circuit modules. For example, in fig. 7, the control circuit 111C is coupled to the first processing circuit 101C, the second processing circuit 102C, and the third processing circuit 103C corresponding to the pass circuit module 10C, and the control circuit 211C is coupled to the first processing circuit 201C, the second processing circuit 202C, and the third processing circuit 203C corresponding to the pass circuit module 20C. The control circuit corresponding to the pass circuit module selectively enables or disables one or more of the plurality of processing circuits corresponding to the pass circuit module in accordance with a pass control signal (e.g., SCL1 or SCL 2). For example, in fig. 7, the control circuit 111C selectively enables or disables one or more of the first processing circuit 101C, the second processing circuit 102C, and the third processing circuit 103C corresponding to the pass circuit module 10C according to the pass control signal SCL 1. Control circuit 211C may also be similarly applied to pass circuit block 20C.

In the embodiment of fig. 7, the first processing circuits 101C and 102C are implemented using CRC (cyclic redundancy check) circuits. A CRC is a hash function used to generate a verification code having a small fixed number of bits from data such as a network data frame, data packet, or computer file. For example, the CRC is used to detect or check errors that may occur after the data is transmitted or stored. When there is data to be transmitted or stored, the first processing circuit may calculate a check code through the CRC and attach the check code to the rear of the data. Then, the first processing circuit on the receiver side may perform the same CRC operation and check whether the check codes coincide with each other in order to check whether a change has occurred in the data. For example, the first processing circuits 101C and 201C are implemented by CRC circuits conforming to the international standard CCITT CRC-16.

The second processing circuit 102C or 202C may implement another data processing. For example, the second processing circuit 102C or 202C may calculate the total number of data traffic, or packets or frames, in the data interface. The third processing circuit 103C or 203C may implement another data processing. However, the present embodiment is not limited to such an example.

Returning to fig. 7, when the path control signal SCL1 or SCL2 indicates that the first processing is to be performed, the control circuits 111C and 211C of the plurality of path circuit modules 10C and 20C enable the first processing circuits 101C and 201C of the plurality of path circuit modules and couple the first processing circuits 101C and 201C of the plurality of path circuit modules to the respective paths LD1 and LD2, thereby processing different data sets of the plurality of paths in parallel. For example, the pass control signal may indicate that the first processing circuit is enabled and that the second and third processing circuits are disabled.

The lane control signals may also indicate different combinations to enable or disable one or more processing circuits in a lane circuit block corresponding to the same lane. For example, when the path control signal SCL1 or SCL2 indicates that the first process and the second process are performed, the first and second processing circuits of the plurality of path circuit blocks perform the first and second processes. Further, the CRC is performed by the first processing circuit, and other data processing, such as processing of calculating the data traffic or the total number of packets or frames in the data interface, is performed simultaneously by the second processing circuit.

FIG. 8 is a diagram depicting an embodiment of a PDU (protocol data unit) processed by the multi-pass data processing circuit of FIG. 7. As shown in fig. 8, block 800 represents a frame or packet including data characters 1 through 9, A, B, and C. Further, the block 850 represents a data set expressed as a plurality of hexadecimal codes corresponding to the frame, and includes, for example, data sets of 0x1017 to 0x1012A and 0x04a 20. Among the data sets, the last data set 0x04a20 is a check code generated by CRC based on CCITT CRC-16, which is performed on the data sets 0x1017 to 0x 1012A.

Here, it is assumed that the block 850 serving as a data set expressed as a plurality of hexadecimal codes corresponding to the frame is transmitted from the transmitter side to the receiver side, and the multi-pass data processing circuit 1C of fig. 7 verifies the accuracy of the data on the receiver side.

FIG. 9 is a signal diagram illustrating an embodiment of implementing CRC by the multi-pass data processing circuit of FIG. 7. As shown in fig. 7, 8 and 9, in the case of the clock signal CLK represented by the signal 901, a plurality of data sets of a frame represented by the block 850 are input in parallel to the multi-path data processing circuit 1C of fig. 7 through the two paths LD1 and LD2 of the data interface so as to process data in parallel. As indicated by signals 904 and 907, the two data sets (e.g., 0x10107 and 0x08284) of the frame represented by block 850 are input in parallel to the first processing circuit 101C of the lane circuit module 10C and the first processing circuit 201C of the lane circuit module 20C to process the data. Then, two data sets (e.g., 0x03132 and 0x03334) are input to the first processing circuits 101C and 201C in a parallel manner to process the data. In this way, the last two data sets (e.g., 0x1012A and 0x04a20) are also input to the first processing circuits 101C and 201C in parallel to process the data.

As shown in fig. 9, the control circuits 111C and 211C output signals 902 and 906 to the first processing circuits 101C and 201C in accordance with the path control signals SCL1 and SCL2 in the case of the clock signal CLK represented by the signal 901, and selectively activate the first processing circuits 101C and 201C to process data. The high level of signals 902 and 906 indicates enable and the low level of signals 902 and 906 indicates disable.

Data of the output terminal and the input terminal of the first information register 91C are represented by signals 903 and 908, respectively, and 0xFFFF of the data represents an initial value of the output terminal of the first information register 91C.

The processing results PU1_ LD1_ R and PU1_ LD2_ R of the first processing circuits 101C and 201C are represented by signals 905 and 909, respectively. As shown in fig. 9, a signal 909 corresponding to the processing result PU1_ LD2_ R of the first processing circuit 201C is expressed as an accurate pulse wave signal (for example, high level) in the final output of the calculation because an accurate result is obtained by the CRC. However, the present embodiment is not limited to such an example.

For example, the frame of block 800 may be data processed by various layers such as a transport layer, a network layer, and/or a data link layer, although the disclosure is not limited thereto. As shown in fig. 8, block 800 represents data included in a frame, as an example. For example, the frame 800 includes a head 801, a body 803, and a foot 805. The header 801 includes fields ESC _ DL, SOF, TC, and RSD. ESC _ DL denotes a specific code for distinguishing a control code from a data code, and SOF denotes a code indicating such a control code to start a new frame. The TCs define information traffic or priority and are set to one of a plurality of different information traffic, such as TC 0. RSD denotes a reserved field. The header 801 may also include a network layer indication 811 and network layer information 813. For example, when the network layer indication 811 (e.g., represented by L3S) is set to 1, it indicates that the frame includes information of the network layer L3. Network layer information 813 (e.g., represented by DestDeviceID _ ENC) is an identification ID or address of the destination device indicating the device to which the protocol data unit is to be transferred. The header 801 also includes a transport layer indication value 815 (e.g., represented by L4S) indicating that transport layer information (i.e., L4) is also present in the protocol data unit. The header 801 includes a port identification value 817 (e.g., represented by DestCPortID _ ENC), which port identification value 817 determines to which port of the destination device the data of the L4 information corresponds, and also includes a flow control flag bit (e.g., represented by FCT) of the L4 information. The end-to-end connection may be identified based on DestCPortID ENC and DestDeviceID ENC. The header 801 may also include an end bit (e.g., represented by an EOM) that indicates whether the frame is the last message of the transport layer. The body 803 includes user or application data to be transmitted. The foot 805 may include a check code generated by CRC based on CCITT CRC-16 and further includes fields ESC _ DL, EOF _ EVEN, and FSN. EOF _ EVEN indicates the last control code of the frame and FSN indicates the frame sequence number, which is the sequence number when the data link layer is transmitting. However, the present embodiment is not limited to such an example.

In some embodiments, the multi-pass data processing circuit 1C of fig. 7 may be additionally extended to a multi-pass data processing circuit suitable for three-pass, four-pass, or other number of passes, by referring to the circuit arrangement of fig. 3 or 5, in order to increase the data frequency bandwidth. Therefore, the multi-channel data processing circuit can meet the requirement on the data frequency bandwidth of the electronic product realized based on the multi-channel data processing circuit.

FIG. 10 is a block diagram illustrating an embodiment of a multi-pass data processing system using an electronic device. As shown in fig. 10, the electronic apparatus 2 and the electronic apparatus 9 perform communication or data transmission, and the electronic apparatus 2 is a data interface based on a plurality of paths (two or more paths) and includes a multi-path data processing system (e.g., 1000 or 2000). The electronic device 2 is a data processing circuit, a communication device, a storage device, etc., the electronic device 9 is a smartphone, a wearable device, a tablet computer, a notebook computer, a desktop computer, a server, or other random computing device, and the data interface is USB, SATA, or other randomly suitable data interface installed inside or outside the computer. The electronic devices 2 and 9 may be implemented as part of an electronic system. As shown in fig. 10, the electronic device 2 includes system modules 1300 and a system memory 1400. For example, the electronic apparatus 2 may be implemented as a memory device such as a memory card or a storage device such as a solid state disk, and the electronic apparatus 9 may be implemented as a network device. In some embodiments, the electronic devices 2 and 9 may be implemented as two or more elements or modules inside the electronic product. However, the present embodiment is not limited to such an example.

The multi-pass data processing system 1000 or 2000 includes a plurality of physical layer circuit blocks (e.g., 1101 and 1102 or 2101 and 2102) and a multi-pass data processing circuit. The multi-lane data processing circuit includes a plurality of lane circuit blocks (e.g., 1201 and 1202 or 2201 and 2202) and a plurality of registers. When the plurality of via circuit modules 1201 and 1202 or 2201 and 2202 and the plurality of registers are the plurality of via circuit modules and the plurality of registers corresponding to at least one of the plurality of embodiments of the multi-via data processing circuit described above (e.g., fig. 1, 3, 5, and 7) or a combination thereof, the plurality of via circuit modules are electrically coupled to the respective vias through the plurality of physical layer circuit modules. For example, each lane is configured to carry a differential signal pair.

In an embodiment, when the lane control signal indicates that any one of the processes is to be performed, the control circuit of the plurality of lane circuit modules enables the plurality of lane circuit modules and the circuit processing circuit corresponding to the process, couples the plurality of lane circuit modules and the processing circuit corresponding to the process to the plurality of lanes through the plurality of physical layer circuit modules, respectively, and processes different data sets of the plurality of lanes in a parallel manner, as shown in fig. 2, 4, 6, or 9.

As shown in fig. 10, in an embodiment, the plurality of physical layer circuit modules (e.g., 1101 and 1102) are transmitter physical layer circuits. In an embodiment, the plurality of physical layer circuit modules 2101 and 2102 are receiver physical layer circuits. In fig. 10, each of the transmitter and receiver stages in the electronic device 2 uses two lanes. However, the present embodiment is not limited to such an example. In some embodiments, the electronic device 2 may be configured in such a way that: such that each of the transmitter stage and the receiver stage uses a first number of lanes and a second number of lanes. The first number and the second number may be the same as or different from each other, and at least one of the first number and the second number may be equal to or greater than 2. According to the embodiments of the multi-pass data processing circuit in fig. 1, 3, 5 and 7, a data processing circuit suitable for an electronic device according to the present embodiment can be realized.

For example, referring to fig. 7-9 and related embodiments, the physical layer circuit modules 2101 and 2102 of fig. 10 may be configured to process data sets from two or more lanes (see fig. 8 and 9). Physical layer circuit modules 2101 and 2102 may then transfer the processed data sets to pass circuit modules 2201 and 2202 implemented according to the embodiment of FIG. 7 to perform CRC according to the above embodiments, or to perform CRC in parallel, and computation of the sum of data traffic and packets or frames. Similarly, the lane circuit modules 1201 and 1202 of fig. 10 may be configured to process data sets of two or more lanes provided from the system module 1300. Then, the pass circuit blocks 1201 and 1202 may transfer the data processed by the CRC or the like to the physical layer circuit blocks 1101 and 1102 so as to transfer the data to the pass.

Accordingly, a data processing circuit applicable to an electronic device employing a multi-pass technology and having a circuit structure of relatively low complexity can be realized to provide various embodiments of a multi-pass data processing circuit and system capable of satisfying the demands of electronic products of multiple versions having data interfaces whose transmission frequency bandwidths are different from each other. The multi-channel data processing circuit and the multi-channel data processing system according to the embodiment not only can have relatively low complexity, but also can have excellent expandability, thereby being beneficial to improving the development efficiency of electronic products and reducing the development cost of the electronic products.

In embodiments related to multi-pass data processing circuitry, one or more of the multi-pass data processing circuitry, pass circuit modules, processing circuitry, information registers, and control circuitry may be implemented using one or more logic gates, logic circuits, digital circuits, or other circuitry, using programmable integrated circuits such as FPGAs (field programmable gate arrays) or circuits such as ASICs (application specific integrated circuits), or using application specific circuits or modules. However, the present embodiment is not limited to such an example.

Therefore, the above-described embodiments may be applied to an electronic device adopting a multi-pass technology, and may implement a data processing circuit having a circuit structure of relatively low complexity to provide various embodiments of a multi-pass data processing circuit and system capable of satisfying the demand of electronic products of a plurality of versions having transmission frequency bandwidths of data interfaces different from each other. The multi-channel data processing circuit and the multi-channel data processing system according to the embodiment not only can have relatively low complexity, but also can have excellent expandability, thereby being beneficial to improving the development efficiency of electronic products and reducing the development cost of the electronic products.

While various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples. Accordingly, the multi-pass data processing circuits and systems described herein should not be limited based on the described embodiments.