阅读说明：本技术 实现i2c通讯的方法和滑板车及存储介质 (Method for realizing I2C communication, scooter and storage medium ) 是由 不公告发明人 于 2019-11-26 设计创作，主要内容包括：本发明公开了一种实现I2C通讯的方法、滑板车和存储介质,其中,实现I2C通讯的方法包括：建立层次状态机；采用所述层次状态机执行I2C通讯的读写函数以实现模拟I2C通讯时序,其中,I2C通讯的读写函数在场定向控制FOC中断下执行,且两次所述场定向控制FOC中断的间隔时间设置为所述读写函数的时序信号。本发明的实现I2C通讯的方法和滑板车,可以实现模拟主机I2C通讯,并且不会打断场定向控制FOC中断函数以及可以提高系统效率。(The invention discloses a method for realizing I2C communication, a scooter and a storage medium, wherein the method for realizing I2C communication comprises the following steps: establishing a hierarchical state machine; and executing a read-write function of I2C communication by adopting the hierarchical state machine to realize simulation of I2C communication time sequence, wherein the read-write function of I2C communication is executed under field-oriented control (FOC) interruption, and the interval time between two times of field-oriented control (FOC) interruption is set as a time sequence signal of the read-write function. The method for realizing I2C communication and the scooter can realize the communication of the analog host I2C, do not interrupt the FOC interruption function of field-oriented control and improve the system efficiency.)

1. A method for implementing I2C communication, comprising:

establishing a hierarchical state machine;

and executing a read-write function of I2C communication by adopting the hierarchical state machine to realize simulation of I2C communication time sequence, wherein the read-write function of I2C communication is executed under field-oriented control (FOC) interruption, and the interval time between two times of field-oriented control (FOC) interruption is set as a time sequence signal of the read-write function.

2. The method of claim 1 for enabling I2C communication, the method further comprising:

when the read-write function is successfully executed, setting a read-write success flag bit;

in the main loop task of the main function, when the read-write success flag bit is identified, the flag bit is cleared, and the processing task of I2C communication data is executed.

3. The method of claim 1, wherein the hierarchical state machine comprises a plurality of parent states, the parent states comprise a plurality of child states, and wherein performing read-write functions of I2C communication using the hierarchical state machine to achieve simulated I2C communication timing comprises:

when the hierarchical state machine is initialized, the father state is set as an idle father state;

when a communication demand is received, converting the father state into a START father state;

in the START parent state, a child state in the START parent state transmits a START signal, and after the START signal transmission is completed, the parent state is converted into a HEAD parent state.

4. The method of claim 3, wherein the performing the read-write function of the I2C communication by using the hierarchical state machine to simulate the I2C communication timing further comprises:

in the HEAD father state, the son state sends the slave device address and the read-write control bit;

and after the slave device address and the read-write control bit are sent, the father state is converted into a WAIT _ ACK father state.

5. The method of claim 4, wherein the performing the read-write function of the I2C communication by using the hierarchical state machine to simulate the I2C communication timing further comprises:

in the WAIT _ ACK parent state, acquiring SDA data in a child state, and confirming whether slave equipment responds according to the SDA data;

if the slave device does not respond, the parent state transitions to a STOP parent state;

and if the slave device has a response, the father state is converted into a READ _ DATA father state or a WRITE _ DATA father state according to the READ-WRITE control bit.

6. The method of claim 5, wherein the performing the read-write function of the I2C communication by using the hierarchical state machine to simulate the I2C communication timing further comprises:

in the parent state of the READ _ DATA, moving SDA DATA into a READ-write cache of I2C, and if complete SDA DATA is received, converting the parent state into an ACK _ DATA parent state;

in the ACK _ DATA parent state, after a child state sends an ACK signal, the parent state is converted into the READ _ DATA parent state again; or, in the ACK _ DATA parent state, after a sub-state in the ACK _ DATA parent state transmits a NACK signal, the parent state is converted into a STOP parent state.

7. The method of claim 5, wherein the performing the read-write function of the I2C communication by using the hierarchical state machine to simulate the I2C communication timing further comprises:

in the WRITE _ DATA father state, shifting the highest bit of DATA to be transmitted into an SDA (DATA-to-DATA architecture) to transmit the highest bit of DATA to a slave device, shifting the DATA to be transmitted to supplement the highest bit of DATA after each time of transmitting the highest bit of DATA, shifting the highest bit of DATA into the SDA again to transmit the highest bit of DATA to the slave device until the DATA to be transmitted is transmitted, and converting the father state into the WAIT _ ACK father state after the DATA to be transmitted is transmitted to the slave device;

and if the ACK signal is detected, the father state is converted into a WRITE _ DATA father state again, and if the ACK signal is not received or the DATA needing to be transmitted is transmitted completely, the father state is converted into a STOP father state.

8. The method of claim 7, wherein the performing the read-write function of the I2C communication by using the hierarchical state machine to simulate the I2C communication timing further comprises:

in the STOP parent state, a child state generates a STOP signal and the parent state transitions to an idle parent state.

9. The method for implementing I2C communication according to any one of claims 3-8, wherein each time the incoming field-oriented control FOC is interrupted, the child state of the current parent state is automatically switched to the next child state.

10. A non-transitory computer storage medium having stored thereon a computer program that, when executed, implements the method of implementing I2C communication of any of claims 1-9.

11. A scooter, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor, the instructions, when executed by the at least one processor, cause the at least one processor to perform the method of implementing I2C communication of any of claims 1-9.

Technical Field

The invention relates to the technical field of vehicle manufacturing, in particular to a method for realizing I2C communication, a scooter adopting the method and a storage medium.

Background

Due to the limited hardware resources of the chip, when the hardware resources of the communication port of the single chip microcomputer are occupied and communication with other equipment is required, the communication is generally realized by simulating the communication of the I2C through an I/O (Input/Output) port. The program for simulating the communication of the host I2C, the conventional I2C clock pulse is realized by a delay function or an interrupt function, and since the priority of the FOC (Field Oriented Control) interrupt in the system is the highest, the FOC interrupt will often interrupt the delay function or the interrupt function of I2C, which results in inaccuracy of the delay function (clock tick) of I2C; furthermore, the I2C function is implemented within the main function, and if the clock ticks are implemented by a delay function, the system is inefficient because the I2C function takes too much time because the main function is executed sequentially.

Disclosure of Invention

The present invention is directed to solving at least one of the problems of the prior art. To this end, an object of the present invention is to provide a method for implementing I2C communication, which can implement analog host I2C communication, and does not interrupt the FOC interrupt function and can improve the system efficiency.

A second object of the invention is to propose a non-transitory computer storage medium.

The third purpose of the invention is to provide a scooter.

In order to achieve the above object, a method for implementing I2C communication according to an embodiment of the first aspect of the present invention includes: establishing a hierarchical state machine; and executing a read-write function of I2C communication by adopting the hierarchical state machine to realize simulation of I2C communication time sequence, wherein the read-write function of I2C communication is executed under field-oriented control (FOC) interruption, and the interval time between two times of field-oriented control (FOC) interruption is set as a time sequence signal of the read-write function.

According to the method for realizing I2C communication, the I2C communication time sequence is simulated by adopting a layered state machine, so that the optimization of the execution efficiency is facilitated, the utilization rate of a processor is improved, the read-write function of I2C communication is executed under the interruption of field-oriented control FOC instead of being executed in a main function, and the interval time of the interruption of the field-oriented control FOC for two times is set as the time sequence signal of the read-write function, so that the interruption of the FOC is avoided, the influence on the execution efficiency of the main function due to the delay of the I2C function is avoided, and the improvement of the system efficiency is facilitated.

In some embodiments, the method further comprises: when the read-write function is successfully executed, setting a read-write success flag bit; in the main loop task of the main function, when the read-write success flag bit is identified, the flag bit is cleared, and the processing task of I2C communication data is executed.

In some embodiments, the hierarchical state machine includes a plurality of parent states, the parent states include a plurality of child states, and performing a read-write function of the I2C communication with the hierarchical state machine to achieve the simulated I2C communication timing includes: when the hierarchical state machine is initialized, the father state is set as an idle father state; when a communication demand is received, the parent state is converted into a START parent state, in the START parent state, a child state in the START parent state transmits a START signal, and after the START signal is transmitted, the parent state is converted into a HEAD parent state.

In some embodiments, said performing read and write functions of I2C communication using said hierarchical state machine to achieve simulated I2C communication timing further comprises: in the HEAD father state, the son state sends the slave device address and the read-write control bit; and after the slave device address and the read-write control bit are sent, the father state is converted into a WAIT _ ACK father state.

In some embodiments, said performing read and write functions of I2C communication using said hierarchical state machine to achieve simulated I2C communication timing further comprises: in the WAIT _ ACK parent state, acquiring SDA data in a child state, and confirming whether slave equipment responds according to the SDA data; if the slave device does not respond, the parent state transitions to a STOP parent state; and if the slave device has a response, the father state is converted into a READ _ DATA father state or a WRITE _ DATA father state according to the READ-WRITE control bit.

In some embodiments, said performing read and write functions of I2C communication using said hierarchical state machine to achieve simulated I2C communication timing further comprises: in the parent state of the READ _ DATA, moving SDA DATA into a READ-write cache of I2C, and if complete SDA DATA is received, converting the parent state into an ACK _ DATA parent state; in the ACK _ DATA parent state, after a child state sends an ACK signal, the parent state is converted into the READ _ DATA parent state again; or, in the ACK _ DATA parent state, after a sub-state in the ACK _ DATA parent state transmits a NACK signal, the parent state is converted into a STOP parent state.

In some embodiments, said performing read and write functions of I2C communication using said hierarchical state machine to achieve simulated I2C communication timing further comprises: in the WRITE _ DATA father state, shifting the highest bit of DATA to be transmitted into an SDA (DATA-to-DATA architecture) to transmit the highest bit of DATA to a slave device, shifting the DATA to be transmitted to supplement the highest bit of DATA after each time of transmitting the highest bit of DATA, shifting the highest bit of DATA into the SDA again to transmit the highest bit of DATA to the slave device until the DATA to be transmitted is completely transmitted, and converting the father state into the WAIT _ ACK father state after the DATA to be transmitted is transmitted to the slave device; and if the ACK signal is detected, the father state is converted into a WRITE _ DATA father state again, and if the ACK signal is not received or the DATA needing to be transmitted is transmitted completely, the father state is converted into a STOP father state.

In some embodiments, said performing read and write functions of I2C communication using said hierarchical state machine to achieve simulated I2C communication timing further comprises: in the STOP parent state, a child state generates a STOP signal and the parent state transitions to an idle parent state.

In an embodiment, each time the ingress oriented control FOC is interrupted, the child state of the current parent state automatically switches to the next child state.

The second aspect of the present invention provides a non-transitory computer storage medium, on which a computer program is stored, where the computer program is executed to implement the method for implementing I2C communication.

In order to achieve the above object, a scooter according to a third aspect of the present invention includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions, when executed by the at least one processor, cause the at least one processor to perform the method of implementing I2C communications.

According to the scooter provided by the embodiment of the invention, the instruction is stored in the memory and is executed by the processor, so that the method for realizing I2C communication in the embodiment can be realized, the execution efficiency can be improved, and the resource utilization rate of the processor can be improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a flow diagram of a method of implementing I2C communication, according to one embodiment of the invention;

FIG. 2 is a diagram showing the arrangement of the FOC interruption function, the I2C function and the main function in the field oriented control in the related art;

FIG. 3 is a schematic diagram of the parallel arrangement of the field oriented control FOC interrupt and the I2C function according to one embodiment of the present invention;

FIG. 4 is a schematic diagram of an idle parent state according to one embodiment of the invention;

FIG. 5 is a schematic diagram of a START parent status according to one embodiment of the invention;

FIG. 6 is a schematic diagram of the HEAD parent status according to one embodiment of the invention;

FIG. 7 is a schematic diagram of the WAIT _ ACK parent state according to one embodiment of the invention;

FIG. 8 is a schematic diagram of the READ _ DATA parent state, according to one embodiment of the invention;

FIG. 9 is a diagram of the ACK _ DATA parent state according to one embodiment of the invention;

FIG. 10 is a schematic diagram of the WRITE _ DATA parent state, according to one embodiment of the invention;

FIG. 11 is a schematic diagram of a STOP parent state according to one embodiment of the present invention;

fig. 12 is a block diagram of a scooter according to one embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below, the embodiments described with reference to the drawings being illustrative, and the embodiments of the present invention will be described in detail below.

A method of implementing I2C communication according to an embodiment of the present invention is described below with reference to fig. 1-11.

Fig. 1 is a flowchart of a method for implementing I2C communication according to an embodiment of the present invention, and as shown in fig. 1, the method for implementing I2C communication according to an embodiment of the present invention at least includes steps S1 and S2.

And S1, establishing a hierarchical state machine.

Specifically, the hierarchical State Machine classifies and extracts a plurality of states on the basis of a Finite State Machine (FSM), the states of the same type are taken as a parent State, the states in the parent State are respectively taken as child states, when the jump condition is met among the parent states, the State jump can be realized, when the jump condition is met among the child states in the parent State, the internal jump can be realized, and the child states among the parent states cannot jump, so that the execution steps can be simplified, and the execution efficiency is optimized.

And S2, executing a read-write function of the I2C communication by adopting a hierarchical state machine to realize simulation of I2C communication time sequence, wherein the read-write function of the I2C communication is executed under the interruption of the field-oriented control FOC of the motor, and the interval time of the interruption of the field-oriented control FOC is set as a time sequence signal of the read-write function.

Specifically, in the conventional practice, the I2C clock pulse is implemented by a delay function or an interrupt function, as shown in fig. 2, since the field-oriented control FOC interrupt enters every 125us because the field-oriented control FOC interrupt has the highest priority in the system, the field-oriented control FOC interrupt will often interrupt the delay function or interrupt function of I2C, resulting in inaccuracy of the delay function of I2C; and, the I2C function is executed in main functions, which are executed sequentially, thus resulting in low system efficiency due to the fact that the I2C function takes more time.

However, in the embodiment of the present invention, as shown in fig. 3, the read-write function of I2C communication is executed under the field-oriented control FOC interrupt, and the interval time between two field-oriented control FOC interrupts is set as the timing signal of the read-write function, so that the I2C function is not interrupted by the field-oriented control FOC interrupt, and thus the delay of the I2C function is not caused, and the task processing of the main function of main is not affected by the I2C function executed under the field-oriented control FOC interrupt, which is beneficial to improving the system efficiency.

According to the method for realizing the I2C communication, the read-write function of the I2C communication is executed by adopting the layered state machine to realize the simulation of the I2C communication time sequence, the optimization of the execution efficiency is facilitated, the utilization rate of a processor is improved, the read-write function of the I2C communication is executed under the interruption of the field-oriented control FOC instead of the main function, and the interval time of the two times of field-oriented control FOC interruption is set as the time sequence signal of the read-write function, so that the interruption of the field-oriented control FOC interruption is avoided, the influence on the execution efficiency of the main function due to the delay of the I2C function is avoided, and the improvement of the system efficiency is facilitated.

Furthermore, when the read-write function of the I2C communication is successfully executed, a read-write success flag bit is set; in the main loop task of the main function, when the read-write success flag bit is identified, the flag bit is cleared, and the processing task of I2C communication data is executed. Specifically, the read-write function of I2C communication is executed under the interruption of field oriented control FOC with the highest priority of frequency 8KHz (125us), the 125us is the SCL timing signal of I2C communication, because of using the state machine mode, the execution time of each time is only about 50ns, when the read-write function of I2C communication is executed successfully, the read-write success flag bit will be set, in the task cycle of main function 5ms, the program judges the read-write success flag bit of I2C, if set, the flag bit will be cleared, and the I2C data analysis and related processing tasks are executed, thereby, the task of once 5ms in the main function cycle will not be interrupted, and the processing efficiency is improved.

The following describes a process of implementing the simulated I2C communication by using a hierarchical state machine to execute the read/write function of the I2C communication according to an embodiment of the present invention.

Where the hierarchical state machine includes multiple parent states, in some embodiments, a complete DATA transfer may include an idle parent state, a START parent state, a HEAD parent state, a WAIT _ ACK parent state, a READ _ DATA parent state, a WRITE _ DATA parent state, an ACK _ DATA parent state, and a STOP parent state, with multiple child states included in the parent state. And, every time the incoming field oriented control FOC is interrupted, the child state in the current parent state will automatically transition to the next child state.

When the hierarchical state machine is initialized, the parent state is set to an IDLE parent state, for example, as shown in fig. 4, the hierarchical state machine is a schematic diagram of an IDLE parent state, that is, an IDLE state. When a communication demand is received, the parent state is converted into a START parent state, in the START parent state, a child state in the START parent state transmits a START signal, and after the START signal is transmitted, the parent state is converted into a HEAD parent state.

For example, fig. 5 is a schematic diagram illustrating a START parent state according to an embodiment of the present invention, and as shown in fig. 5, the START parent state includes three sub-states, sub-state 1: SDA is set as output, wherein SDA is 1, and SCL is 1; sub-state 2: when SDA is 0, a START signal is sent; substate 3: SCL ═ 0, START signaling is completed, and the parent state transitions to the HEAD parent state.

In the HEAD father state, the son state sends the slave device address and the read-write control bit; after the slave address and the read/write control bit are transmitted, the parent state is changed to the WAIT _ ACK parent state. For example, as shown in fig. 6, the transmission DATA includes 7 bits of slave Address +1 bits of R/W read/write control bits, i.e., DATA ═ 7bit Address +1bit R/W read/write bits, and in this state, three sub-states are included, where sub-state 1: move the most significant bit of DATA to be sent into SDA, substate 2: SCL ═ 1, substate 3: and SCL is 0, one bit of DATA is transmitted through the jump of the timing signal, the DATA is shifted by one bit to the left, three sub states are circulated until the 8-bit DATA is transmitted, and the father state is converted into the WAIT _ ACK father state.

In the WAIT _ ACK parent state, the child state collects SDA data and confirms whether the slave equipment responds or not according to the SDA data; if the slave device does not answer, the father state is converted into the STOP father state; if the slave device has a reply, the parent state transitions to either the READ _ DATA parent state or the WRITE _ DATA parent state based on the READ and WRITE control bits.

For example, as shown in fig. 7, in the WAIT _ ACK parent state, three child states are included, wherein child state 1: SDA is set as input; sub-state 2: SCL ═ 1, i.e., release data line signal, substate 3: the reading data line signals SDA and SDA are set as output; if not, SCL is 0, the father state is converted to STOP father state, otherwise, if it is, SCL is 0, according to R/W READ-WRITE control bit, the father state is converted to READ _ DATA father state or WRITE _ DATA father state.

Further, in the READ _ DATA parent state, the SDA DATA is moved into the READ-write buffer of I2C, and if the complete SDA DATA is received, the parent state is converted to the ACK _ DATA parent state. And after the sub-state in the parent state of the ACK _ DATA transmits the ACK signal, the parent state is converted into the parent state of the READ _ DATA again, or after the sub-state in the parent state of the ACK _ DATA transmits the NACK signal in the parent state of the ACK _ DATA, the parent state is converted into the parent state of the STOP.

Specifically, as shown in fig. 8, in the READ _ DATA parent state, three child states are included, child state 1: judging whether N DATA needing to be read are read completely, wherein N is the DATA length, such as 8 bits, if yes, converting the father state into the STOP father state, if not, setting SDA as input, SLC is 0, entering the child state 2, changing the time sequence jump into 1 in the child state 2, namely SCL is 1, entering the child state 3, in the child state 3, moving SDA into the lowest bit of DATA, if the moved SDA DATA is not received, moving DATA to the left by one bit, returning to the child state 1, repeating the three child states until N complete DATA, such as 8 bits of DATA are received, preparing to read the next DATA, and converting the father state into the ACK _ DATA father state.

As shown in fig. 9, in the ACK _ DATA parent state, three child states are included, child state 1: SCL ═ 0; the SDA is set as output, and when the acknowledgement ACK signal is received, the SDA is 0, and when the NACK signal is received, the SDA is 1; the process jumps to the child state 2, in the child state 2, the SCL that is the timing signal jump is equal to 1, the process enters the child state 3, in the child state 3, the SCL that is the timing signal jump again is equal to 0, when the response ACK signal is received, the parent state is switched to the READ _ DATA parent state, and when the response ACK signal is received, the parent state is switched to the STOP parent state.

In the embodiment, in a WRITE _ DATA father state, the highest bit of DATA needing to be transmitted is shifted into the SDA to transmit the DATA to the slave device, after the highest bit of DATA is transmitted each time, the DATA needing to be transmitted is shifted to supplement the highest bit of DATA, the highest bit of DATA is shifted into the SDA again to transmit the highest bit of DATA to the slave device until the DATA needing to be transmitted is transmitted completely, and after the DATA needing to be transmitted is transmitted to the slave device, the father state is converted into a WAIT _ ACK father state; if the ACK signal is detected, the parent state is converted into a WRITE _ DATA parent state again, and if the ACK signal is not received or transmission of DATA to be transmitted is completed, the parent state is converted into a STOP parent state.

For example, as shown in fig. 10, in the WRITE _ DATA parent state, three child states are included, a child state 1 determines whether N, for example, 8-bit DATA has been transmitted, if so, the parent state is converted into the STOP parent state, if not, the highest bit of DATA to be transmitted is shifted into SDA, and the child state 2 is entered, and in the child state 2, SCL is 1, and the child state 3 is entered, and in the child state 3, the timing signal jumps, that is, SCL is 0, DATA is shifted to the left by one bit, and if 8-bit DATA has not been transmitted, the child state 1 is returned, and three child states are circulated until 8-bit DATA has been transmitted, and next DATA is prepared, and the parent state is converted into the no WAIT _ ACK parent state, and execution of the WAIT _ ACK parent state is performed as described in the above embodiment.

Further, in the STOP parent state, the child state generates a STOP signal, and the parent state is converted into an idle parent state to complete reading or writing of complete data. Specifically, as shown in fig. 11, in the STOP parent state, two sub-states are included, in the sub-state 1, SCL ═ 0 and SDA ═ 0, one STOP signal is generated, and the transition is made to the sub-state 2, in the sub-state 2, SCL ═ 1 and SDA ═ 1, and the parent state is transitioned to the idle parent state, and a complete data transmission is completed.

In summary, the method for implementing I2C communication according to the embodiment of the present invention implements the read-write function of I2C communication by using the hierarchical state machine to simulate all timings of I2C host communication, and for an embedded software system with limited chip hardware resources, the execution efficiency can be optimized by using the hierarchical state machine, and the read-write function of I2C can be implemented under field-oriented control FOC interruption, so that the CPU utilization can be improved.

The second aspect embodiment of the present invention also provides a non-transitory computer storage medium, on which a computer program is stored, the computer program being executed to implement the method for implementing I2C communication of the above embodiment. The method for implementing I2C communication can refer to the description of the above embodiments.

In a third aspect, the present invention provides a scooter, fig. 12 is a block diagram of the scooter according to one embodiment of the present invention, and as shown in fig. 12, the scooter 1 according to the embodiment of the present invention comprises at least one processor 10 and a memory 20 communicatively connected to the at least one processor 10, wherein the memory 20 stores instructions executable by the at least one processor 10, and the instructions, when executed by the at least one processor 10, cause the at least one processor 10 to perform the method for implementing I2C communication of the aforementioned embodiment.

According to the scooter 1 of the embodiment of the present invention, the memory 20 stores the instruction, and the processor 10 executes the instruction, so as to implement the method for implementing I2C communication of the above embodiment, which can improve the execution efficiency and the utilization rate of the processor resources.

In the description of this specification, any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of custom logic functions or processes, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.

While embodiments of the invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.