阅读说明：本技术 一种lvds转usb3.0多通道适配器 (LVDS-to-USB 3.0 multi-channel adapter ) 是由 邱晓晗 林方 王煜 司福棋 于 2020-12-28 设计创作，主要内容包括：本发明的一种LVDS转USB3.0多通道适配器,该适配器通过增加了多路接口芯片,并且FPGA通过乒乓缓存和状态查询等方式,可以独立处理各通道数据。LVDS转USB3.0多通道适配器的USB3.0主控芯片可按照UART协议发送和接收数管控制指令,于是在适配器电路上增加了多路接口芯片。本发明成本低廉,体积小重量轻,连接和操作简单,适用于进行一些需要频繁移动位置的测试。一个USB接口以及一个USB设备就可完成四通道数管控制和数传接收功能,减小了上位机软件设计的复杂性。通道数据相互独立、互不干扰,可以作为单通道或多通道适配器使用,提高了设计的通用性。(According to the LVDS-to-USB 3.0 multi-channel adapter, the multi-channel interface chip is added, and the FPGA can independently process data of each channel in a ping-pong cache mode, a state query mode and the like. The USB3.0 main control chip of the LVDS-to-USB 3.0 multi-channel adapter can send and receive digital control instructions according to a UART protocol, and therefore a multi-channel interface chip is added to an adapter circuit. The invention has the advantages of low cost, small volume, light weight and simple connection and operation, and is suitable for testing positions needing to be frequently moved. One USB interface and one USB device can complete four-channel data tube control and data transmission receiving functions, and complexity of upper computer software design is reduced. The channel data are independent and do not interfere with each other, and can be used as a single-channel or multi-channel adapter, so that the design universality is improved.)

1. The utility model provides a LVDS changes USB3.0 multichannel adapter which characterized in that: the system comprises 1 path of USB3.0 interface, 1 FPGA, 1 USB3.0 main control chip, 4 paths of RS-422 interface chips and 4 paths of LVDS interface chips;

the RS-422 interface chip is connected with a tube counting interface to realize the mutual conversion of the input and output RS-422 level and the TTL level, when the upper computer sends a tube counting instruction, the tube counting interface is realized by a USB3.0 main control chip, the FPGA caches the received tube counting interface and broadcasts the RS-422 interface of each channel;

when each channel sends an RS-422 tube counting instruction, the channel number is judged and marked by the FPGA and then sent to an upper computer through a USB3.0 main control chip and a USB3.0 interface;

each data transmission interface converts the input LVDS signals into TTL signals to be sent to the FPGA, judges which channel the LVDS signals come from in the FPGA, marks the channel number of the LVDS signals of the channel, converts the LVDS signals into 16-bit parallel signals conforming to a USB interface chip protocol, sends the 16-bit parallel signals to a USB3.0 main control chip, and sends data to an upper computer through a USB3.0 interface.

2. The LVDS-to-USB 3.0 multi-channel adapter according to claim 1, wherein: the USB3.0 main control chip configuration structure is as follows:

1) the first interface is a UART interface, and the UART interface comprises three endpoints which are respectively a sending endpoint, a receiving endpoint and an interruption endpoint so as to realize the function of a serial port;

2) the second interface is a synchronous slave equipment queue interface which comprises a synchronous slave equipment queue endpoint for receiving FPGA transmission data; the synchronous slave queue interface is used for an application of which an external processor needs to perform data read/write access to an internal buffer of the CYUSB 3014.

3. The LVDS-to-USB 3.0 multi-channel adapter according to claim 1, wherein: the FPGA receives LVDS serial image data of each channel at the same time, a cross-clock domain conversion function from serial data to parallel data is realized, ping-pong caches of corresponding channels are written after conversion is completed, then the full-empty state of each ping-pong cache is inquired, frame headers and channel numbers are packed and added in the reading process, marking is carried out according to the channel numbers, and finally the signals are sequentially sent to a USB3.0 main control chip according to a USB3.0 interface protocol for transmission.

4. The LVDS-to-USB 3.0 multi-channel adapter according to claim 3, wherein: after a four-channel LVDS interface in the FPGA receives LVDS serial image data, a clock domain crossing serial-parallel conversion module converts the serial image data into 16-bit parallel image data and stores the 16-bit parallel image data into a corresponding channel ping-pong cache, after one RAM in the ping-pong cache is fully written, a ping-pong cache state bit is inverted, and the read-write states of two RAMs in the ping-pong cache are determined by the ping-pong cache state bit;

the ping-pong buffer output data is output by the read state RAM, and the read counter, the ping-pong buffer state bit and the read data are output.

5. The LVDS-to-USB 3.0 multi-channel adapter according to claim 4, wherein:

the FPGA also comprises a four-channel data processing module, wherein the four-channel data processing module inquires ping-pong cache status bits and channel reading status flag bits of all channels, and when one channel ping-pong cache is in the reading status bit and the channel reading status flags are consistent, the four-channel data processing module sends a DMA channel control unit of the channel data to a USB3.0 main control chip and sends the channel data to an upper computer through a USB3.0 interface;

before sending the channel data, the channel packet head is sent in advance, ping-pong cache flag bits of each channel are determined by ping-pong cache read-write states, and whether the channel read-state flag bits are read out by the channel RAM is determined;

when the two status flags are not consistent or the channel RAM data is completely sent, the next channel status is continuously inquired, and the LVDS image data of each channel are sent in sequence in a circulating manner.

6. The LVDS-to-USB 3.0 multi-channel adapter according to claim 1, wherein:

the RS-422 data pipe interface is divided into a sending module and a receiving module;

the RS-422 digital receiving module extracts and caches the state information of the channel spectrometers sent by the channel spectrometers according to a communication protocol, after all instructions are cached, the state information is sent to an upper computer through a USB3.0 main control chip and a USB3.0, the upper computer judges a channel number according to the packet headers of the channel data, and the state information is extracted and displays the current key index states;

the RS-422 digital tube sending module is used for sending a control instruction by an upper computer, extracting the instruction by the FPGA four-path RS-422 instruction serial-parallel conversion module according to a communication protocol, caching the instruction by the four-path RS-422 instruction caching module, sending the instruction to the four-path RS-422 instruction processing module to extract effective information after receiving a group of control instructions, and determining to send the instructions of exposure time, gain, number of photos and time code to which channel CCD imaging circuit to control the working mode by judging the packet head of an instruction chain.

7. The LVDS-to-USB 3.0 multi-channel adapter according to claim 1, wherein:

the USB3.0 main control chip sends and receives a digital tube control instruction according to a UART protocol.

Technical Field

The invention relates to the technical field of adapters, in particular to a multi-channel adapter for converting LVDS (Low Voltage differential Signaling) into USB (Universal Serial bus) 3.0.

Background

The satellite-borne spectrometer mainly utilizes the narrow-band absorption characteristics of gas molecules in the air to identify gas components, and deduces the concentration of trace gas according to the narrow-band absorption intensity. Certain satellite-borne spectrometers monitor and analyze satellite loads for various atmospheric pollutants (e.g., NO2, SO2, O3, and CO) by absorbing ultraviolet spectral lines using DOAS technology.

The satellite-borne spectrometer and the satellite-borne platform adopt a standard aviation interface, and debugging and testing are needed to be firstly carried out on the ground in the development process. In the past, an industrial personal computer and a plurality of acquisition cards are often adopted for testing LVDS and RS-422 interfaces of a CCD imaging circuit of a certain satellite-borne spectrometer, but the industrial personal computer is large in size and inconvenient to debug and test under different working environments, and the mode that the industrial personal computer is additionally provided with the acquisition cards is inconvenient, so that a product which is simple, easy to connect, small in size and light in weight is needed. Compared with an industrial personal computer, the notebook computer is easy to carry, the most common and convenient interface of the notebook computer is a USB interface, so the development requirement of an adapter with USB3.0 as the interface is generated, and the LVDS-to-USB 3.0 adapter is produced at the same time. Because newly developed satellite-borne spectrum observation is divided into two earth pushing sweeps and two adjacent edge swinging sweeps, and the total number of the CCD imaging circuits is four, four board cards and four USB3.0 interfaces are needed for the scheme of only supporting the conversion from one-channel LVDS to the USB3.0 adapter. Therefore, the LVDS-to-USB 3.0 multi-channel adapter is developed, four RS-422 digital interfaces and four LVDS data transmission interfaces are added on the premise of not increasing a USB interface, the connection of ground debugging is further simplified, and the flexibility of ground debugging is enhanced.

Interpretation of related terms:

usb 3.0: universal Serial Bus 3.0, a short for Universal Serial Bus, is an external Bus standard, and is used to standardize the connection and communication between a computer and external devices.

B, FPGA: the Field Programmable Gate Array is a kind of semiconductor integrated circuit for short.

LVDS: low Voltage Differential Signaling is a short for Low Voltage Differential signal, and is a protocol for transmitting data at high speed by adopting an extremely Low Voltage swing and a Differential form.

RS-422: EIA-422, is a series of data transmission protocols that specify the use of 4-wire, full duplex, differential transmission, and multicast.

E, UART: a universal serial data bus for asynchronous communications.

Disclosure of Invention

The invention provides an LVDS-USB 3.0 multi-channel adapter which can solve the technical problem.

In order to achieve the purpose, the invention adopts the following technical scheme:

an LVDS-to-USB 3.0 multichannel adapter comprises 1 path of USB3.0 interface, 1 FPGA, 1 USB3.0 main control chip, 4 paths of RS-422 interface chips and 4 paths of LVDS interface chips; the RS-422 interface chip is connected with a tube counting interface to realize the mutual conversion of the input and output RS-422 level and the TTL level, when the upper computer sends a tube counting instruction, the tube counting interface is realized by a USB3.0 main control chip, the FPGA caches the received tube counting interface and broadcasts the RS-422 interface of each channel;

when each channel sends an RS-422 tube counting instruction, the channel number is judged and marked by the FPGA and then sent to an upper computer through a USB3.0 main control chip and a USB3.0 interface;

each data transmission interface converts the input LVDS signals into TTL signals to be sent to the FPGA, judges which channel the LVDS signals come from in the FPGA, marks the channel number of the LVDS signals of the channel, converts the LVDS signals into 16-bit parallel signals conforming to a USB interface chip protocol, sends the 16-bit parallel signals to a USB3.0 main control chip, and sends data to an upper computer through a USB3.0 interface.

Further, the configuration structure of the USB3.0 main control chip is as follows:

1) the first interface is a UART interface, and the UART interface comprises three endpoints which are respectively a sending endpoint, a receiving endpoint and an interruption endpoint so as to realize the function of a serial port;

2) the second interface is a synchronous slave equipment queue interface which comprises a synchronous slave equipment queue endpoint for receiving FPGA transmission data; the synchronous slave queue interface is used for an application of which an external processor needs to perform data read/write access to an internal buffer of the CYUSB 3014.

Furthermore, the FPGA receives LVDS serial image data of each channel at the same time, a clock domain crossing conversion function from serial data to parallel data is realized, the data is written into ping-pong caches of corresponding channels after conversion is completed, then the full-empty state of each ping-pong cache is inquired, frame headers and channel numbers are packed and added in the reading process, the frame headers and the channel numbers are marked according to the channel numbers, and finally the data are sequentially sent to a USB3.0 main control chip according to a USB3.0 interface protocol for transmission.

Furthermore, after the four-channel LVDS interface in the FPGA receives LVDS serial image data, the clock domain crossing serial-parallel conversion module converts the serial image data into 16-bit parallel image data and stores the 16-bit parallel image data into a corresponding channel ping-pong cache, after one RAM in the ping-pong cache is fully written, a ping-pong cache state bit is inverted, and the read-write states of two RAMs in the ping-pong cache are determined by the ping-pong cache state bit;

the ping-pong buffer output data is output by the read state RAM, and the read counter, the ping-pong buffer state bit and the read data are output.

Further, the FPGA also comprises a four-channel data processing module, wherein the four-channel data processing module queries ping-pong cache status bits and channel reading status flag bits of all channels, and when one channel ping-pong cache is in the reading status bit and the channel reading status flags are consistent, the four-channel data processing module sends the channel data DMA channel control unit to a USB3.0 main control chip and sends the channel data DMA channel control unit to an upper computer through a USB3.0 interface;

before sending the channel data, the channel packet head is sent in advance, ping-pong cache flag bits of each channel are determined by ping-pong cache read-write states, and whether the channel read-state flag bits are read out by the channel RAM is determined;

when the two status flags are not consistent or the channel RAM data is completely sent, the next channel status is continuously inquired, and the LVDS image data of each channel are sent in sequence in a circulating manner.

Further, the RS-422 digital interface is divided into a sending module and a receiving module;

the RS-422 digital receiving module extracts and caches the state information of the channel spectrometers sent by the channel spectrometers according to a communication protocol, after all instructions are cached, the state information is sent to an upper computer through a USB3.0 main control chip and a USB3.0, the upper computer judges a channel number according to the packet headers of the channel data, and the state information is extracted and displays the current key index states;

the RS-422 digital tube sending module is used for sending a control instruction by an upper computer, extracting the instruction by the FPGA four-path RS-422 instruction serial-parallel conversion module according to a communication protocol, caching the instruction by the four-path RS-422 instruction caching module, sending the instruction to the four-path RS-422 instruction processing module to extract effective information after receiving a group of control instructions, and determining to send the instructions of exposure time, gain, number of photos and time code to which channel CCD imaging circuit to control the working mode by judging the packet head of an instruction chain.

Further, the USB3.0 main control chip sends and receives the digital control instruction according to the UART protocol.

According to the technical scheme, the LVDS-to-USB 3.0 multi-channel adapter (hereinafter referred to as the adapter) comprises 1 path of USB3.0 interface, 1 FPGA, 1 CYUSB3014(USB3.0 main control chip), 4 paths of RS-422 digital interfaces and 4 paths of LVDS interfaces. The adapter can independently process data of each channel by adding various interface chips and by the FPGA in modes of ping-pong cache, state query and the like. The USB3.0 main control chip of the LVDS-to-USB 3.0 multi-channel adapter can send and receive a digital control instruction according to a UART protocol, and therefore various interface chips are added to the adapter circuit.

The invention can realize the following functions:

1. the upper computer is connected with a USB3.0 interface and respectively sends a digital control command to a certain 4-channel CCD imaging circuit of the satellite-borne spectrometer connected with 4 paths of RS-422 interfaces of the adapter through a USB3.0 main control chip and an FPGA, wherein the digital control command comprises the following steps: exposure time, gain adjustment, photographing times and other control parameters. The 4 RS-422 interfaces can simultaneously receive spectrometer state information returned by CCD imaging circuits of all channels of a certain satellite-borne spectrometer and return the spectrometer state information to the upper computer through the 1 USB3.0 interface.

2. LVDS serial image information is sent by 4 paths of LVDS interfaces of a certain satellite-borne spectrometer 4-channel CCD imaging circuit connecting adapter and is sent to an upper computer through the FPGA and a USB3.0 main control chip through the same path of USB3.0 interface. The scheme of the LVDS-USB 3.0 multi-channel adapter solves the problem that a certain satellite-borne spectrometer needs to adopt a plurality of LVDS-USB 3.0 adapters for a multi-channel CCD imaging circuit or adopt a plurality of industrial personal computers which are additionally provided with a plurality of acquisition cards or board cards in the past. One board card of the scheme of the LVDS-to-USB 3.0 multi-channel adapter can be simultaneously connected with a 4-channel CCD imaging circuit, so that a ground detection platform building mode which is light, portable, low in cost and simple in connection is provided.

In general, the present invention has the following advantages:

1. the scheme has the advantages of low cost, small volume, light weight and simple connection and operation, and is suitable for testing positions needing to be frequently moved.

2. One USB interface and one USB device can complete four-channel data tube control and data transmission receiving functions, and complexity of upper computer software design is reduced.

3. The data of each channel are independent and do not interfere with each other, and the adapter can be used as a single-channel or multi-channel adapter, so that the universality of design is improved.

4. The adapter can be suitable for multiple types of pipe interfaces of RS-232, RS-485 and RS-422, and the universality of the adapter is further improved.

Drawings

FIG. 1 is a block diagram of an interface of a conventional adapter circuit on a satellite platform;

FIG. 2 is a form of using an industrial personal computer and an acquisition card in the existing ground detection platform design;

FIG. 3 is a diagram of a prior art spectrometer connected to a ground detection station;

FIG. 4 is a schematic diagram of a conventional LVDS-to-USB 3.0 communication adapter;

FIG. 5 is a block diagram of a conventional LVDS-to-USB 3.0 communication adapter;

FIG. 6 is a schematic diagram of a CCD imaging circuit connected to a ground inspection platform using the present invention;

FIG. 7 is a diagram of the overall circuit configuration of the present invention;

FIG. 8 is a diagram of the application of the present invention to data read/write access to the internal buffers of the CYUSB 3014;

FIG. 9 is a schematic diagram of the FPGA module structure of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention.

The CCD imaging circuit is the most important component of a certain satellite-borne spectrometer, and the LVDS-to-USB 3.0 multi-channel adapter is mainly used for testing the CCD imaging circuit of the spectrometer, and the interface of the adapter circuit on a certain satellite-borne platform is shown in figure 1; the RS-422 digital interface mainly has the function of sending a control instruction of the imaging circuit and receiving state information returned by the spectrometer, and the LVDS digital transmission interface mainly has the function of receiving serial image data sent by the CCD imaging circuit.

The following modes exist:

method for additionally installing acquisition card on industrial personal computer

In the development process of the CCD imaging circuit, ground detection equipment needs to be completed before the imaging circuit, and a debugging and testing platform is provided for a simulated satellite platform. Generally, the design of the ground detection platform is completed by using an industrial personal computer + an acquisition card, as shown in fig. 2:

wherein:

1) the RS-422 serial port card is responsible for controlling the number of the tubes, and the prior design selects PCI-8431 produced by NI company.

2) The LVDS board card is responsible for receiving data transmission data, and PCI-6561 produced by NI company is selected in the previous design.

Second, mode of using LVDS to convert into USB3.0 communication adapter

The connection of the DOAS imaging spectrometer system and the ground detection table is shown in fig. 3, which mainly accomplishes two functions:

(1) the serial LVDS interface format image signals output by the DOAS imaging spectrometer system are converted into USB interface format image signals and are sent to an upper computer for real-time imaging and storage, so that real-time debugging and testing are facilitated and the image signals are used for subsequent data processing.

(2) The instruction data sent by the upper computer through the USB interface is as follows: control commands such as image start-stop, exposure time and gain, time code information and the like are converted into an RS-422 synchronous serial communication format through a USB3.0 adapter and sent to a spectrometer system, and the working mode of the spectrometer is controlled and inquired.

The LVDS interface of the spectrometer is a high-speed data transmission communication interface with the code rate of 43Mbps, and the interface is used as a data transmission communication interface; the RS-422 interface of the spectrometer is a low-speed interface, the code rate is 100Kbps, and the interface is used as a digital tube communication interface.

A system diagram of an LVDS to USB3.0 adapter according to the above requirements is shown in fig. 4. As can be seen from fig. 4, the DOAS imaging spectrometer system first sends LVDS image data to the LVDS receiving chip of the USB3.0 communication adapter, then sends the LVDS image data to the FPGA for serial-to-parallel conversion, sends the LVDS image data to the USB chip through the FPGA, and finally sends the LVDS image data to the host computer through the USB interface. The instruction data is directly communicated with the upper computer through the RS-422 chip and the USB chip. Therefore, the LVDS-to-USB 3.0 communication adapter mainly completes interface design of the USB3.0 communication adapter and firmware design of the USB3.0 adapter, including firmware of an FPGA chip and firmware of a USB chip.

In the design, a spectrometer system sends data to an FPGA through an LVDS interface to complete serial-parallel conversion, the converted 16-bit parallel data passes through a data ping-pong cache unit and then sends high-speed image data to a USB, and at the moment, a CYUSB3014 serves as a slave device and transmits the data to a USB endpoint through an internal DMA channel of the CYUSB. The PC sends command data to the RS-422 interface of the spectrometer system through the USB, wherein the command data belongs to low-speed data, and at the moment belongs to a master device mode, the USB interface supports a UART mode to realize non-USB serial data transmission, in the mode, TXD (output) of the UART is mapped to a D-row, and RXD (input) of the UART is mapped to a D + row.

As shown in fig. 2, the main disadvantages of the design and inspection using the industrial personal computer and the acquisition card are that the solution is too costly, has a large volume and weight, is inconvenient to move, has complex connections, and is inconvenient to move when performing some tests (such as external field experiments) requiring frequent movement of positions. In addition, the design problem also includes that the previous LVDS acquisition card PCI-6561 has an upper limit of 50M on the input LVDS clock frequency, cannot completely meet the requirements of subsequent products, and is stopped.

As shown in fig. 3, the scheme of the LVDS to USB3.0 adapter is convenient to move, but four adapter board cards are required to connect a CCD imaging circuit of a four-channel certain satellite spectrometer. At the moment, four USB interfaces are needed for connecting the notebook computer, in addition, the four adapters are mapped into four devices in the system, the complexity of upper computer software design is increased, and the inconvenience of operation is increased in the process of debugging and testing the four-channel CCD imaging circuit of the spectrometer.

Therefore, the embodiment of the invention designs an LVDS-to-USB 3.0 multi-channel adapter, on the basis of the advantages that the LVDS-to-USB 3.0 adapter is high in cost, inconvenient to move, low in cost and the like relative to an industrial personal computer, a USB interface, an FPGA and a CYUSB3014(USB3.0 main control chip) are not added, and only the RS-422 and the LVDS interface are added on a board card, so that the four-channel CCD imaging circuit of the spectrometer can be debugged and tested simultaneously, and the convenience of simultaneous debugging and testing operation of multiple channels when the multi-channel CCD imaging circuit exists in the spectrometer is further solved; the research and development cost of the ground inspection platform is further reduced; the complexity of the design of the upper computer test software is further reduced.

The following is a detailed description:

integral design

The connection between the CCD imaging circuit and the ground inspection platform is shown in fig. 6, and it can be seen that the LVDS to USB3.0 multi-channel adapter performs three functions:

1. a certain satellite-borne spectrometer is divided into four channels including push-to-ground scanning and edge-to-edge scanning, and each channel comprises a set of RS-422 digital interface and LVDS digital transmission interface. Each group of RS-422 multi-tube interfaces can simultaneously or time-divisionally send or receive multi-tube signals, and all groups of signals do not interfere with each other. Each set of LVDS data transmission interfaces can simultaneously accept LVDS serial image data. The adapter can simultaneously use four channels, and can also be independently used as a single-channel, double-channel or three-channel LVDS-to-USB 3.0 adapter.

2. The interface of the digital tube has 2 groups of reverse signals TX and RX, and a serial port protocol meeting RS-422 level specification is used. The transmitted content comprises time codes, image start and stop, exposure time, image gain and the like, and state information replied by a CCD imaging circuit of a certain spectrometer can be transmitted back.

3. The data transmission interface is composed of 3 groups of signals, the direction of the data transmission interface is sent to the adapter by the CCD imaging circuit, and the 3 groups of signals meet the LVDS level specification. The Data transmission interface is mainly used for converting image signals output by the CCD imaging circuit into image signals in a USB interface format and sending the image signals to an upper computer for real-time imaging and storage, so that real-time debugging is facilitated and the Data processing is performed subsequently.

Circuit structure

The overall circuit structure of the LVDS-to-USB 3.0 multi-channel adapter is shown in FIG. 7. The RS-422 interface chip is connected with a number tube interface to realize the mutual conversion of the input and output RS-422 level and the TTL level, when the upper computer sends a number tube instruction, the number tube interface is realized by a USB3.0 main control chip, the FPGA caches the received number tube instruction, and then broadcasts the RS-422 interface of each channel. Correspondingly, when each channel sends an RS-422 digital command, the channel number is judged and marked by the FPGA and then sent to the upper computer through the USB3.0 main control chip and the USB3.0 interface. Each data transmission interface converts the input LVDS signals into TTL signals to be sent to the FPGA, judges which channel the LVDS signals come from in the FPGA, marks the channel number of the LVDS signals of the channel, converts the LVDS signals into 16-bit parallel signals conforming to a USB interface chip protocol, sends the 16-bit parallel signals to a USB3.0 main control chip, and sends data to an upper computer through a USB3.0 interface.

USB3.0 firmware design

The USB3.0 interface chip designed this time selects CYUSB3014 chip produced by Cypress company. The CYUSB3014 chip integrates a USB3.0, USB2.0 physical layer and a 32-bit ARM926EJ-S microprocessor, has powerful data processing capability, supports a maximum of 16 output interfaces and 16 input interfaces, and has 512KB of RAM on chip for storing firmware and data. The data transmission interface and the data interface are both realized by an Endpoint (Endpoint) technology in the USB3.0 device.

The USB3.0 configuration structure designed this time is as follows:

1) the first interface is a UART interface, which includes three endpoints, namely a Transmit (TX), a Receive (RX), and an INTERRUPT (INTERRUPT) endpoint, to implement a serial port function.

2) The second Interface is a Synchronous Slave queue Interface (Synchronous Slave FIFO Interface) which comprises a Synchronous Slave queue (Slave FIFO) endpoint for receiving FPGA transmission data. The synchronous slave queue interface is generally used for an application in which an external processor needs to perform data read/write access to an internal buffer of the CYUSB3014, and the structure of the synchronous slave queue interface is shown in fig. 8:

FPGA design

LVDS data transmission function

The LVDS data transmission function is mainly realized by the FPGA and mainly completed: meanwhile, receiving LVDS serial image data of each channel, realizing a cross-clock domain conversion function from serial data to parallel data, writing the converted data into a ping-pong buffer of a corresponding channel, then inquiring the full-empty state of each ping-pong buffer, and packing and adding a frame header and a channel number in the reading process, for example, adding a frame header of 0x12340001 when reading a channel 1, wherein 0x1234 is the frame header and is used for finding the initial position of each channel message, and 0001 represents the channel number and is used for data splicing of the same channel. And marking according to the channel number, and finally sequentially sending to a USB3.0 main control chip for transmission according to a USB3.0 interface protocol. As shown in particular in fig. 9.

When the four-channel LVDS interface receives LVDS serial image data, the clock domain crossing serial-parallel conversion module converts the serial image data into 16-bit parallel image data and stores the 16-bit parallel image data into the corresponding channel ping-pong cache, after one RAM in the ping-pong cache is fully written, a ping-pong cache State bit (State) is inverted, and the read-write State of two RAMs in the ping-pong cache is determined by the ping-pong cache State bit. The ping-pong buffer output data is output from the read State RAM, and outputs a read counter (ReadCnt), a ping-pong buffer State bit (State), and read data (Date). The four-channel data processing module mainly queries a ping-pong buffer status bit (State) and a channel reading status flag bit (ReadState) of each channel, and when one channel ping-pong buffer is in the reading status bit and the channel reading status flags are consistent, sends the channel data to a USB3.0 main control chip (out Date) through a DMA channel control unit shown in fig. 7, and sends the channel data to an upper computer through a USB3.0 interface. Before sending the channel data, the channel header is sent first (out date ═ Mark). The ping-pong buffer status flag (State) of each channel is determined by the ping-pong buffer read-write status, and the channel read status flag (ReadState) is determined by whether the channel RAM is read out. When the two status flags are not consistent or the channel RAM data is completely sent, the next channel status is continuously inquired, and the LVDS image data of each channel are sent in sequence in a circulating manner.

RS-422 several-tube interface

The RS-422 digital interface is divided into a sending module and a receiving module.

The RS-422 digital receiving module extracts and caches the state information of the channel spectrometers sent by the channel spectrometers according to a communication protocol, after all instructions are cached, the state information is sent to an upper computer through a USB3.0 main control chip and a USB3.0, the upper computer judges a channel number according to the packet headers of the channel data, and the state information is extracted and displays the current key index states.

The RS-422 digital tube sending module is used for sending a control instruction by an upper computer, extracting the instruction according to a communication protocol by the FPGA four-path RS-422 instruction serial-parallel conversion module in the figure 7, caching the instruction by the four-path RS-422 instruction caching module, sending the instruction to the four-path RS-422 instruction processing module to extract effective information after receiving a group of control instructions, and determining to send the instructions of exposure time, gain, number of photos, time code and the like to the CCD imaging circuit of which channel to control the working mode by judging the packet head of an instruction chain.

The USB3.0 main control chip can send and receive digital control instructions according to a UART protocol, so that the LVDS-to-USB 3.0 multi-channel adapter integrates various interface chips such as RS-232, RS-485 and RS-422, can be suitable for spectrometer systems with different interfaces, and improves the compatibility of the adapter.

From the above, the present invention has the following features:

1. the adapter is only suitable for one USB3.0 interface to be connected with a notebook computer, and can realize that the 4-path LVDS data transmission interface receives LVDS serial image data and the 4-path RS-422 data tube interface receives and sends a data tube control instruction.

2. The adapter can be used as a single-channel, double-channel, three-channel or four-channel LVDS-to-USB 3.0 adapter. The channels are independent and do not interfere with each other.

Generally, the ground sample of the conventional scheme of processing a control machine by a collection card is large in size and inconvenient to move, so that the debugging and the testing are inconvenient in different environments, the scheme of adopting a notebook computer is most convenient, and a USB interface is the most common interface of the notebook computer, so that an LVDS-to-USB 3.0 adapter is developed. Because the existing project adopts four channel spectrometers, four LVDS-to-USB 3.0 adapters are required, 4 USB interfaces are required when the notebook is connected, and the USB interfaces are mapped into 4 devices on an upper computer, so that the complexity of software design and software operation is increased. Therefore, the LVDS-to-USB 3.0 multi-channel adapter is developed on the basis of converting LVDS to USB3.0 adapters and on the basis of not increasing the size of the adapter, the adapter is additionally provided with a plurality of interface chips, and FPGA can independently process data of each channel in modes of ping-pong cache, state query and the like. The USB3.0 main control chip of the LVDS-to-USB 3.0 multi-channel adapter can send and receive a digital control instruction according to a UART protocol, and therefore various interface chips are added to the adapter circuit.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.