阅读说明：本技术 互联裸芯与mpu的接口系统及其通信方法 (Interface system for interconnecting bare core and MPU and communication method thereof ) 是由 魏敬和 黄乐天 肖志强 冯敏刚 丁涛杰 郑利华 于 2021-02-05 设计创作，主要内容包括：本发明涉及互联裸芯与MPU的接口系统及其通信方法。互联裸芯与MPU的接口系统包括：数据接口、中断接口和调试接口；数据接口包括SPI接口、DDR数据接口和DMA控制接口,SPI接口用于MPU在启动阶段的自主启动,DMA控制接口用于DMA启动结束控制；中断接口用于接收来自网络的中断数据包并解析得到MPU需要的脉冲中断输入,同时中断接口接收到来自数据接口的中断地址操作并将其转换为中断事件发出；调试接口包括JTAG-Core调试接口,用于接收来自网络的调试数据包并翻译为JTAG协议用于MPU调试。该系统通过中断接口、DDR数据接口、SPI接口和JTAG-Core调试接口将互连裸芯所提供的接口与主设备MPU接口对应互连,实现高性能信息处理微系统中MPU的扩展以及MPU与互连裸芯之间的高速通信。(The invention relates to an interface system for interconnecting a bare chip and an MPU and a communication method thereof. An interface system interconnecting die and MPU includes: a data interface, an interrupt interface and a debugging interface; the data interface comprises an SPI (serial peripheral interface), a DDR (double data rate) data interface and a DMA (direct memory access) control interface, the SPI interface is used for the automatic starting of the MPU in the starting stage, and the DMA control interface is used for controlling the ending of the DMA starting; the interrupt interface is used for receiving an interrupt data packet from a network and analyzing the interrupt data packet to obtain a pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface and is used for receiving a debugging data packet from a network and translating the debugging data packet into a JTAG protocol for MPU debugging. The system correspondingly interconnects the interface provided by the interconnected bare chip and the MPU interface of the main equipment through the interrupt interface, the DDR data interface, the SPI interface and the JTAG-Core debugging interface, and realizes the expansion of the MPU in the high-performance information processing micro system and the high-speed communication between the MPU and the interconnected bare chip.)

1. An interface system interconnecting die and MPU, comprising: a data interface, an interrupt interface and a debugging interface; the data interface comprises an SPI (serial peripheral interface), a DDR (double data rate) data interface and a DMA (direct memory access) control interface, the SPI interface is used for the automatic starting of the MPU in the starting stage, and the DMA control interface is used for controlling the ending of the DMA starting; the interrupt interface is used for receiving an interrupt data packet from a network and analyzing the interrupt data packet to obtain a pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface which is used for receiving a debugging data packet from a network and translating the debugging data packet into a JTAG protocol for MPU debugging.

2. The interface system of claim 1, wherein the SPI interface, DDR data interface, DMA control interface, and interrupt interface are connected to the same router in the interconnect die; the debug interface is connected with another router in the interconnection bare chip.

3. The communication method of the interconnected bare chip and the MPU is characterized in that data transmission is carried out between the interconnected bare chip and the MPU through a data interface, interrupt transmission is carried out through an interrupt interface, and MPU debugging is carried out through a debugging interface; the MPU controls data access between the slave devices through a DMA control interface; the data interface comprises an SPI interface, a DDR data interface and a DMA control interface; the debugging interface comprises a JTAG-Core debugging interface.

4. The method of claim 3, wherein the MPU sends a memory access request to the interconnected die in DDR data format via the data interface; the interconnection bare chip converts the response data packet into a DDR data format and sends the DDR data format to the MPU.

5. The method of claim 4 wherein the MPU generates a request packet when sending a request event to the interconnect die, the method comprising: converting address information of a request event from the MPU into routing information by using a configurable address mapping table, wherein the routing information is used for representing a path through which a data packet passes in a network; generating the head and the tail of a data packet in a packaging module, and generating event contents into flits to form a complete data packet; writing the data packet into a request Buffer, and simultaneously recording the information of the current data packet in a message queue;

the interconnected bare chip generates response information from the response data packet, and the generation of the response information comprises the following steps: reading the data packet from the response Buffer, and eliminating the corresponding data packet record from the message queue; and the unpacking module verifies and eliminates the head and the tail of the data packet and integrates the content in the volume microchip of the data packet to generate a detailed signal required by the main equipment.

6. The method of claim 3 further comprising counting each record in the message queue using a watchdog, and if a packet remains in the message queue for a time period exceeding a threshold, the watchdog running over and generating an interrupt to notify the MPU that the packet is lost in the network and the data transmission fails, and the MPU performs corresponding processing.

7. The method of claim 3 in which the interrupt transmissions include a master-master interrupt transmission between the MPU and a master-slave interrupt transmission between the MPU and a slave device;

the master-master interrupt transmission includes the steps of: the MPU writes interrupt information to a section of fixed interrupt address preset in an address space of the MPU through a data interface, the interrupt interface packages the interrupt information into an interrupt event data packet and sends the interrupt event data packet to the interconnection die, and the other MPU receives the interrupt event data packet through the interrupt interface, unpacks the interrupt event data packet and translates the interrupt event data packet into an interrupt signal;

when the master-slave interrupt is transmitted, the interrupt interface of the slave device collects the interrupt information of the slave device, encodes and packages the interrupt information into an interrupt event data packet, and transmits the interrupt event data packet to the interconnection die, and the interrupt interface of the MPU receives and unpacks the interrupt event data packet and translates the interrupt event data packet into an interrupt signal.

8. The method of claim 3, wherein the MPU controls data access between the slave devices through the DMA control interface, and by accessing a fixed DMA address preset in an address space of the MPU, the access address space is converted into a register for configuring the DMA and the DMA is started to complete a corresponding data transfer instruction.

9. The method of claim 8 wherein the MPU controlling data access between slave devices via a DMA control interface comprises:

the first step, the MPU writes the address information of data transportation and the configuration information of data length into the exclusive address space of the DMA through a data interface;

secondly, the DMA control interface sends a read request event to the source slave equipment after receiving the configuration information, wherein the read request event has a specific event information mark, and the data returned by the slave equipment is returned to the target slave equipment;

thirdly, after the source slave equipment receives the read request event, packaging the data to be read into a write data event and sending the write data event to the target slave equipment;

fourthly, after receiving the write data event, the target slave device returns a write response event to the DMA control interface;

and fifthly, the DMA control interface generates an interrupt pulse to inform the MPU of finishing data transfer after receiving the write response event.

Technical Field

The invention relates to a communication interface, in particular to an interface system for interconnecting a bare chip and an MPU and a communication method thereof.

Background

In a monolithic asic, all components are designed and fabricated in the same process on a single silicon wafer. As process dimensions shrink, the cost and development cycle for developing such integrated circuits becomes extremely high. In this case, multi-die integration is a necessary choice, i.e., a plurality of functional and verified, unpackaged chip components are interconnected and assembled together and packaged as a whole chip in the same package, thereby forming a package-level network nop (network package). These dies can be made by different processes and from different manufacturers, thus greatly shortening and reducing the development cycle and difficulty. The difficulty of multi-die integration is how to efficiently interconnect the dies and ensure that higher microsystem performance is achieved under the constraint of power consumption. The existing communication protocol facing multi-die integration is a special protocol or has poor universality; or the technical system is too bulky and difficult to use. Under the condition that a multi-die interconnection bus protocol is immature, how to define the multi-die interconnection bus protocol which meets the development requirement of the current integrated circuit in China is a key problem for breaking through a new generation of integrated microsystems based on the practical situation and the current technical level in China.

Microsystems support heterogeneous integration by multiplexing existing dies. From the view of system level division, the micro system is formed by cascading a plurality of micro components, and each micro component is composed of an interconnected bare chip and other bare chips. The interconnection die is a die-level network NoD (a die including a high-speed on-chip network and an expansion bus) as a core, and is formed by adding various standard protocol interface conversion, configuration units, clock management and other circuits. The interconnected bare chip supports integrated bare chip including MPU (embedded microprocessor bare chip) as main equipment, peripheral equipment as slave equipment, storage equipment such as DDR SDRAM and the like, and DSP and FPGA which can integrate various interface forms such as main equipment interface, slave equipment interface, peer equipment interface and the like. Because of having multiple interfaces, how to implement expansion and communication between the interconnected dies and the MPU is an urgent problem to be solved.

Disclosure of Invention

In order to solve the above problems, the present invention provides an interface system of an interconnection die and an MPU, which includes an interrupt interface, a DDR data interface, an SPI interface, and a JTAG-Core debug interface, and can realize the expansion of a main device MPU and the high-speed communication between the main device and the interconnection die in a high-performance information processing microsystem by correspondingly interconnecting an interface provided by the interconnection die and the MPU interface, thereby solving the problem of the high-speed communication between the interconnection die and the MPU, and efficiently performing the rapid expansion and integration of main device processing devices such as the MPU.

The specific technical scheme is as follows:

an interface system interconnecting die and MPU, comprising: a data interface, an interrupt interface and a debugging interface; the data interface comprises an SPI (serial peripheral interface), a DDR (double data rate) data interface and a DMA (direct memory access) control interface, the SPI interface is used for the automatic starting of the MPU in the starting stage, and the DMA control interface is used for controlling the ending of the DMA starting; the interrupt interface is used for receiving an interrupt data packet from a network and analyzing the interrupt data packet to obtain a pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface which is used for receiving a debugging data packet from a network and translating the debugging data packet into a JTAG protocol for MPU debugging.

Preferably, the SPI interface, the DDR data interface, the DMA control interface, and the interrupt interface are connected to the same router in the interconnected die; the debug interface is connected with another router in the interconnection bare chip.

The communication method of the interconnected bare chip and the MPU comprises the steps that data transmission is carried out between the interconnected bare chip and the MPU through a data interface, interrupt transmission is carried out through an interrupt interface, and MPU debugging is carried out through a debugging interface; the MPU controls data access between the slave devices through a DMA control interface; the data interface comprises an SPI interface, a DDR data interface and a DMA control interface; the debugging interface comprises a JTAG-Core debugging interface.

Preferably, the MPU sends a memory access request to the interconnected bare chip in a DDR data format through a data interface; the interconnection bare chip converts the response data packet into a DDR data format and sends the DDR data format to the MPU.

Further, the MPU generates a request packet when sending the request event to the interconnect die, and the generating the request packet includes the following steps: converting address information of a request event from the MPU into routing information by using a configurable address mapping table, wherein the routing information is used for representing a path through which a data packet passes in a network; generating the head and the tail of a data packet in a packaging module, and generating event contents into flits to form a complete data packet; writing the data packet into a request Buffer, and simultaneously recording the information of the current data packet in a message queue; the interconnected bare chip generates response information from the response data packet, and the generation of the response information comprises the following steps: reading the data packet from the response Buffer, and eliminating the corresponding data packet record from the message queue; and the unpacking module verifies and eliminates the head and the tail of the data packet and integrates the content in the volume microchip of the data packet to generate a detailed signal required by the main equipment.

Preferably, the method further comprises counting each record existing in the message queue by using a watchdog, starting from record generation until record elimination, and if the retention time of a data packet in the message record exceeds a certain threshold, the watchdog count overflows and generates an interrupt to inform the MPU that the data packet is lost in the network and the data transmission fails, and the MPU performs corresponding processing.

Preferably, the interrupt transmission includes a master-master interrupt transmission between the MPU and a master-slave interrupt transmission between the MPU and the slave device; the master-master interrupt transmission includes the steps of: the MPU writes interrupt information to a section of fixed interrupt address preset in an address space of the MPU through a data interface, the interrupt interface packages the interrupt information into an interrupt event data packet and sends the interrupt event data packet to the interconnection die, and the other MPU receives the interrupt event data packet through the interrupt interface, unpacks the interrupt event data packet and translates the interrupt event data packet into an interrupt signal; when the master-slave interrupt is transmitted, the interrupt interface of the slave device collects the interrupt information of the slave device, encodes and packages the interrupt information into an interrupt event data packet, and transmits the interrupt event data packet to the interconnection die, and the interrupt interface of the MPU receives and unpacks the interrupt event data packet and translates the interrupt event data packet into an interrupt signal.

Preferably, when the MPU controls data access between the slave devices through the DMA control interface, the MPU converts an access address space into a register for configuring the DMA by accessing a fixed DMA address preset in the address space of the MPU, and starts the DMA to complete a corresponding data transfer instruction.

Further, the MPU controls data access between slave devices through a DMA control interface, including the steps of: the first step, the MPU writes the address information of data transportation and the configuration information of data length into the exclusive address space of the DMA through a data interface; secondly, the DMA control interface sends a read request event to the source slave equipment after receiving the configuration information, wherein the read request event has a specific event information mark, and the data returned by the slave equipment is returned to the target slave equipment; thirdly, after the source slave equipment receives the read request event, packaging the data to be read into a write data event and sending the write data event to the target slave equipment; fourthly, after receiving the write data event, the target slave device returns a write response event to the DMA control interface; and fifthly, the DMA control interface generates an interrupt pulse to inform the MPU of finishing data transfer after receiving the write response event.

Compared with the prior art, the invention has the following beneficial effects:

the interface system of the interconnected bare chip and the MPU correspondingly interconnects the interface provided by the interconnected bare chip and the interface of the main equipment MPU through the interrupt interface, the DDR data interface, the SPI interface and the JTAG-Core debugging interface, and realizes the expansion of the main equipment MPU and the high-speed communication between the main equipment and the interconnected bare chip in the high-performance information processing micro system.

1. The interface system for interconnecting the bare chip and the MPU can meet the integration and expansion of the bare chip of main equipment such as the MPU. The interconnection bare chip provides a main equipment interrupt interface, a DDR data interface, an SPI interface and a JTAG-Core debugging interface for the MPU main equipment, and the expansion of the main equipment MPU in the high-performance information processing micro system can be realized by correspondingly interconnecting the interface provided by the interconnection bare chip and the main equipment MPU interface.

2. An SPI interface in a master device interface is only used for starting BootRom reading and does not occupy bandwidth during operation; the DMA interface does not directly participate in data transportation, so the data volume is small; the interrupt interface has small data volume and small bandwidth occupation, so that three data interfaces and the interrupt interface are arbitrated and distributed by respective converters and then are accessed into one router, and the complexity of address mapping can be effectively reduced under the condition of ensuring the overall performance of the interface of the main equipment.

Drawings

FIG. 1 is a schematic diagram of an interface system interconnecting die and MPU;

FIG. 2 is a schematic diagram of a complete structure of an interface system interconnecting die and MPU;

FIG. 3 is a schematic diagram of the structure of the data interface of the MPU;

FIG. 4 is a schematic diagram of interrupt transmission between an MPU and a slave device;

FIG. 5 is a schematic diagram of the MPU0 writing interrupt data to an interrupt address;

FIG. 6 is a diagram of MPU0 interrupt interface packetizing send interrupt event packets to MPU 1;

FIG. 7 is an interrupt interface of MPU1 interpreting a packet and generating a corresponding interrupt pulse;

FIG. 8 is a DMA control slave-to-slave data transfer;

FIG. 9 is a flow chart of slave-to-slave data transfer;

FIG. 10 is an MPU sending control instructions to a DMA address space;

FIG. 11 is a DMA initiating a read request event to a source slave;

FIG. 12 is a source slave initiating a write data event to a destination slave;

FIG. 13 is a destination slave initiating a write response event to a DMA;

FIG. 14 is a DMA initiating an interrupt to an MPU;

fig. 15 is a schematic diagram of a structure of an interconnect die.

Detailed Description

The invention will now be further described with reference to the accompanying drawings.

As shown in fig. 15, an interconnect die includes: the protocol conversion circuit comprises a plurality of protocol conversion modules and is used for providing a plurality of standard mainstream protocol interfaces connected with the outside; the external interconnection interface comprises a pair of synchronous controllers and is used for communicating with other interconnection bare chips; and the internal bare chip level network comprises a transmission bus and a router, and the synchronous controller and the protocol conversion module are respectively connected with the boundary nodes of the internal bare chip level network and are used for transmitting data packets from interfaces or other interconnected bare chips.

The function bare chip is connected with the protocol conversion module through a standard protocol bus.

The interconnected bare cores are connected through an expansion bus (CIBP).

The interconnection bare chip mainly comprises an internal bare chip level Network (NoD), a protocol conversion circuit and an external interconnection interface. NoD for data routing and high speed transport. The protocol conversion circuit provides a plurality of standard mainstream protocol interfaces connected with the outside, and comprises a plurality of protocol conversion modules for converting NoD protocol to mainstream protocol, and is used for being connected with other functional bare cores. The external interconnection interface mainly comprises a pair of synchronous controllers, and the external interconnection interface is controlled by the synchronous controllers to realize data transmission of different clock domains inside and outside the bare chip. The external interconnection interface and each conversion module of the protocol conversion circuit are respectively connected with one boundary node in NoD, thereby forming a data transmission path.

The interconnect die transmits the interrupt request in the form of a data packet over the network.

Example one

As shown in fig. 1 and 2, an interface system for interconnecting dies and an MPU includes: a data interface, an interrupt interface and a debugging interface; the data interface comprises an SPI (serial peripheral interface), a DDR (double data rate) data interface and a DMA (direct memory access) control interface, the SPI interface is used for the automatic starting of the MPU in the starting stage, and the DMA control interface is used for controlling the ending of the DMA starting; the interrupt interface is used for receiving an interrupt data packet from a network and analyzing the interrupt data packet to obtain a pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface which is used for receiving a debugging data packet from a network and translating the debugging data packet into a JTAG protocol for MPU debugging.

The SPI interface, the DDR data interface, the DMA control interface and the interrupt interface are connected with the same router in the interconnected bare chip; the debug interface is connected with another router in the interconnection bare chip.

The multi-die integrated high-performance information processing micro system can meet the integration and expansion of the dies of main equipment such as MPU. The interconnection die provides a main equipment interrupt interface, a DDR data interface, an SPI interface and a JTAG-Core debugging interface for the MPU main equipment, and as shown in figure 1, the expansion of the main equipment MPU in the high-performance information processing micro system can be realized by correspondingly interconnecting the interface provided by the interconnection die and the main equipment MPU interface.

Since NoD in the interconnection bare chip can convert all access and storage operations into corresponding data packets and transmit the data packets through networks in the bare chip and between the bare chip, for the access and storage request of the main device, the main device only needs to send the access and storage request to the interconnection bare chip in a DDR data format through a DDR data interface, and the data packets are sent to the network after the DDR data interface of the main device of the interconnection bare chip packages the access and storage request. Meanwhile, the DDR data interface of the master device may also receive a data response from the interconnect die, that is, the DDR data interface of the master device of the interconnect die converts the response data packet into a DDR data format and inputs the DDR data format to the master device.

For an interrupt request of a master device, a fixed space is arranged in an address space of the master device and used as an interrupt address, the master device writes interrupt information into the interrupt address of the master device through a DDR data interface to complete the sending of the interrupt request, and the master device interrupt interface of an interconnected bare chip packages the interrupt request into an interrupt event (an event defined for processing data transmission and a data event defined in addition to the event, including a read request event, a read response event, a write data event and a write response event) data package to be sent into a network after receiving the interrupt information. For the interrupt reception of the master device, the master device interrupt interface of the interconnected bare chip unpacks the interrupt event data packet according to the specified data packet format and translates the data packet into an interrupt signal, and the master device receives the interrupt information from the interconnected bare chip through the interrupt interface and further interrupts the MPU.

A master device may control data access between two or more slave devices through a DMA control interface. Similar to the interrupt, there is a fixed space in the address space of the master device as the address of the DMA, so the master device configures and activates the DMA control interface in the interconnect die master device interface through the DDR data interface, and data transfer can be performed between two or more slave devices under the control of the DMA control interface.

The SPI interface of the master device is used for the master device to be started autonomously in a starting stage, the MPU sends a read request for BootRom on the interconnected bare chip through the SPI interface to read a starting code of the MPU, and the starting code is executed to realize the starting of the MPU.

The JTAG interface of the main equipment is used for connecting a JTAG-Core interface in the main equipment interface of the interconnected bare chip, and the MPU receives a JTAG debugging command from the interconnected bare chip through the interface, so that the debugging of the main equipment in the high-performance information processing micro system is realized.

Specifically, as shown in fig. 2, the complete MPU interface is divided into three categories: data interface, interrupt interface, debugging interface. The interconnection bare chip provides a main equipment interrupt interface, a DDR data interface, an SPI interface and a JTAG-Core debugging interface for MPU main equipment, wherein the data interface comprises a BootROM special SPI interface, a DDR data interface and a DMA control interface of the MPU, the interrupt interface is used for receiving an interrupt data packet from a network and analyzing to obtain a pulse interrupt input required by the MPU, the interrupt interface receives an interrupt address operation from the DDR and converts the interrupt address operation into an interrupt event to be sent, and the debugging interface JTAG-Core belongs to a slave interface type and is used for receiving a debugging data packet from the network and translating the debugging data packet into a JTAG protocol for MPU debugging.

The three data interfaces and the interrupt interface are accessed into a router after being arbitrated and distributed by respective converters: the SPI interface in the four interfaces is only used for starting BootRom reading and does not occupy bandwidth during operation; the DMA control interface is different from the traditional DMA, the DMA control interface only serves as DMA starting and ending control and does not directly participate in data transportation, so that the data volume is small; the data volume of the interrupt interface is small, the bandwidth is small, and therefore the four interfaces are accessed to the same router, and the complexity of address mapping is effectively reduced under the condition that the overall performance of the interfaces of the main equipment is guaranteed. When the four interfaces simultaneously send data packets, the data packets are sent out in sequence after being arbitrated by the arbitration circuit, and when the input data packets reach the interface of the router of the interface, the distribution circuit distributes the data packets to each interface according to event types and event addresses in the data packets: if the event is an interrupt event, the event is distributed to an interrupt interface for conversion; if the data is BootRom data, the data is distributed to an SPI interface for conversion; if the type of data is the data type, the data is sent to a data interface or a DMA control interface. Furthermore, the debug interface of the MPU is used to receive debug instructions from the network as a conventional slave data interface, independent of the rest of the interface, where the debug is seen as reading and writing to the MPU internal registers.

Example two

The communication method of the interconnected bare chip and the MPU comprises the steps that data transmission is carried out between the interconnected bare chip and the MPU through a data interface, interrupt transmission is carried out through an interrupt interface, and MPU debugging is carried out through a debugging interface; the MPU controls data access between two or more slave devices through a DMA control interface; the data interface comprises an SPI interface, a DDR data interface and a DMA control interface; the debugging interface comprises a JTAG-Core debugging interface.

The MPU sends a memory access request to the interconnected bare chip in a DDR data format through a data interface; the interconnection bare chip converts the response data packet into a DDR data format and sends the DDR data format to the MPU.

The MPU generates a request data packet when sending a request event to the interconnected bare chip, and the generation of the request data packet comprises the following steps: converting address information of a request event from the MPU into routing information by using a configurable address mapping table, wherein the routing information is used for representing a path through which a data packet passes in a network; generating the head and the tail of a data packet in a packaging module, and generating event contents into flits to form a complete data packet; writing the data packet into a request Buffer, and simultaneously recording the information of the current data packet in a message queue; the interconnected bare chip generates response information from the response data packet, and the generation of the response information comprises the following steps: reading the data packet from the response Buffer, and eliminating the corresponding data packet record from the message queue; and the unpacking module verifies and eliminates the head and the tail of the data packet and integrates the content in the volume microchip of the data packet to generate a detailed signal required by the main equipment.

The method also includes counting each record in the message queue by using the watchdog, and from the record generation to the record elimination, if the retention time of a data packet in the message record exceeds a certain threshold value, the watchdog count overflows and generates an interrupt to inform the MPU that the data packet is lost in the network and the data transmission fails, and the MPU performs corresponding processing.

The interrupt transmissions include a master-master interrupt transmission between the MPU and a master-slave interrupt transmission between the MPU and a slave device; the master-master interrupt transmission includes the steps of: the MPU writes interrupt information to a section of fixed interrupt address preset in an address space of the MPU through a data interface, the interrupt interface packages the interrupt information into an interrupt event data packet and sends the interrupt event data packet to the interconnection die, and the other MPU receives the interrupt event data packet through the interrupt interface, unpacks the interrupt event data packet and translates the interrupt event data packet into an interrupt signal; when the master-slave interrupt is transmitted, the interrupt interface of the slave device collects the interrupt information of the slave device, encodes and packages the interrupt information into an interrupt event data packet, and transmits the interrupt event data packet to the interconnection die, and the interrupt interface of the MPU receives and unpacks the interrupt event data packet and translates the interrupt event data packet into an interrupt signal.

And when the MPU controls data access between two or more slave devices through the DMA control interface, the access address space is converted into a register for configuring the DMA and starts the DMA to complete a corresponding data transfer instruction by accessing a fixed DMA address preset in the address space of the MPU.

The MPU controls data access between two or more slave devices through the DMA control interface, and comprises the following steps: the first step, the MPU writes the address information of data transportation and the configuration information of data length into the exclusive address space of the DMA through a data interface; secondly, the DMA control interface sends a read request event to the source slave equipment after receiving the configuration information, wherein the read request event has a specific event information mark, and the data returned by the slave equipment is returned to the target slave equipment; thirdly, after the source slave equipment receives the read request event, packaging the data to be read into a write data event and sending the write data event to the target slave equipment; fourthly, after receiving the write data event, the target slave device returns a write response event to the DMA control interface; and fifthly, the DMA control interface generates an interrupt pulse to inform the MPU of finishing data transfer after receiving the write response event.

The conversion method of the data interface of the main equipment comprises the following steps:

as shown in fig. 3, both SPI and DDR (DMA) are data type interfaces with the same hardware implementation.

For the input channel, it is mainly responsible for processing request events from the master device, for generating request packets: firstly, converting address information of a request event from a main device into routing information by using a configurable address mapping table, wherein the routing information is used for representing a path through which a data packet passes in a network; then generating the head and the tail of the data packet in a packaging module, and simultaneously generating event contents into a body microchip to form a complete data packet; and finally, writing the data packet into the request Buffer, and simultaneously recording the information of the current data packet in the message queue.

For the output channel, it is mainly responsible for processing the response packet from the network on chip, and is used to generate the response information required by the master device: firstly, reading a data packet from a response Buffer, and eliminating a corresponding data packet record from a message queue; and then, the unpacking module verifies and eliminates the head and the tail of the data packet, and integrates the content in the body microchip of the data packet to generate a detailed signal required by the main equipment.

In addition, in order to avoid the main device waiting all the time due to the event dependence (one event must be strictly completed before the next event can be carried out), a watchdog module is also arranged at the protocol conversion interface of the main device, and the watchdog module is a group of counters and generates a pulse after the count value is full. The watchdog will count each record in the message queue, and from the record generation to the record elimination, if the retention time of a data packet in the message record exceeds a certain threshold, the watchdog count overflow will generate an interrupt to inform the master device that the data packet is lost in the network, and the data transmission fails, and the master device needs to perform corresponding processing.

The method for converting the interrupt interface of the main equipment comprises the following steps:

the interrupt interface not only realizes responding to the interrupt event, but also realizes sending the interrupt event. A fixed space is arranged in the address space of the main device and used as an interrupt address, and after the main device writes interrupt information to the interrupt address through a data interface (DDR), the interrupt controller packs the information into an interrupt event data packet and sends the interrupt event data packet.

At NoD, forwarding of the slave-master interrupt is as shown in fig. 4, where an interrupt receiving interface at the slave interface collects the pulse interrupt information from the slave, encodes and packages the information into an interrupt event packet, and the packet is transmitted through the network and arrives at the master interrupt interface, then unpacks the packet into a corresponding interrupt pulse and sends the corresponding interrupt pulse to the master.

And NoD, the master-to-master interrupt transmission is divided into 3 steps as shown in fig. 5 to 7:

first, as shown in fig. 5, the MPU0 writes interrupt information data to its own interrupt address.

In the second step, as shown in fig. 6, the interrupt interface generates an interrupt packet based on the interrupt information and sends the interrupt packet to the destination host MPU 1.

Third, as shown in fig. 7, the interrupt interface of the MPU1 receives the interrupt packet, parses it, and generates an interrupt pulse to the MPU 1.

The method for converting the DMA control interface of the main equipment comprises the following steps:

the existing basic data event type cannot realize data transmission between the slave device and the slave device in the network, because the slave device interface cannot actively send out the request event and only can passively receive the request event, so that to realize the data transmission between the slave device and the slave device, additional hardware is required to send out the corresponding request event, and the DMA control interface is responsible for completing the task, as shown in fig. 8.

Similar to the interrupt interface, a fixed address space is divided into a DMA control interface in the address space of the MPU, accessing the address space is converted into configuring a register of the DMA control interface and starting the DMA to complete a corresponding data transfer instruction, so that the DMA control interface is used as a DDR derived interface, and when a data read/write address in the DDR falls into the address space of the DMA, the data read/write address is not sent to the network through the data interface of the DDR but is analyzed by the DMA control interface and data transfer is performed. As shown in fig. 9, a slave-to-slave data transfer flow initiated by the MPU is one time.

First, as shown in fig. 10, the MPU writes configuration information such as address information and data length of data transfer into an address space dedicated to the DMA through the DDR interface;

second, as shown in fig. 11, the DMA control interface sends a read request event to the source slave device after receiving the configuration information, where the read request event has specific event information indicating that the data returned from the slave device is not returned to the MPU, but is returned to a specific destination slave device;

thirdly, as shown in fig. 12, after receiving the read request event, the source slave device packages the data to be read into a write data event and sends the write data event to the destination slave device;

fourthly, as shown in fig. 13, the destination slave device returns a write response event to the DMA control interface after receiving the write data event;

in the fifth step, as shown in fig. 14, the DMA control interface generates an interrupt pulse to notify the MPU that the data transfer is completed after receiving the write response event.

The method has the advantages that:

1. the multi-die integrated high-performance information processing micro system can meet the integration and expansion of the dies of main equipment such as MPU. The interconnection bare chip provides a main equipment interrupt interface, a DDR data interface, an SPI interface and a JTAG-Core debugging interface for the MPU main equipment, and the expansion of the main equipment MPU in the high-performance information processing micro system can be realized by correspondingly interconnecting the interface provided by the interconnection bare chip and the main equipment MPU interface.

2. An SPI interface in a master device interface is only used for starting BootRom reading and does not occupy bandwidth during operation; the DMA interface does not directly participate in data transportation, so the data volume is small; the interrupt interface has small data volume and small bandwidth occupation, so that three data interfaces and the interrupt interface are arbitrated and distributed by respective converters and then are accessed into one router, and the complexity of address mapping can be effectively reduced under the condition of ensuring the overall performance of the interface of the main equipment.

The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive step, which shall fall within the scope of the appended claims.