阅读说明：本技术 三维（3d）存储器阵列中的集成字线触点结构 (Integrated word line contact structures in three-dimensional (3D) memory arrays ) 是由 N·K·查克拉瓦蒂 K·N·伊森 A·特里帕蒂 E·L·梅斯 J·S·卡治安 R·宾根内尔 于 2020-09-23 设计创作，主要内容包括：公开了一种包括集成字线(WL)触点结构的存储器阵列。存储器阵列包括多个WL,多个WL至少包括第一WL和第二WL。集成WL触点结构包括分别用于第一WL和第二WL的第一WL触点和第二WL触点。第二WL触点延伸穿过第一WL触点。例如,第二WL触点嵌套在第一WL触点内。中间隔离材料将第二WL触点与第一WL触点隔离。在示例中,第二WL触点延伸穿过第一WL中的孔以到达第二WL。隔离材料将第二WL触点与第一WL中的孔的侧壁隔离。(A memory array including an integrated Word Line (WL) contact structure is disclosed. The memory array includes a plurality of WLs including at least a first WL and a second WL. The integrated WL contact structure includes first and second WL contacts for the first and second WLs, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. The intermediate isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.)

1. A memory array, comprising:

a plurality of Word Lines (WLs) including at least a first WL and a second WL;

a first WL contact and a second WL contact for the first WL and the second WL, respectively, wherein the second WL contact extends through the first WL contact; and

an isolation structure for isolating the second WL contact from the first WL contact.

2. The memory array of claim 1, wherein the second WL contact extends through a hole in the first WL to reach the second WL, and the isolation structure isolates the second WL contact from a sidewall of the hole in the first WL.

3. The memory array of claim 1, wherein:

the plurality of WLs form a staircase WL structure of the memory array; and is

The second WL is at a lower level of the ladder than the first WL.

4. The memory array of claim 3, wherein a length of the second WL contact is greater than a length of the first WL contact.

5. The memory array of any one of claims 1 to 4, wherein the plurality of WLs includes a third WL, and wherein the memory array further comprises:

a third WL contact for the third WL,

wherein the third WL contact extends through the second WL, an

Wherein the third WL contact is isolated from the second WL contact by an additional isolation structure.

6. The memory array of claim 5, further comprising:

a pillar extending through the first WL, the second WL, and the third WL; and

a plurality of memory cells, wherein each memory cell is located at a corresponding junction of a corresponding pillar and a corresponding WL,

wherein each of the first, second, and third WLs has (i) a first end near which the strut extends, and (ii) an opposite second end near which a corresponding WL contact is coupled, and

wherein second ends of the first, second and third WLs are substantially aligned.

7. The memory array of any one of claims 1 to 4, wherein the plurality of WLs includes a third WL and a fourth WL, and wherein the 3D memory array further comprises:

a third WL contact and a fourth WL contact for the third WL and the fourth WL, respectively, wherein the fourth WL contact extends through the third WL contact and the third WL; and

an additional isolation structure to isolate the fourth WL contact from the third WL contact and the third WL,

wherein the third WL contact and the fourth WL contact do not extend through the first WL and the second WL.

8. The memory array of claim 7, further comprising:

a pillar extending through the first WL, the second WL, and the third WL; and

a plurality of memory cells, wherein each memory cell is located at a corresponding junction of a corresponding pillar and a corresponding WL,

wherein each of the first, second, and third WLs has (i) a first end near which the strut extends, and (ii) an opposite second end near which a corresponding WL contact is coupled;

a second end of the first WL is offset by a first distance with respect to a second end of the second WL;

a second end of the second WL is offset with respect to a second end of the third WL by a second distance; and is

The second distance is greater than the first distance.

9. The memory array of claim 8, wherein the second end of the first WL is substantially aligned with the second end of the second WL such that the first distance is zero or less than 5 nm.

10. The memory array of any one of claims 1 to 4, wherein the isolation structures comprise one or both of a dielectric material or an electrically insulating material.

11. The memory array of any one of claims 1 to 4, wherein the memory array is a three-dimensional (3D) NAND ladder memory array or a 3D NOR ladder memory array.

12. A motherboard, wherein the memory array of any of claims 1 to 4 is attached to the motherboard.

13. A computing system comprising the memory array of any of claims 1 to 4.

14. An integrated circuit memory, comprising:

a first Word Line (WL), a second WL, a third WL, and a fourth WL;

a pillar extending through the first WL, the second WL, the third WL, and the fourth WL;

a first WL contact structure comprising first and second WL contacts for the first and second WLs, respectively; and

a second WL contact structure comprising third and fourth WL contacts for the third and fourth WLs, respectively.

15. The integrated circuit memory of claim 14, wherein the second WL contact is nested within the first WL contact, and wherein the fourth WL contact is nested within the third WL contact.

16. The integrated circuit memory of claim 14 or 15, wherein:

the first WL contact structure comprises a first dielectric material for isolating the first WL contact from the second WL contact; and is

The second WL contact structure includes a second dielectric material for isolating the third WL contact from the fourth WL contact.

17. The integrated-circuit memory of claim 16 wherein:

the second WL contact extends through a first opening in the first WL and is isolated from sidewalls of the first opening in the first WL by the first dielectric material; and is

The fourth WL contact extends through a second opening in the third WL and is isolated from sidewalls of the second opening in the third WL by the second dielectric material.

18. A method for forming a memory array, the method comprising:

forming a first Word Line (WL) and a second WL;

forming a first WL contact coupled to the first WL, wherein a first via extends through the first WL contact and the first WL;

forming a dielectric layer within sidewalls of the first via, wherein a second via extends through the dielectric layer; and is

Depositing a conductive material within the second via to form a second WL contact, such that the second WL contact (i) extends through the first WL contact and the first WL, and (ii) is isolated from the first WL contact and the first WL by the dielectric layer.

19. The method of claim 18, wherein the dielectric layer is a first dielectric layer, and wherein forming the first WL contact comprises:

forming a second dielectric layer over the first WL;

etching the second dielectric layer to form an opening exposing the first WL; and

conformally depositing a conductive material on sidewalls of the first dielectric layer through the opening to form the first WL contact, wherein the first via extends through the first WL contact.

20. The method of claim 19, wherein a portion of the first WL is exposed through the first via, and wherein the method further comprises:

removing the portion of the first WL such that the first via extends through the portion of the first WL.

Background

Flash memory, such as NAND flash memory, is a non-volatile storage medium. Three-dimensional (3D) flash memory arrays typically include a plurality of Word Lines (WLs) arranged in a staggered or "staircase" fashion such that each WL is at a corresponding particular distance from the top of the memory array. The WLs located in the lower or deeper portions of the staircase are at a relatively longer distance from the top of the memory array than the WLs located in the higher or shallower portions of the staircase. A plurality of WL contacts are formed for a corresponding plurality of WLs. As more and more levels of memory cells are packaged within the memory array (i.e., as the number of WLs increases), the WL contacts extend deeper into the array to reach the WLs at the opposite bottom of the staircase. Thus, as the number of levels of memory cells in modern memory arrays increases, the aspect ratio of WL contacts increases in order to maintain the same die size. For example, a deeper WL contact for contacting a WL at the deeper end of the step has a relatively higher aspect ratio. Many challenges remain for such high aspect ratio WL contacts.

Drawings

Fig. 1 illustrates a cross-sectional view of a memory array including a plurality of Word Lines (WLs) and a corresponding plurality of WL contacts, wherein the WL contacts extend through and are isolated from another WL contact, according to some embodiments of the present disclosure.

Fig. 2A-2C each illustrate an exemplary top view of a cross-section of an integrated WL contact structure, according to some embodiments of the present disclosure.

Fig. 2D illustrates an example cross-sectional side view of an integrated WL contact structure, wherein a middle isolation layer between two WL contacts of the integrated WL contact structure extends up to the bottom of an upper WL of a corresponding WL group, according to some embodiments of the present disclosure.

Fig. 2E illustrates a perspective view of an integrated WL contact structure of a memory array, according to some embodiments of the present disclosure.

Fig. 3A, 3B illustrate example alignments of WLs in a group of WLs according to some embodiments of the present disclosure.

Fig. 4A, 4B illustrate an example memory array in which an integrated WL contact structure includes WL contacts for more than two WLs, according to some embodiments of the present disclosure.

Fig. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, and 5L collectively illustrate a method for forming an integrated WL contact structure for a memory array or other staircase structure, according to some embodiments of the present disclosure.

FIG. 6A shows a memory array including WLs and corresponding WL contacts, where none of the WL contacts are nested within another WL contact; and fig. 6B illustrates a memory array including WL and corresponding WL contacts, where the WL contacts nest within another corresponding WL contact to provide an integrated WL contact structure in accordance with one or more embodiments of the present disclosure.

FIG. 7 illustrates an example computing system implemented with the memory structures disclosed herein in accordance with one or more embodiments of the present disclosure.

Detailed Description

Disclosed herein is a three-dimensional (3D) memory array comprising a plurality of Word Lines (WLs) and a corresponding plurality of WL contacts. In some embodiments, the WLs are arranged in a plurality of WL groups, each WL group including a corresponding two or more WLs. The WL contacts of each WL group are nested or otherwise combined to form a corresponding integrated WL contact structure. In an example embodiment where each WL group includes two WLs (e.g., an upper WL and a lower WL), the integrated WL contact structure includes an inner WL contact nested within an outer WL contact, where an intermediate isolation layer (e.g., comprising a dielectric material and/or an electrically insulating material) electrically and physically isolates the inner and outer WL contacts. In one such embodiment, the outer WL contact is coupled to an upper WL of the corresponding WL group, and the inner WL contact is coupled to a lower WL of the corresponding WL group. According to some such embodiments, the inner WL contact extends through the outer WL contact and also through a through-hole in the upper WL to reach the lower WL. The inner WL contacts are not in physical or electrical contact with the sidewalls of the vias in the upper WL because the intervening isolation layer further isolates the inner WL contacts from the sidewalls of the vias in the upper WL. Many configurations will be appreciated.

General overview

As previously discussed herein, many challenges remain with respect to high aspect ratio WL contacts. For example, etching deep holes for relatively deep WL contacts is particularly challenging. In more detail, the Critical Dimension (CD) of the WL contact is the width of the contact measured at the top cross section of the contact. Increasing the CD of the WL contact causes the WL contact to have a relatively lower aspect ratio, thereby facilitating the etching process and/or allowing more memory levels to be added. However, the maximum CD of the deepest WL contact is constrained by the WL contact pitch and the minimum end-to-end (METE) distance between two adjacent WL contacts. For this reason, increasing CD leads to undesirable effects: the width of the WL is correspondingly increased and thus the footprint of the memory array is increased.

Accordingly, the present disclosure provides an integrated WL contact structure that allows for an increase in the CD of the WL contact without a corresponding increase in the WL width and/or the size of the memory array. For example, consider the following example case: the WLs of a given memory array are arranged in a ladder fashion, with each WL at a certain distance from the top of the memory array. In some such embodiments, the WLs are grouped into a plurality of WL groups. Each WL group includes two or more consecutive or adjacent WLs. The WLs of a particular WL group share a corresponding integrated WL contact structure.

For example, assume a group of WLs comprising a first WL and an adjacent second WL, wherein the first WL is at a higher level in the ladder than the second WL. Thus, the first WL is also referred to herein as the "upper WL" of the WL group, and the second WL is also referred to as the "lower WL" of the WL group, to reflect their relative positions with respect to the ladder. The memory array also includes a first WL contact for an upper WL and a second WL contact for a lower WL. In some embodiments, the first and second WL contacts are combined to form an integrated WL contact structure. In some embodiments, the second WL contact is nested within the first WL contact. Because the second WL contact is nested within the first WL contact, the first WL contact is also referred to herein as an "outer WL contact", and the second WL contact is also referred to herein as an "inner WL contact". In some embodiments, the inner WL contact extends through the outer WL contact, and the two WL contacts are physically and electrically isolated by an intermediate isolation layer or isolation structure comprising a dielectric and/or insulating material. In some such embodiments, the outer WL contact physically contacts or is coupled to the upper WL, while the inner WL contact extends through a via in the upper WL to the lower WL and physically contacts or is coupled to the lower WL. The inner WL contacts are not in physical or electrical contact with the sidewalls of the vias in the upper WL because the isolation layer isolates the inner WL contacts from the sidewalls of the vias in the upper WL.

In some embodiments, the first interconnect feature contacts a top portion of the external WL contact to couple the external WL contact with the first routing structure. Similarly, a second interconnect feature contacts a top of the inner WL contact to couple the inner WL contact with a second routing structure.

Although the above examples discuss an integrated WL contact structure with two WL contacts, the integrated WL contact structure may also include more than two WL contacts. In an example where there are three WL contacts in the integrated WL contact structure, the WL contacts may be referred to herein as outer WL contacts, middle WL contacts, and inner WL contacts for the upper WL, middle WL, and lower WL, respectively. The intermediate WL contact is nested within the outer WL contact and is isolated from the outer WL contact by a first isolation layer. Similarly, the inner WL contact is nested within the intermediate WL contact and is isolated from the intermediate WL contact by a second isolation layer. Furthermore, the inner WL contacts extend through the holes in the upper and middle WLs and are isolated from the sidewalls of the holes by the first and second isolation layers. Furthermore, the intermediate contact extends through a hole in the upper WL and is isolated from the sidewall of the hole by a first isolation layer.

Since the integrated WL contact structure is shared between the WLs of a group of WLs, the WLs of the group need not be staggered with respect to each other. In an example, the ends of the upper and lower WLs may now be substantially aligned with the corresponding ends of the lower WL, although in another example the ends of the upper and lower WLs may be staggered. Thus, note that according to some embodiments, a typical ladder architecture is not required, but other embodiments may include a typical ladder architecture.

Because the inner WL contact is nested within the outer WL contact, the outer WL contact has a larger width and a higher CD than when the WL contacts are separated and compared to the independent WL contacts. Thus, the integrated WL contact structure allows for a higher CD for the external WL contacts. The increase in CD of the external WL contacts does not come at the expense of any increase in WL width or memory array size. Rather, the increase in CD of the outer WL contact is due, at least in part, to the inner WL contact extending through the outer WL contact.

The increase in CD causes the aspect ratio of the outer WL contact to correspondingly decrease, which aids in the WL contact formation process. For example, as discussed in further detail herein, the external WL contacts are formed by etching holes within the memory array dielectric. Since the outer WL contacts have a larger CD and a lower aspect ratio, the etching of the holes is relatively easy when forming the outer WL contacts. Since only one integrated WL contact is formed per two WLs, in an example, up to 1.5 times (1.5x) the step width can be utilized for the etching operation when forming the external WL contacts. The larger CD of the deeper WL contacts causes faster etching of the deepest contacts, which results in faster process time and higher margin (margin) for WL contact etch operations to fabricate the memory array without a corresponding increase in the size of the memory array.

As discussed herein, terms referring to directions (e.g., up, down, vertical, horizontal, left, right, front, back, etc.) are used for convenience to describe example embodiments of an integrated circuit depicted in a particular orientation. Embodiments of the present disclosure are not intended to be limited by these directional references.

As used herein, a material that is "compositionally different" or "compositionally distinct" refers to two materials having different chemical compositions. Such compositional differences may be, for example, due to elements being in one material but not in another (e.g., SiGe is compositionally different from silicon), or due to one material having all of the same elements as the second material, but at least one of those elements being intentionally provided in a different concentration in one material relative to the other material (e.g., SiGe having 70 atomic percent germanium is compositionally different from SiGe having 25 atomic percent germanium). In addition to this diversity of chemical compositions, the materials may have different dopants (e.g., gallium and magnesium) or the same dopant, but at different concentrations. In other embodiments, compositionally different materials may also refer to two materials having different crystallographic orientations. For example, (110) silicon may differ or differ in composition from (100) silicon. For example, in the case of blanket wafer layer transfer, creating stacks of different orientations may be achieved.

Note that as used herein, the expression "X includes at least one of a or B" means X that may include, for example, only a, only B, or both a and B. Thus, unless explicitly stated, an X comprising at least one of A or B should not be construed as requiring an X for each of A and B. For example, the expression "X includes a and B" means X that explicitly includes a and B. Furthermore, the same is true for any number of items greater than 2, where "at least one" of those items is included in X. For example, as used herein, the expression "X comprises at least one of A, B or C" means that X may comprise each of a only, B only, C only, a and B only (but not C), a and C only (but not B), B and C only (but not a), or A, B and C. Even though any of A, B or C happened to include multiple types or variations. To this end, unless explicitly stated, an X comprising at least one of A, B or C should not be understood to require an X for each of A, B and C. For example, the expression "X includes A, B and C" refers to X specifically including each of A, B and C. Likewise, the expression "X included in at least one of a or B" refers to X that may be included, for example, in only a, only B, or both a and B. As will be appreciated, the discussion above regarding "X includes at least one of a or B" is equally applicable herein.

Elements referred to herein by a common reference label followed by a particular number or letter may be referred to collectively by the reference label individually. For example, the WLs 108a, … …, 108f of fig. 1 may be collectively and generally referred to as a plural form of the WL108, and a singular form of the WL 108.

Architecture and methodology

Fig. 1 illustrates a cross-sectional view of a memory array (also referred to as an "array") 100 including a plurality of Word Lines (WLs) 104a, … …, 104f and a corresponding plurality of WL contacts 108a, … …, 108f, wherein the WL contact (e.g., WL contact 108b) extends through and is isolated from the corresponding WL contact (e.g., WL contact 108a), according to some embodiments of the present disclosure.

In an example, the array 100 includes any suitable 3D memory array, such as a floating gate flash memory array, a charge trap (e.g., replacement gate) flash memory array, a phase change memory array, a resistive memory array, an ovum memory array, a ferroelectric transistor random access memory (FeTRAM) array, a nanowire memory array, a 3D NAND memory, a 3D NOR memory, or any other 3D memory array. In one example, the memory array 100 is a stacked 3D NAND flash memory array that stacks multiple floating gate or charge trapping flash memory cells in a vertical stack wired in a NAND (not and) manner. In another example, the 3D memory array 100 includes 3D NOR (not or) memory cells. Although only six WLs 104a, … …, 104f are shown for array 100, array 100 may have any suitable number of WLs.

In some embodiments, array 100 includes one or more struts, such as struts 120a, 120b, 120 c. Although only three posts 120 are shown, the array 100 can have any other suitable number of posts, such as one, two, four, or higher. Individual charge storage devices (e.g., memory cells not shown) are formed at or near the corresponding junctions of the corresponding WLs and the corresponding pillars. Thus, a plurality of memory cells are formed in the array 100 in a plurality of locations defined by the engagement of the individual pillars and the individual WLs. The pillars 120a, 120b, 120c are also referred to herein as memory pillars.

In one example, WL108 couples a plurality of memory cells. For example, a plurality of memory cells formed at or near the junctions of WL108a and respective pillars 120a, 120b, 120c are coupled by WL108 a. Charge storage devices coupled by the same WL may be logically grouped into memory pages. In some embodiments, WL108 comprises a conductive material, such as tungsten, polysilicon, a suitable metal, and/or any suitable conductive material.

The array 100 is shown at a high level in FIG. 1, with various components within the array 100 not shown. For example, although not shown, the array 100 includes or is coupled to one or more logic circuits including logic components such as address decoders, state machines, buffers, word line drivers, bit line drivers, sense amplifiers, voltage dividers, charge pumps, digital logic blocks, logic gates, switches, inverters, adders, multipliers, and/or any other suitable components of memory array logic circuits. Similarly, although not shown, the array 100 includes various conductive access lines to enable access to memory cells, such as bit lines, Select Gate Source (SGS) and Select Gate Drain (SGD), current common source (SRC, also referred to as source plate), and/or any other suitable memory access lines.

In some embodiments, the WLs 104 are grouped in multiple groups. For example, WLs 104a, 104b are grouped in a first group 128a, WLs 104c, 104d are grouped in a second group 128b, and WLs 104e, 104f are grouped in a third group 128 c. Although in fig. 1, each WL group includes two WLs, the teachings of the present disclosure are not intended to be so limited, and a WL group may include more than two WLs, such as three WLs (e.g., as discussed with respect to fig. 4A), or a greater number of WLs (e.g., as discussed with respect to fig. 4B). Thus, each WL group includes two or more WLs.

The WLs in each WL group share the WL contacts of the corresponding integrated WL contact structure. For example, the WL contacts of WL group 128a are combined to form integrated WL contact structure 124a, the WL contacts of WL group 128b are combined to form integrated WL contact structure 124b, and the WL contacts of WL group 128c are combined to form integrated WL contact structure 124 c.

The integrated WL contact structure 124a has a WL contact 108b nested within another WL contact 108a and isolated by an intervening isolation layer or isolation structure 112a (also referred to herein as isolation material 112). In an example, the isolation layer 112 includes a dielectric material and/or an electrically insulating material. For example, the integrated WL contact structure 124a has a WL contact 108b that extends through the WL contact 108a and also extends through the WL104 a. For example, WL contact 108b is coupled (e.g., connected) to WL104 b, and WL contact 108a is coupled (e.g., connected) to WL104 a. For example, WL contact 108b is physically attached to WL104 b, and WL contact 108a is physically attached to WL104 a. In some embodiments, WL contact 108b contacts WL104 b and is electrically coupled to WL104 b. Thus, WL contact 108b serves as a contact for WL104 b, and external logic circuitry communicates with WL104 b through WL contact 108 b. Similarly, WL contact 108a contacts WL104a and is electrically coupled to WL104 a. Thus, WL contact 108a serves as a contact for WL104a, and external logic circuitry communicates with WL104a through WL contact 108 a.

WL contact 108b extends through WL104a, and WL contact 108b is isolated from WL104a by isolation layer 112, which isolation layer 112 is also referred to herein as isolation material 112 a. For example, WL104a has an opening or via, and WL contact 108b extends through the via of WL104 a. The WL contact 108b does not touch the sidewall of the via of the WL104 a. For example, WL contact 108b is isolated from the sidewalls of the via of WL104a by isolation material 112 a. Thus, isolation material 112a also extends through the via of WL104a and contacts the sidewall of the via of WL104 a. The isolation material 112a also separates and isolates the WL contact 108b from the WL contact 108 a. Thus, the isolation material 112a physically and electrically isolates the WL contact 108b from the WL104a and the WL contact 108 a.

Thus, for example, the WL contact 108b is nested within the other WL contact 108 a. The inner WL contact 108b is located inside the outer WL contact 108a, and the two WL contacts are electrically and physically isolated from each other by the isolation material 112 a. The outer WL contact 108a is in electrical and physical contact with the upper WL104a, while the inner WL contact 108b is in electrical and physical contact with the lower WL104 b. The inner WL contact 108b extends through a hole in the upper WL104 a. The inner WL contact 108b is physically and electrically isolated from the upper WL104a and the outer WL contact 108a by the isolation material 112 a. As shown, the length of the inner WL contact 108b is greater than the length of the outer WL contact 108 a.

Although the spaces between the integrated WL contact structures 124a, 124b, 124c are shown as empty in fig. 1, in an example, at least a portion of the spaces between the integrated WL contact structures 124a, 124b, 124c are occupied by a suitable dielectric and/or insulating material 135 (e.g., a suitable oxide) that electrically and physically separates the various integrated WL contact structures 124a, 124b, 124 c.

Fig. 2A-2C each illustrate an example top view of a cross-section of an integrated WL contact structure 124a, according to some embodiments of the present disclosure. As can be seen in each of fig. 2A-2C, each WL structure 104a includes an inner WL contact 108b that extends through an outer WL contact 108a, wherein the outer WL contact 108a is separated from the inner WL contact 108a by an isolation material 112A. However, there are some differences between the example embodiments shown. In the example of fig. 2A, the cross-sections 108a and 108b of the WL contacts are substantially circular. Thus, in this example, WL contacts 108a and 108b may be imaged (e.g., by a cross-sectional scanning electron microscope or other imaging equipment) as concentric conical cylinders separated by the separation material 112 a. In some embodiments, the cylinder is tapered such that the width of the top of the cylinder is higher compared to the width of the bottom, see, e.g., fig. 1. In the example of fig. 2B, the cross-sections 108a and 108B of the WL contacts are substantially elliptical. In the example of fig. 2C, the cross-sections 108a and 108b of the WL contacts are substantially rectangular. As will be appreciated in light of this disclosure, the cross-sectional shapes 108a, 108b of the WL contacts may vary, for example, based on the formation technique used.

Referring again to fig. 1, isolation layer 112a extends down to WL104 b, isolation layer 112b extends down to WL104 d, and so on. However, in some example embodiments, isolation layer 112a may extend only down to the bottom of WL104a, isolation layer 112b may extend only down to the bottom of WL104 c, and so on, as shown in fig. 2D. Fig. 2D illustrates an integrated WL contact structure 124' according to some embodiments of the present disclosure, wherein a middle isolation layer 112' (e.g., isolation layer 112a ' between WL contacts 108a, 108b) between two WL contacts of the integrated WL contact structure 124' (e.g., integrated WL contact structure 124a ') extends down to the bottom of an upper WL (e.g., WL104 a) of a corresponding WL group (e.g., WL group 128 a). Thus, isolation layer 112a' extends through WL104a and terminates at the bottom of WL104 a. Note that the isolation layer 112a' is still able to physically and electrically isolate the inner WL contact 108b from (i) the sidewalls of the hole in the upper WL104a and (ii) the outer WL contact 108 a.

Fig. 2E illustrates a perspective view of an integrated WL contact structure 124 of a memory array (e.g., memory array 100 of fig. 1) according to some embodiments of the present disclosure. For example, fig. 2E shows WLs 104a, 104b and an integrated WL contact structure 124 including WL contacts 108a, 108b and a middle spacer layer 112 a. As discussed with respect to fig. 2A-2B, WL contacts 108a, 108B and isolation layer 112A are shown in fig. 2E as concentric cylinders having a slightly circular or elliptical cross-section. In fig. 2E, isolation layer 112a extends up to the bottom of WL104a, as discussed with respect to fig. 1, thereby electrically and physically isolating WL contact 108b from both WL contact 108a and WL104 a.

Also marked in fig. 2E is a layer 215 comprising an insulating material, which is located between any two adjacent WLs. For example, layer 215 exists between WL104a and 104b, between WL104 b and 104c, and so on, but layer 215 is not labeled in fig. 1. Layer 215 is an insulating layer comprising a suitable insulating material, such as an oxide material (e.g., silicon oxide, carbon-doped oxide, or another suitable oxide material), an oxynitride material (e.g., silicon oxynitride), and/or a nitride material (e.g., silicon nitride), and is also referred to as a layered oxide layer.

Also shown in fig. 2E are contact terminals 272a, 272b for the WL contacts 108a, 108b, respectively. For example, the contact terminals 272a, 272b are vias (via) that couple the WL contacts 108a, 108b, respectively, to external circuitry. In this case, note that the wiring layers 276a, 276b are coupled to the contact terminals 272a, 272b, respectively. The contact terminals 272a, 272b and/or the wiring layers 276a, 276b comprise an electrically conductive material, such as a suitable metal. The routing layers 276a, 276b pass signals between the WLs 104a, 104b and external components (e.g., logic circuitry for reading from and/or writing to the memory array 100).

Fig. 3A, 3B illustrate example alignments of WLs in a group of WLs according to some embodiments of the present disclosure. For clarity of illustration, in each of fig. 3A-3B, only WL group 128a including WLs 104a, 104B and WL group 128B including WLs 104c, 104d are shown, and the third WL group 128c is not shown.

In an example, each WL104 has a first end and an opposite second end, wherein the strut extends through a first portion of the WL proximate the first end and the corresponding WL contact is in contact with a second portion of the WL proximate the second end. In fig. 3A, 3B, the first ends of WLs 104a, 104B, 104c, 104d are labeled 302a1, 302B1, 302c1 and 302d1, respectively. Similarly, second ends of WLs 104a, 104b, 104c, 104d are labeled 302a2, 302b2, 302c2, and 302d2, respectively.

In the example of fig. 3A, for WL group 128a including WLs 104a, 104b, second ends 302a2 and 302b2 are substantially aligned. Similarly, for WL group 128b, which includes WLs 104c, 104d, second ends 302c2 and 302d2 are substantially aligned. In contrast, in a 3D memory array without an integrated WL contact structure (e.g., as shown later herein in fig. 6A), all word lines are staggered or arranged in a staircase-like pattern such that none of the two WLs are substantially aligned at the second end. However, because a single integrated WL contact structure is used for multiple WLs of a WL group in the memory array of fig. 3A, the second ends of the multiple WLs of a WL group can now be substantially aligned.

In the example of fig. 3B, for WL group 128a including WLs 104a, 104B, the length of the misalignment of second ends 302a2 and 302B2 is D1. Similarly, for WL group 128b including WLs 104c, 104D, the second ends 302c2 and 302D2 are misaligned by length D1' (which may be equal to D1). Additionally, the second ends 302b2, 302c2 of the respective WLs 104b, 104c are misaligned a distance D2. In some embodiments, D2 is relatively higher than D1 and D1', e.g., 5 times, 10 times, 20 times or higher. The misalignment D1 (or D1') may be intentional or may be an unintentional consequence of process or equipment limitations accompanying the WL formation process.

Note that the distances D1 and D1' in fig. 3B are substantially zero in fig. 3A, wherein substantially zero indicates that the distance D1 is less than a threshold, e.g., 1nm, 2nm, 5nm, 10nm, etc.

In a 3D memory array without an integrated WL contact structure (e.g., as shown later herein in fig. 6A), all word lines are staggered or arranged in a staircase-like pattern with substantially similar misalignment between two adjacent word lines. In contrast, due to the integrated WL contact structure 124 of fig. 3B, the misalignment between two adjacent WLs in fig. 3B depends on whether the two WLs belong to the same WL group or two different WL groups.

In fig. 1-3B, the integrated WL contact structure 124 includes WL contacts for corresponding two WLs. However, the teachings of the present disclosure are not intended to be limited to an integrated WL contact structure that includes WL contacts for only two WLs. For example, fig. 4A illustrates a memory array 400 in accordance with some embodiments of the present disclosure in which an integrated WL contact structure 424 includes WL contacts for more than two WLs. For example, in the example of fig. 4A, integrated WL contact structure 424 includes WL contacts for three WLs 404A, 404b, 404c, and integrated WL contact structure 425 includes WL contacts for three WLs 404d, 404e, 404 f. For example, FIG. 4A shows a WL group 428 comprising three WLs 404A, 404b, 404c and a WL group 429 comprising three WLs 404d, 404e, 404f, but each WL group may comprise more than three WLs. Array 400 may include several such WL groups, with only two WL groups 428, 429 being shown for clarity of illustration. Also shown in fig. 4A are struts 420a, 420b, 420 c.

In some embodiments, the integrated WL contact structure 424 has WL contacts 408a, 408b, and 408c for WL404a, 404b, and 404c, respectively. For example, WL contact 408c extends through WL contact 408b, and WL contact 408b extends through WL contact 408 a. Furthermore, WL contacts 408b, 408c extend through WL404a, and WL contact 408c extends through WL404 b. As shown in fig. 4A, isolation material 412a electrically and physically isolates WL contact 408b from WL contact 408a and WL 404A. Similarly, isolation material 412b electrically and physically isolates WL contact 408c from WL contact 408b and WL404 b. Thus, WL contact 408c is nested within WL contact 408b, and WL contact 408b is nested within WL contact 408 a. The integrated WL contact structure 425 has a similar structure, but for clarity of illustration, the individual components of the integrated WL contact structure 425 are not labeled in fig. 4A.

Fig. 4B illustrates a memory array 401 in which an integrated WL contact structure 464 includes WL contacts for more than two WLs, according to some embodiments of the present disclosure. For example, in the example of fig. 4B, integrated WL contact structure 464 includes WL contacts for six WLs 404a, 404B, 404c, 404d, 404e, and 404f, and integrated WL contact structure 465 includes WL contacts for six WLs 404g, 404h, 404i, 404j, 404k, and 404 l. For example, fig. 4B shows WL group 478 comprising six WLs 404a, … …, 404f and WL group 479 comprising six WLs 404g, … …, 404l, but each WL group may comprise more (or less) than six WLs, e.g., seven, eight, or more number of WLs. The array 401 may include several such WL groups, but only two WL groups 478, 479 are shown for clarity of illustration. Also shown in fig. 4A are struts 420a, 420b, 420 c.

In some embodiments, the integrated WL contact structure 464 has WL contacts 408a, 408b, 408c, 408d, 408e, 408f for the WLs 404a, … …, 404f, respectively. For example, WL contact 408c extends through WL contact 408b, WL contact 408b extends through WL contact 408a, and so on. Also shown are isolation materials 412a, … …, 412e, each of which is interposed between two corresponding WL contacts. The integrated WL contact structure 464 will be apparent to those skilled in the art based on a discussion of various other integrated WL contact structures discussed herein, and therefore, the integrated WL contact structure 464 will not be discussed in further detail. The integrated WL contact structure 465 has a similar structure, but for purposes of clarity of illustration, the individual components of the integrated WL contact structure 465 are not labeled in fig. 4B.

As shown in fig. 4A-4B (and also discussed with respect to fig. 3A), the WLs of the WL group need not be formed as "ladders". For example, in fig. 4B, the ends of WLs 404a, … …, 404f may be substantially aligned, or may be slightly misaligned as a result of process and/or equipment limitations in the technology that accompany the formation of the WLs, as discussed with respect to fig. 3A-3B.

Fig. 5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, and 5L collectively illustrate a method for forming an integrated WL contact structure of the memory array 100 of fig. 1, according to some embodiments of the present disclosure. These figures show a cross-sectional view of the array 100 and form the array 100. Referring to fig. 5A, WLs 104a, … …, 104f are shown. Isolation material 502 and etch stop material 504 are also shown. Voids 501a, 501b, 501c are defined within the isolation material 502, and individual integrated WL contact structures will be formed in such voids, as will be discussed in more detail herein. Any suitable isolation material commonly used in memory arrays may be used in fig. 5A. Although not shown, the voids 501a, 501b, 501c are formed by depositing an isolation material 502 on the WL and selectively etching the isolation material 502.

In fig. 5B, a layer 508 comprising a conductive material is conformally deposited within the voids 501a, 501B, 501c and over the etch stop layer 504. For example, the conductive material of layer 508 includes a metal and/or any other suitable conductive material. In some embodiments, deposition is performed using Chemical Vapor Deposition (CVD), plasma-enhanced chemical vapor deposition (PE-CVD), Atomic Layer Deposition (ALD), plasma-enhanced atomic layer deposition (PE-ALD), Physical Vapor Deposition (PVD), and/or any suitable deposition technique.

Referring now to fig. 5C, portions of layer 508 are etched such that WL contact 108a is formed on the sidewall of void 501a from layer 508. Similarly, WL contact 108c is formed on the sidewall of void 501b, and WL contact 108e is formed on the sidewall of void 501 c. Thus, such portions of layer 508 are etched: above the etch stop layer 504 and on the bottom of the voids 501a, 501b, 501 c. In some embodiments, portions of layer 508 are anisotropically etched (e.g., dry directional etching).

Referring now to fig. 5D, the portions of WLs 104a, 104c, 104e exposed through voids 501a, 501b, 501c, respectively, are removed. In some embodiments, portions of the WLs 104a, 104c, 104e are anisotropically etched (e.g., dry-directionally etched). In some embodiments, the etching is selective such that exposed WLs are removed without removing the WL contacts 108a, 108b, 108 c.

Referring now to fig. 5E, a layer 512 comprising an isolation material (e.g., a dielectric material and/or an electrically insulating material) is conformally deposited within the voids 501a, 501b, 501c and over the etch stop layer 504. The material of layer 512 includes, for example, any suitable isolation material used in memory arrays. In some embodiments, deposition is performed using CVD, PE-CVD, ALD, PE-ALD, PVD, and/or any suitable deposition technique.

Referring now to fig. 5F, portions of layer 512 are etched to form isolation layers 112a, 112b, 112c within voids 501a, 501b, 501c, respectively. Thus, such portions of layer 512 are etched: above the etch stop layer 504 and on the bottom of the voids 501a, 501b, 501 c. In some embodiments, portions of layer 512 are anisotropically etched (e.g., dry directional etched).

Fig. 5F also shows a top view of a portion of WL104a (the portion shown with dashed lines). For example, the isolation material 112a is nested within the WL contact 108 a. Also, in top view, the lower WL104 b is visible through the void 501a within the isolation material 112 a. In the example of fig. 5F, the top view of WL contact 108a and isolation material 112A is oval-however, as discussed with respect to fig. 2A-2c, any other suitable shape is possible.

Referring now to fig. 5G, a layer 514 comprising a conductive material such as a metal is deposited within the voids 501a, 501b, 501c and on top of the etch stop layer 504. In some embodiments, deposition is performed using CVD, PE-CVD, ALD, PE-ALD, PVD, and/or any suitable deposition technique.

Referring now to fig. 5H, layer 514 is selectively removed, thereby forming WL contacts 108b, 108d, and 108f from layer 514. For example, removing the top of layer 514 may be performed using a suitable etching operation, a polishing operation (e.g., Chemical Mechanical Polishing (CMP)), and/or a suitable removal operation.

As previously discussed herein, for example, the WL contact 108b is nested within the other WL contact 108 a. The inner WL contact 108b is located inside the outer WL contact 108a, and the two WL contacts 108a, 108b are electrically and physically isolated from each other by an isolation material 112 a. In some embodiments, the inner WL contact 108b is self-aligned with the outer WL contact 108 a. For example, after forming the outer WL contact 108a in fig. 5C, 5D, the isolation material 112a is conformally deposited in fig. 5E, 5F. Subsequently, layer 514 is deposited in fig. 5G to form WL contact 108 b. Due to the conformal deposition of the isolation material 112a, the WL contact 108b is self-aligned with the WL contact 108 a. The inner WL contact 108b is embedded within the outer WL contact 108 a.

Referring now to fig. 5I, a layer 520 comprising an insulating material is deposited on top of the array 100 such that the layer 520 covers the isolation layer 112 and the exposed top of the WL contacts 108. In some embodiments, deposition is performed using CVD, PE-CVD, ALD, PE-ALD, PVD, and/or any suitable deposition technique. Referring now to fig. 5J, layer 520 is patterned to expose portions of the tops of WL contacts 108a, … …, 108 f. The remaining portion of layer 520 still masks the isolation layers 112a, 112b, 112c and the etch stop layer 504.

Referring now to fig. 5K, a layer 530 comprising a conductive material such as a metal is deposited on top of the array 100 such that the layer 530 covers the patterned layer 520 and the exposed top of the WL contacts 108. In some embodiments, deposition is performed using CVD, PE-CVD, ALD, PE-ALD, PVD, and/or any suitable deposition technique. Referring now to fig. 5L, the top of layer 530 is removed, such as by a polishing operation (e.g., a CMP operation). The remaining portions of layer 530 form terminals 272a, … …, 272f (terminals are discussed with respect to fig. 2E) for WL contacts 108a, … …, 108f, respectively.

The resulting array 100 of fig. 5L is similar to the array shown in fig. 1. It may be noted that there are some visual differences between the two arrays shown in fig. 1 and 5L. For example, in fig. 1, the integrated WL contact structure 124 is shown to have a somewhat tapered shape. Such a taper may be present in the sidewalls of the isolation material 502 in fig. 5A. Such tapering may be intentional or may be a result of process and/or equipment limitations in the techniques that accompany the formation of voids 501a, 501b, 501c using an etch within isolation material 502 in fig. 5A. Because the WL contact 108 and the isolation material 112 are conformally deposited, the tapered shape of the voids 501a, 501b, 501c also propagates to the WL contact 108 and the isolation material 112, as shown in fig. 1. However, for purposes of clarity of illustration, the tapering of the various layers is shown in FIGS. 5A-5L.

Furthermore, for purposes of clarity of illustration, the isolation layer 502 (shown in fig. 5A-5L) separating the integrated WL contact structure 124 is not shown in fig. 1. Additionally, although fig. 5L shows terminals 272a, … …, 272f, these terminals are not shown in fig. 1 for the sake of brevity. Also, for purposes of brevity, the layers 504, 520 shown in FIG. 5L are not shown in FIG. 1.

FIG. 6A shows a memory array 600 including WL 604a, … …, 604f and corresponding WL contacts 608a, … …, 608f, where none of the WL contacts of FIG. 6A are nested within another WL contact; and fig. 6B illustrates the memory array 100 of fig. 1 including WL104a, … …, 104f and respective WL contacts 108a, … …, 108f, wherein the WL contact of fig. 6B is nested within another corresponding WL contact, in accordance with one or more embodiments of the present disclosure. The array 600 of FIG. 6A is similar to a conventional memory array.

In fig. 6A, pitch P1 of WL contact 608, meter (minimum end-to-end distance) between two WL contacts, and critical dimension CD, which is the width of the WL contact at its top end, are shown. The aspect ratio of the WL contact is the ratio of (i) the depth of the WL contact to (ii) the CD of the WL contact.

In 3D memory arrays, WL contact etching relies on the concept of Aspect Ratio Dependent Etching (ARDE) to allow WL contacts to fall on WLs of different depths simultaneously. For example, the depth of the various WL contacts is different, where the depth of WL contact 608f is higher than the depth of WL contact 608 a.

In an example, it may be beneficial to increase the CD of deeper contacts. In particular, it may be beneficial to increase the CD of the deepest contact (i.e., contact 608f in the example of fig. 6A). For example, increasing the CD of contact 608f provides better margin to balance the penetration of shallow contacts and underetching of deeper contacts. In other words, increasing the CD of the deepest contact results in a lower aspect ratio of the deepest contact, making it relatively easy to etch the WL contact at the deep end. However, in FIG. 6A, the CD of the deepest WL contact is limited by: (i) WL contact pitch P1 (e.g., whose scaling is limited by step width and die size) and/or (ii) minimum end-to-end specifications, as defined by subdivision requirements. Thus, these constraints define an upper limit on the CD of the deepest contact 608f, and the CD cannot be increased beyond the threshold. In other words, an increase in the maximum CD of the deepest contact affects (e.g., increases) the step width and/or die size, which may be undesirable.

In contrast, the integrated WL contact structure of the array 100 of fig. 6B allows for an increase in WL contact CD without affecting die size, and thus an increase in etch margin. For example, in a given integrated WL contact structure (e.g., integrated WL contact structure 124c), the external WL contact (e.g., WL contact 108e) is formed by an etching operation. For example, the isolation material 502 must be etched to form the void 501c in fig. 5A. The inner WL contact (e.g., WL contact 108f) is simply embedded within the outer WL contact, and thus the inner WL contact is not formed by an etching operation. Since only one WL contact structure is formed per two WLs, in an example, up to 1.5 times (1.5x) the step width can now be utilized for the etching operation when forming the outer WL contacts. In other words, embedding the internal WL contacts within the external WL contacts allows the CD of the external WL contacts to be increased without a corresponding increase in the width of the WLs and/or without a corresponding increase in the size of the memory array. Thus, embedding the inner WL contacts in the outer WL contacts allows for an increase in the CD of the outer and inner WL contacts. For example, fig. 6B shows a top view of the integrated WL contact structure 124c, where the CDs of the WL contacts 108e, 108f are shown. The CD of the WL contacts 108e, 108f of fig. 6B may be made substantially larger than the CD of the WL contact 608f of fig. 6A for the same size of the arrays 100 and 600. For example only, given the same dimensions of memory arrays 100 and 600, the CD of WL contact 608f may be approximately 250 nanometers (nm), while the CD of WL contact 608e may be approximately 600 nm. Thus, the integrated WL contact structure of the array 100 of fig. 6B allows for an increase in WL contact CD even for deeper WL contacts. This allows a higher margin when modulating ARDE. Furthermore, the larger CD of the deeper WL contacts causes faster etching of the deepest contacts, which results in faster processing time and higher margin for WL etch operations to fabricate the memory array without a corresponding increase in memory array size.

FIG. 7 illustrates an example computing system implemented with the memory structures disclosed herein in accordance with one or more embodiments of the present disclosure. As can be seen, the computing system 2000 houses a motherboard 2002. The motherboard 2002 may include a plurality of components, including but not limited to a processor 2004 and at least one communication chip 2006, each of which may be physically and electrically coupled to the motherboard 2002 or otherwise integrated in the motherboard 2002. It should be appreciated that the motherboard 2002 may be, for example, any printed circuit board, whether a motherboard, a daughter board mounted to a motherboard, or the only board of the system 2000, among others.

Depending on its application, the computing system 2000 may include one or more other components, which may or may not be physically and electrically coupled to the motherboard 2002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory such as 3D NAND flash memory), a graphics processor, a digital signal processor, an encryption processor, a chipset, an antenna, a display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a Global Positioning System (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., hard disk drive, Compact Disc (CD), Digital Versatile Disc (DVD), etc.). In some embodiments, the functions may be integrated into one or more chips (e.g., note that the communication chip 2006 may be part of the processor 2004 or otherwise integrated into the processor 2004).

Any memory included in the computing system 2000, for example, any 3D memory (e.g., 3D flash memory, 3D NAND flash memory, 3D NOR memory, or any other suitable 3D memory discussed in this disclosure), may include one or more memory arrays including integrated WL contact structures as discussed herein.

The communication chip 2006 enables wireless communication for data transfer to and from the computing system 2000. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, but in some embodiments they may not. The communication chip 2006 may implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA +, HSDPA +, HSUPA +, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocol known as 3G, 4G, 5G, and higher releases. The computing system 2000 may include a plurality of communication chips 2006. For example, a first communication chip 2006 may be dedicated to shorter range wireless communications, such as Wi-Fi and Bluetooth, while a second communication chip 2006 may be dedicated to longer range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and the like.

The processor 2004 of the computing system 2000 includes an integrated circuit die packaged within the processor 2004. The term "processor" may refer to any device or portion of a device that processes electronic data, e.g., from registers and/or memory, to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 2006 may also include an integrated circuit die packaged within the communication chip 2006. As will be understood in light of this disclosure, it is noted that multi-standard wireless capabilities can be integrated directly into the processor 2004 (e.g., where the functionality of any chip 2006 is integrated into the processor 2004, rather than having a separate communication chip). It is further noted that the processor 2004 may be a chipset having such wireless capabilities. In short, any number of processors 2004 and/or communication chips 2006 may be used. Also, any one chip or chipset may have multiple functions integrated therein.

In various embodiments, the computing system 2000 may be a laptop computer, a netbook, a notebook computer, a smartphone, a tablet, a Personal Digital Assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices, as variously described herein.

Further example embodiments

Many variations and configurations will be apparent in light of this disclosure and the following examples.

Example 1. a memory array, comprising: a plurality of Word Lines (WLs) including at least a first WL and a second WL; a first WL contact and a second WL contact for the first WL and the second WL, respectively, wherein the second WL contact extends through the first WL contact; and an isolation structure for isolating the second WL contact from the first WL contact.

The memory array of example 1, wherein the second WL contact extends through a hole in the first WL to reach the second WL, and the isolation structure isolates the second WL contact from a sidewall of the hole in the first WL.

Example 3. the memory array of example 2, wherein the isolation structure extends through the hole in the first WL and lands on the second WL.

Example 4. the memory array of any of examples 1-3, wherein: the plurality of WLs form a staircase WL structure of the memory array; and the second WL is at a lower level of the ladder than the first WL.

Example 5. the memory array of example 4, wherein the length of the second WL contact is greater than the length of the first WL contact.

The memory array of any of examples 1-5, wherein the plurality of WLs includes a third WL, and wherein the memory array further comprises: a third WL contact for the third WL, wherein the third WL contact extends through the second WL, and wherein the third WL contact is isolated from the second WL contact by an additional isolation structure.

Example 6a. the memory array of example 6, further comprising: a pillar extending through the first WL, the second WL, and the third WL; and a plurality of memory cells, wherein each memory cell is located at a corresponding junction of a corresponding pillar and a corresponding WL, wherein each of the first, second, and third WLs has (i) a first end near which the pillar extends, and (ii) an opposite second end near which a corresponding WL contact is coupled, and wherein the second ends of the first, second, and third WLs are substantially aligned.

Example 7. the memory array of any of examples 1-6, wherein the plurality of WLs includes a third WL and a fourth WL, and wherein the 3D memory array further comprises: a third WL contact and a fourth WL contact for the third WL and the fourth WL, respectively, wherein the fourth WL contact extends through the third WL contact and the third WL; and an additional isolation structure for isolating the fourth WL contact from the third WL contact and the third WL.

Example 8. the memory array of example 7, further comprising: a strut extending through the plurality of WLs; and a plurality of memory cells, wherein each memory cell is at a corresponding junction of a corresponding pillar and a corresponding WL.

Example 9. the memory array of example 8, wherein: the first, second, and third WLs are WLs of the plurality of WLs; and each of the first, second, and third WLs having (i) a first end near which the strut extends, and (ii) an opposite second end near which a corresponding WL contact is coupled; a second end of the first WL is offset by a first distance with respect to a second end of the second WL; a second end of the second WL is offset with respect to a second end of the third WL by a second distance; and the second distance is greater than the first distance.

Example 10 the memory array of example 9, wherein the second end of the first WL is substantially aligned with the second end of the second WL such that the first distance is zero or less than 5 nm.

Example 10a. the memory array of any one of examples 1-10, wherein the isolation structure comprises one or both of a dielectric material or an electrically insulating material.

Example 11. the memory array of any of examples 1-10a, wherein the memory array is a flash memory array.

Example 12. the memory array of any of examples 1-11, wherein the memory array is a three-dimensional (3D) NAND ladder memory array.

Example 13. a motherboard, wherein the memory array of any of examples 1-12 is attached to the motherboard.

Example 14. a computing system, comprising the memory array of any of examples 1-13.

Example 15. an integrated circuit memory, comprising: a first Word Line (WL), a second WL, a third WL, and a fourth WL; a pillar extending through the first WL, the second WL, the third WL, and the fourth WL; a first WL contact structure comprising first and second WL contacts for the first and second WLs, respectively; and a second WL contact structure comprising a third WL contact and a fourth WL contact for the third WL and the fourth WL, respectively.

The integrated circuit memory of example 15 of example 16, wherein the second WL contact is nested within the first WL contact, and wherein the fourth WL contact is nested within the third WL contact.

Example 17. the integrated circuit memory of any of examples 15-16, wherein: the first WL contact structure comprises a first dielectric material for isolating the first WL contact from the second WL contact; and the second WL contact structure includes a second dielectric material for isolating the third WL contact from the fourth WL contact.

Example 18. the integrated circuit memory of example 17, wherein: the second WL contact extends through a first opening in the first WL and is isolated from sidewalls of the first opening in the first WL by the first dielectric material; and the fourth WL contact extends through a second opening in the third WL and is isolated from sidewalls of the second opening in the third WL by the second dielectric material.

Example 19. the integrated circuit memory of any of examples 15-18, further comprising: a fifth WL, wherein the first WL contact structure further comprises a fifth WL contact for the fifth WL.

Example 20. the integrated circuit memory of example 19, wherein: the second WL contact is nested within the first WL contact; and is a fifth WL contact nested within the second WL contact.

Example 21 the integrated circuit memory of example 20, wherein the first WL contact structure further comprises: a first dielectric material for isolating the first WL contact from the second WL contact; and a second dielectric material for isolating the second WL contact from the fifth WL contact.

Example 22 the integrated circuit memory of any of examples 15-21, wherein: the first WL, the second WL, and the third WL are three WLs of the integrated circuit memory; each of the first, second, and third WLs having (i) a first end near which the strut extends, and (ii) an opposite second end near which a corresponding WL contact is coupled; a second end of the first WL is offset by a first distance with respect to a second end of the second WL; a second end of the second WL is offset with respect to a second end of the third WL by a second distance; and the second distance is greater than the first distance.

Example 23. the integrated circuit memory of example 22, wherein the first distance is zero or less than 10 nm.

Example 24. the integrated circuit memory of any of examples 15-23, wherein the integrated circuit memory is a three-dimensional (3D) NAND staircase flash memory array.

Example 25. a motherboard, wherein the integrated circuit memory according to any of examples 15-24 is attached to the motherboard.

Example 26. a computing system comprising the integrated circuit memory of any of examples 15-25.

Example 27 a method for forming a memory array, the method comprising: forming a first Word Line (WL) and a second WL; forming a first WL contact coupled to the first WL, wherein a first via extends through the first WL contact and the first WL; forming a dielectric layer within sidewalls of the first via, wherein a second via extends through the dielectric layer; and depositing a conductive material within the second via to form a second WL contact such that the second WL contact (i) extends through the first WL contact and the first WL, and (ii) is isolated from the first WL contact and the first WL by the dielectric layer.

Example 28 the method of example 27, wherein the dielectric layer is a first dielectric layer, and wherein forming the first WL contact includes: forming a second dielectric layer over the first WL; etching the second dielectric layer to form an opening exposing the first WL; and conformally depositing a conductive material on sidewalls of the first dielectric layer through the opening to form the first WL contact, wherein the first via extends through the first WL contact.

Example 29. the method of example 28, wherein a portion of the first WL is exposed through the first via, and wherein the method further comprises: removing the portion of the first WL such that the first via extends through the portion of the first WL.

Example 30. the method of example 28, wherein the second WL contact extends through the first WL contact and the first WL, and is in physical contact with the second WL.

Example 31 the method of any of examples 27-30, wherein a third via extends through the second WL contact, wherein the dielectric layer is a first dielectric layer, and wherein the method comprises: forming a second dielectric layer within sidewalls of the third via, wherein a fourth via extends through the second dielectric layer; and depositing another conductive material within the fourth via to form a third WL contact, such that third WL contact (i) extends through the second WL contact and the second WL, and (ii) is isolated from the second WL contact and the second WL by the second dielectric layer.

The foregoing detailed description has been presented for purposes of illustration. It is not intended to be exhaustive or to limit the disclosure to the precise form described. Many modifications and variations are possible in light of this disclosure. It is therefore intended that the scope of the application be limited not by this detailed description, but rather by the claims appended hereto. Future filed applications claiming priority to the present application may claim the disclosed subject matter in different ways, and may generally include any set of one or more limitations that are disclosed or otherwise presented in various ways herein.