阅读说明：本技术 3d nand存储器及其形成方法 (3D NAND memory and forming method thereof ) 是由 李兆松 肖莉红 刘沙沙 卢峰 王恩博 邵明 王浩 杨号号 张勇 于 2019-01-31 设计创作，主要内容包括：本发明涉及一种3D NAND存储器及其形成方法。所述3D NAND存储器的所述形成方法包括：提供半导体衬底,所述半导体衬底上形成有第一堆叠结构,所述第一堆叠结构中具有第一沟道孔,所述第一沟道孔底部的半导体衬底中具有凹槽；在所述凹槽中形成半导体外延层；在所述半导体外延层表面形成金属硅化物层；在所述第一沟道孔侧壁和底部上形成电荷存储层；刻蚀所述第一沟道孔底部上的电荷存储层以及部分金属硅化物层,形成暴露出半导体外延层表面的开口；在所述开口中形成第二沟道层,所述第二沟道层与所述半导体外延层相接触。本发明保证第一沟道孔的特征尺寸保持不变或变化很小,从而保证工艺的稳定性。(The invention relates to a 3D NAND memory and a forming method thereof. The forming method of the 3D NAND memory comprises the following steps: providing a semiconductor substrate, wherein a first stacked structure is formed on the semiconductor substrate, a first channel hole is formed in the first stacked structure, and a groove is formed in the semiconductor substrate at the bottom of the first channel hole; forming a semiconductor epitaxial layer in the groove; forming a metal silicide layer on the surface of the semiconductor epitaxial layer; forming a charge storage layer on the sidewall and the bottom of the first channel hole; etching the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer; and forming a second channel layer in the opening, wherein the second channel layer is in contact with the semiconductor epitaxial layer. The invention ensures that the characteristic dimension of the first channel hole is kept unchanged or has small change, thereby ensuring the stability of the process.)

1. A method for forming a 3D NAND memory, comprising:

providing a semiconductor substrate, wherein a first stacked structure formed by alternately stacking a sacrificial layer and an isolation layer is formed on the semiconductor substrate, a first channel hole penetrating through the thickness of the first stacked structure is formed in the first stacked structure, and a groove is formed in the semiconductor substrate at the bottom of the first channel hole;

forming a semiconductor epitaxial layer in the groove;

forming a metal silicide layer on the surface of the semiconductor epitaxial layer;

forming a charge storage layer on the sidewall and the bottom of the first channel hole;

etching the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer;

and forming a second channel layer in the opening, wherein the second channel layer is in contact with the semiconductor epitaxial layer.

2. The method of forming a 3D NAND memory as claimed in claim 1, wherein the metal silicide layer is formed by a process comprising: forming metal layers on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing to enable the metal layer to react with the semiconductor epitaxial layer to form a metal silicide layer; removing the unreacted metal.

3. The method of forming a 3D NAND memory of claim 2 wherein the annealing atmosphere is an inert gas and the annealing temperature is less than 600 degrees celsius.

4. The method of forming a 3D NAND memory of claim 1 wherein the etch selectivity of the metal silicide layer relative to the charge storage layer and the semiconductor epitaxial layer is at least greater than 2: 1.

5. The method of forming a 3D NAND memory of claim 1, further comprising:

forming a first channel layer on the charge storage layer; and etching the first channel layer, the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing out of the surface of the semiconductor epitaxial layer.

6. The method of forming a 3D NAND memory as claimed in claim 5, wherein the step of forming the second channel layer in the opening comprises:

removing the first channel layer;

a second channel layer is formed on the surface of the charge storage layer and the surfaces of the bottom and the side walls of the opening.

7. The method of forming a 3D NAND memory as claimed in claim 5, wherein the step of forming the second channel layer in the opening comprises:

and reserving the first channel layer, and forming a second channel layer on the surface of the first channel layer and the surfaces of the bottom and the side wall of the opening.

8. The method of forming a 3D NAND memory of claim 1, further comprising:

filling a channel hole sacrificial layer in the first channel hole;

a second stacked structure in which sacrificial layers and isolation layers formed on the first stacked structure are alternately stacked; a second channel hole penetrating through the thickness of the second stacked structure is formed in the second stacked structure and is communicated with the first channel hole;

removing the channel hole sacrificial layer;

and forming a charge storage layer on the side walls and the bottom of the first channel hole and the second channel hole.

9. The method for forming a 3D NAND memory as claimed in claim 1 or 8, wherein the sacrificial layer is replaced with a control gate.

10. A3D NAND memory, comprising:

the semiconductor device comprises a semiconductor substrate, and a first stacked structure, wherein control gates and isolation layers are alternately stacked on the semiconductor substrate, a first channel hole penetrating through the thickness of the first stacked structure is formed in the first stacked structure, a groove is formed in the semiconductor substrate at the bottom of the first channel hole, and a semiconductor epitaxial layer is formed in the groove;

the metal silicide layer is positioned on the surface of the semiconductor epitaxial layer;

a charge storage layer on sidewalls and a bottom of the first channel hole;

a second channel layer on the charge storage layer, the second channel layer in contact with the semiconductor epitaxial layer.

11. The 3D NAND memory of claim 10 wherein the etch selectivity of the metal silicide layer relative to the charge storage layer and the semiconductor epitaxial layer is at least greater than 2: 1.

12. The 3D NAND memory of claim 10 wherein the metal silicide layer is of a material of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, or titanium silicide.

13. The 3D NAND memory of claim 10 wherein the charge storage layer comprises a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.

14. The 3D NAND memory of claim 10 further comprising:

a first channel layer on the charge storage layer;

and an opening in the first channel layer and the charge storage layer on the bottom of the first channel hole and exposing the metal silicide layer.

15. The 3D NAND memory of claim 10 further comprising:

a second stacked structure in which sacrificial layers and isolation layers are alternately stacked on the first stacked structure, the second stacked structure having a second channel hole penetrating a thickness of the second stacked structure therein, the second channel hole communicating with the first channel hole; a charge storage layer is on sidewalls and a bottom of the first and second channel holes.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a 3D NAND memory and a forming method thereof.

Background

NAND flash memory is a better storage device than hard disk drives, and is widely used in electronic products as people seek nonvolatile storage products with low power consumption, light weight and good performance. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND memories with a 3D structure are proposed.

The formation process of existing 3D NAND memories generally includes: forming a stacked layer in which silicon nitride layers and silicon oxide layers are alternately stacked on a substrate; etching the stacked layer to form a channel hole in the stacked layer, etching the substrate at the bottom of the channel hole after the channel hole is formed, and forming a groove in the substrate; forming an Epitaxial silicon layer, also commonly referred to as SEG, in the recess at the bottom of the channel hole by Selective Epitaxial Growth (Selective Epitaxial Growth); forming a charge storage layer and a channel layer in the channel hole, the channel layer being connected to an epitaxial silicon layer (SEG); and removing the silicon nitride layer, and forming gate metal at the position where the silicon nitride layer is removed.

In the existing 3D NAND memory forming process, the characteristic size of a channel hole is easy to change, and the stability of the process is influenced.

Disclosure of Invention

The technical problem to be solved by the invention is how to keep the characteristic dimension of the channel hole stable in the process of forming the 3D NAND memory, thereby keeping the stability of the process.

The invention provides a method for forming a 3D NAND memory, which comprises the following steps:

providing a semiconductor substrate, wherein a first stacked structure formed by alternately stacking a sacrificial layer and an isolation layer is formed on the semiconductor substrate, a first channel hole penetrating through the thickness of the first stacked structure is formed in the first stacked structure, and a groove is formed in the semiconductor substrate at the bottom of the first channel hole;

forming a semiconductor epitaxial layer in the groove;

forming a metal silicide layer on the surface of the semiconductor epitaxial layer;

forming a charge storage layer on the sidewall and the bottom of the first channel hole;

etching the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing the surface of the semiconductor epitaxial layer;

and forming a second channel layer in the opening, wherein the second channel layer is in contact with the semiconductor epitaxial layer.

Optionally, the forming process of the metal silicide layer is as follows: forming metal layers on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing to enable the metal layer to react with the semiconductor epitaxial layer to form a metal silicide layer; removing the unreacted metal.

Optionally, the annealing atmosphere is an inert gas, and the annealing temperature is lower than 600 ℃.

Optionally, the etching selection ratio of the metal silicide layer to the charge storage layer and the semiconductor epitaxial layer is at least greater than 2: 1.

Optionally, the method further includes: forming a first channel layer on the charge storage layer; and etching the first channel layer, the charge storage layer and part of the metal silicide layer on the bottom of the first channel hole to form an opening exposing out of the surface of the semiconductor epitaxial layer.

Optionally, the specific step of forming the second channel layer in the opening includes:

removing the first channel layer;

a second channel layer is formed on the surface of the charge storage layer and the surfaces of the bottom and the side walls of the opening.

Optionally, the specific step of forming the second channel layer in the opening includes:

and reserving the first channel layer, and forming a second channel layer on the surface of the first channel layer and the surfaces of the bottom and the side wall of the opening.

Optionally, the method further includes:

filling a channel hole sacrificial layer in the first channel hole;

a second stacked structure in which sacrificial layers and isolation layers formed on the first stacked structure are alternately stacked;

a second channel hole penetrating through the thickness of the second stacked structure is formed in the second stacked structure and is communicated with the first channel hole;

removing the channel hole sacrificial layer;

and forming a charge storage layer on the side walls and the bottom of the first channel hole and the second channel hole.

Optionally, the sacrificial layer is replaced by a control gate.

In order to solve the above problems, the present invention also provides a 3D NAND memory comprising:

the semiconductor device comprises a semiconductor substrate, and a first stacked structure, wherein control gates and isolation layers are alternately stacked on the semiconductor substrate, a first channel hole penetrating through the thickness of the first stacked structure is formed in the first stacked structure, a groove is formed in the semiconductor substrate at the bottom of the first channel hole, and a semiconductor epitaxial layer is formed in the groove;

the metal silicide layer is positioned on the surface of the semiconductor epitaxial layer;

a charge storage layer on sidewalls and a bottom of the first channel hole;

a second channel layer on the charge storage layer, the second channel layer in contact with the semiconductor epitaxial layer.

Optionally, the etching selection ratio of the metal silicide layer to the charge storage layer and the semiconductor epitaxial layer is at least greater than 2: 1.

Optionally, the metal silicide layer is made of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide or titanium silicide.

Optionally, the charge storage layer includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.

Optionally, the method further includes:

a first channel layer on the charge storage layer;

and an opening in the first channel layer and the charge storage layer on the bottom of the first channel hole and exposing the metal silicide layer.

Optionally, the method further includes:

a second stacked structure in which sacrificial layers and isolation layers are alternately stacked on the first stacked structure, the second stacked structure having a second channel hole penetrating a thickness of the second stacked structure therein, the second channel hole communicating with the first channel hole; a charge storage layer is on sidewalls and a bottom of the first and second channel holes.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the forming method of the 3D NAND memory, the metal silicide layer is formed on the surface of the semiconductor epitaxial layer, and when the metal silicide layer is formed, the sacrificial layer on the side wall of the first channel hole is not oxidized, so that the characteristic dimension of the first channel hole is kept unchanged or changed slightly, and the stability of the process is guaranteed; moreover, the metal silicide layer is formed on the surface of the semiconductor epitaxial layer, and when the first channel layer and the charge storage layer on the bottom of the first channel hole are removed by etching to form an opening, the metal silicide layer can be used as an etching stop layer to well protect the surface of the semiconductor epitaxial layer, ensure the flatness of the surface of the semiconductor epitaxial layer and improve the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer when the semiconductor epitaxial layer is contacted with the second channel layer subsequently; and when the metal silicide layer is removed, the metal silicide layer has a high etching selection ratio relative to the first channel layer, the charge storage layer and the semiconductor epitaxial layer, so that the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at two sides of the opening are etched by a small amount, the stability of the characteristic dimension of the first channel hole is further ensured, and meanwhile, the etching amount of the metal silicide layer to the semiconductor epitaxial layer at the bottom is removed by a small amount, and the flatness of the semiconductor epitaxial layer is further ensured.

Further, the forming process of the metal silicide layer comprises the following steps: forming metal layers on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing to enable the metal layer to react with the semiconductor epitaxial layer to form a metal silicide layer; and removing unreacted metal, wherein in the process of forming the metal silicide layer, because the metal layer is directly contacted with the surface of the semiconductor epitaxial layer, the thickness of the formed metal silicide layer is not limited by the depth, the size and the side wall appearance of the first channel hole, so that the thickness of the formed metal silicide layer is kept uniform, the surface of the residual semiconductor epitaxial layer at the bottom of the metal silicide layer can be kept flat, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer when being contacted with the second channel layer subsequently is further improved.

According to the 3D NAND memory, the metal silicide layer is arranged on the surface of the semiconductor epitaxial layer of the 3D NAND memory, and the sacrificial layer on the side wall of the first channel hole cannot be oxidized when the metal silicide layer is formed, so that the characteristic dimension of the first channel hole is kept unchanged or is changed very little; and when the first channel layer and the charge storage layer on the bottom of the first channel hole are removed by etching to form an opening, the metal silicide layer can well protect the surface of the semiconductor epitaxial layer as an etching stop layer, so that the flatness of the surface of the semiconductor epitaxial layer is ensured, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer when the semiconductor epitaxial layer is subsequently contacted with the second channel layer is improved.

Drawings

FIGS. 1-16 are cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention.

Detailed Description

As mentioned in the background, in the conventional 3D NAND memory formation process, the feature size of the channel hole is easy to change, which affects the process stability.

It has been found that the prior art process of forming the charge storage layer and the channel layer generally includes: forming a charge storage layer on the side wall and the bottom of the channel hole; forming a first channel layer on the charge storage layer; etching to remove the first channel layer and the charge storage layer on the bottom of the channel hole, and forming a surface opening exposing the epitaxial silicon layer (SEG); and forming a second channel layer in the opening and on the surface of the first channel layer, wherein the second channel layer and the first channel layer form a channel layer. In order to prevent the surface of the epitaxial silicon layer (SEG) from being damaged when forming the opening, after the epitaxial silicon layer (SEG) is formed, a layer of silicon oxide is formed on the surface of the epitaxial silicon layer (SEG) as an etching stop layer when forming the opening by a thermal oxidation process, and the thermal oxidation process is performed while oxidizing the silicon nitride layer on the sidewall of the channel hole, so that the characteristic dimension of the channel hole is changed.

In addition, when the silicon oxide is formed on the surface of the epitaxial silicon layer (SEG) through the thermal oxidation process, due to the fact that the depth of the channel hole is deep, the size is small and the side wall morphology influences, the oxidizing gas is easily distributed on the surface of the epitaxial silicon layer (SEG) at the bottom of the channel hole unevenly, the surface of the epitaxial silicon layer (SEG) is oxidized unevenly or insufficiently, the thickness of the formed silicon oxide is uneven and the surface of the remaining epitaxial silicon layer (SEG) is uneven, when the silicon oxide is etched after the opening is formed to expose the surface of the epitaxial silicon layer (SEG), the surface of the exposed epitaxial silicon layer (SEG) is uneven, and when the second channel layer is formed on the surface of the uneven epitaxial silicon layer (SEG), the second channel layer and the surface of the epitaxial silicon layer (SEG) are easily in poor contact. Moreover, the etching selectivity of silicon oxide as an etching stop layer relative to the materials of the epitaxial silicon layer (SEG), the channel layer and the charge storage layer is relatively low, which is not favorable for controlling the characteristic size of the channel hole and the surface flatness of the epitaxial silicon layer (SEG).

To this end, the present invention provides a 3D NAND memory and a method of forming the same, wherein the method of forming, by forming a metal silicide layer on a surface of a semiconductor epitaxial layer, the sacrificial layer on the side wall of the first channel hole is not oxidized when the metal silicide layer is formed, thereby ensuring that the characteristic dimension of the first channel hole is kept unchanged or has small change, thereby ensuring the stability of the process, and when the first channel layer and the charge storage layer on the bottom of the first channel hole are etched and removed to form an opening, the metal silicide layer can well protect the surface of the semiconductor epitaxial layer as an etching stop layer, the flatness of the surface of the semiconductor epitaxial layer is guaranteed, and the performance of the semiconductor epitaxial layer at the bottom of the metal silicide layer when the semiconductor epitaxial layer is subsequently contacted with the second channel layer is improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

FIGS. 1-16 are cross-sectional views illustrating a process of forming a 3D NAND memory according to an embodiment of the present invention.

Referring to fig. 1 and 2, a semiconductor substrate 100 is provided, a first stacked structure 111 in which a sacrificial layer 103 and an isolation layer 104 are alternately stacked is formed on the semiconductor substrate 100, a first channel hole 105 penetrating through the thickness of the first stacked structure 111 is formed in the first stacked structure 111, a groove 106 is formed in the semiconductor substrate 100 at the bottom of the first channel hole 105, and a semiconductor epitaxial layer 107 is formed in the groove 106.

The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

The first stacked structure 111 comprises a plurality of sacrificial layers 103 and isolation layers 104 which are alternately stacked, the sacrificial layers 103 are subsequently removed to form a cavity, and then a control gate is formed at the position where the sacrificial layers 103 are removed. The isolation layer 104 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).

The sacrificial layer 103 and the isolation layer 104 are alternately stacked, that is: after forming a layer of sacrificial layer 103, a layer of isolation layer 104 is formed on the surface of sacrificial layer 103, and then the steps of forming sacrificial layer 103 and isolation layer 104 on sacrificial layer 103 are sequentially performed cyclically. In this embodiment, the bottom layer of the first stacked structure 111 is a sacrificial layer 103, and the top layer is an isolation layer 104.

The number of layers of the first stacked structure 111 (the number of layers of the dual-layer stacked structure including the sacrificial layer 103 and the isolation layer 104 in the first stacked structure 111) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the first stacked structure 111 may be 8, 32, 64, or the like, and the greater the number of layers of the first stacked structure 111, the greater the integration level can be. In the present embodiment, only the number of layers of the first stacked structure 111 is 4 as an example.

The sacrificial layer 103 and the isolation layer 104 are made of different materials, and when the sacrificial layer 103 is removed subsequently, the sacrificial layer 103 has a high etching selection ratio relative to the isolation layer 104, so that when the sacrificial layer 103 is removed, the etching amount of the isolation layer 104 is small or negligible, and the flatness of the isolation layer 104 is ensured.

The isolation layer 104 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 103 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 104 is made of silicon oxide, the sacrificial layer 103 is made of silicon nitride, and the isolation layer 104 and the sacrificial layer 103 are formed by a chemical vapor deposition process.

The first channel hole 105 is formed through an anisotropic dry etching process, the anisotropic dry etching process may be a plasma etching process, before the etching process is performed, a patterned mask layer is formed on the first stacked structure 111, the patterned mask layer has an opening exposing the surface of the first stacked structure 111, and when etching is performed, the first stacked structure 111 is etched by using the patterned mask layer as a mask, and the first channel hole 105 is formed in the first stacked structure 111.

In an embodiment, a buffer oxide layer 101 and a dielectric layer 102 located on the buffer oxide layer 101 are further formed between the first stacked structure 111 and the semiconductor substrate 100, and after the first channel hole 105 is formed, the buffer oxide layer 101 and the dielectric layer 102 at the bottom of the first channel hole 105 and a part of the semiconductor substrate 100 are continuously etched to form a groove 106; a semiconductor epitaxial layer 107 (refer to fig. 4) is formed in the groove 106 through a selective epitaxial process, a surface of the semiconductor epitaxial layer 107 is lower than a surface of the dielectric layer 102 and higher than a surface of the semiconductor substrate 100, the semiconductor epitaxial layer 107 is made of silicon, germanium or silicon germanium, and in this embodiment, the semiconductor epitaxial layer 107 is made of silicon.

In an embodiment, the dielectric layer 102 is a two-layer stacked structure including a silicon nitride layer on the buffer oxide layer 101 and a silicon oxide layer on the silicon nitride layer.

Referring to fig. 3, a metal silicide layer 137 is formed on the surface of the semiconductor epitaxial layer 107.

The metal silicide layer 137 is made of nickel silicide, tungsten silicide, cobalt silicide, tantalum silicide, or titanium silicide.

The metal layer is a nickel layer, a tungsten layer, a cobalt layer, a tantalum layer or a titanium layer. The annealing atmosphere is inert gas, the annealing comprises a first annealing and a second annealing, and the temperatures of the first annealing and the second annealing are both lower than 600 ℃.

In the present application, when the metal silicide layer 137 is formed, the sacrificial layer 103 on the sidewall of the first channel hole 105 is not oxidized, so that the feature size of the first channel hole 105 is kept unchanged or changed very little, thereby ensuring the stability of the process; moreover, by forming the metal silicide layer 137 on the surface of the semiconductor epitaxial layer 107, when the first channel layer and the charge storage layer on the bottom of the first channel hole 105 are etched and removed to form an opening, the metal silicide layer 137 can well protect the surface of the semiconductor epitaxial layer 137 as an etching stop layer, so that the flatness of the surface of the semiconductor epitaxial layer 137 is ensured, and the performance of the semiconductor epitaxial layer 107 at the bottom of the metal silicide layer 137 when being contacted with the second channel layer subsequently is improved; and, when removing the metal silicide layer 137, the metal silicide layer 137 has a high etching selectivity ratio with respect to the first channel layer, the charge storage layer and the semiconductor epitaxial layer 107, so that the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at both sides of the opening are etched by a small amount, thereby further ensuring the stability of the characteristic dimension of the channel hole, and simultaneously, the etching amount of the semiconductor epitaxial layer 137 at the bottom is small when removing the metal silicide layer 137, further ensuring the flatness of the semiconductor epitaxial layer 137.

In one embodiment, the forming process of the metal silicide layer 137 includes: forming a metal layer (not shown) on the surface of the semiconductor epitaxial layer 107, the sidewall surface of the first channel hole 105 and the surface of the first stacked structure 111; annealing is carried out, so that the metal layer reacts with the semiconductor epitaxial layer 107 to form a metal silicide layer 137; the unreacted metal is removed, and in the foregoing process, when the metal silicide layer 137 is formed, since the metal layer is in direct contact with the surface of the semiconductor epitaxial layer 107, the thickness of the formed metal silicide layer 137 is not limited by the depth, size, and sidewall morphology of the first channel hole 105, so that the thickness of the formed metal silicide layer 137 is kept uniform, thereby further keeping the surface of the semiconductor epitaxial layer 107 remaining at the bottom of the metal silicide layer 137 flat, and further improving the performance of the semiconductor epitaxial layer 107 at the bottom of the metal silicide layer 137 when being in subsequent contact with the second channel layer.

Referring to fig. 4, the first channel hole 105 (refer to fig. 3) is filled with a channel hole sacrificial layer 108.

The first stacked structure 111 has a flat surface by forming the channel hole sacrificial layer 108, so that a second stacked structure can be formed on the first stacked structure 111 in a subsequent step.

In one embodiment, the channel hole sacrificial layer 108 is formed by: forming a sacrificial material layer in the first channel hole 105 and on the surface of the first stacked structure 111, wherein the sacrificial material layer fills the first channel hole 105; the sacrificial material layer on the surface of the first stacked structure 111 and the channel hole sacrificial layer 108 in the first channel hole 105 are removed by planarization, which may be a chemical mechanical polishing process.

The material of the channel hole sacrificial layer 108 may be polysilicon, amorphous silicon, or amorphous carbon. In this embodiment, the channel hole sacrificial layer 108 is made of polysilicon.

In other embodiments, after the metal silicide layer 137 is formed, the charge storage layer is formed directly on the sidewalls and bottom of the first channel hole without forming the channel hole sacrificial layer 108 and the second stack structure; forming a first channel layer on the charge storage layer; etching the first channel layer and the charge storage layer on the bottom of the first channel hole until reaching the metal silicide layer to form an opening exposing the metal silicide layer; and removing part or all of the metal silicide layer to expose the surface of the semiconductor epitaxial layer from the opening.

Referring to fig. 5, a second stacked structure 112 in which sacrificial layers 109 and isolation layers 110 formed on the first stacked structure 101 are alternately stacked; a second channel hole 115 is formed in the second stack structure 112 through the thickness of the second stack structure 112, and the second channel hole 115 communicates with the first channel hole 105.

The sacrificial layer 109 is subsequently removed to form a cavity, and then a control gate is formed where the sacrificial layer 109 is removed. The isolation layer 110 serves as electrical isolation between different layers of the control gate, and between the control gate and other devices (conductive contacts, trench holes, etc.).

The sacrificial layer 109 and the isolation layer 110 are alternately stacked, that is: after forming a sacrificial layer 109, an isolation layer 110 is formed on the surface of the sacrificial layer 109, and then the steps of forming the sacrificial layer 109 and the isolation layer 110 on the sacrificial layer 109 are sequentially performed cyclically. In this embodiment, the bottom layer of the second stacked structure 112 is a sacrificial layer 109, and the top layer is an isolation layer 110.

The number of layers of the second stacked structure 112 (the number of layers of the dual-layer stacked structure of the sacrificial layer 109 and the isolation layer 110 in the second stacked structure 112) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the second stacked structure 112 may be 8, 32, 64, and the like, and the greater the number of layers of the second stacked structure 112, the higher the integration level is. In the present embodiment, only the number of layers of the second stacked structure 112 is 4 as an example.

The sacrificial layer 109 and the isolation layer 110 are made of different materials, and when the sacrificial layer 109 is removed subsequently, the sacrificial layer 109 has a high etching selectivity relative to the isolation layer 110, so that when the sacrificial layer 109 is removed, the etching amount of the isolation layer 110 is small or negligible, and the flatness of the isolation layer 110 is ensured.

The isolation layer 110 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 109 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 110 is made of silicon oxide, the sacrificial layer 109 is made of silicon nitride, and the isolation layer 110 and the sacrificial layer 109 are formed by a chemical vapor deposition process.

In this embodiment, an anisotropic dry etching process is used to etch the second stack structure 112 to form the second channel hole 115, and in a specific embodiment, the anisotropic dry etching process is a plasma etching process.

In one embodiment, when the second channel hole 115 is formed by etching, a portion of the via hole sacrificial layer 108 may be removed by over-etching.

In an embodiment, before the second stacked structure 112 is etched, a buffer oxide layer 113 and a dielectric layer 114 on the buffer oxide layer 113 are formed on the second stacked structure 112, and before the second stacked structure 112 is etched, an opening corresponding to the second channel hole 115 is formed in the dielectric layer 114 and the buffer oxide layer 113.

In one embodiment, the dielectric layer 114 may be a two-layer stacked structure including a silicon nitride layer on the buffer oxide layer 113 and a silicon oxide layer on the surface of the silicon nitride layer.

In the present embodiment, only one first stack structure and one second stack structure are taken as an example for explanation, and in other embodiments, the first stack structure and the second stack structure may be plural, and plural first stack structures and plural second stack structures are alternately stacked.

Referring to fig. 5 and 6 in combination, the channel hole sacrificial layer 108 is removed.

And removing the channel hole sacrificial layer 108 by wet etching. In this embodiment, TMAH (tetramethylammonium hydroxide) solution is used to remove the channel hole sacrificial layer 108.

Referring to fig. 7 and 8, a charge storage layer 116 is formed on sidewalls and bottoms of the first and second channel holes 105 and 115.

The charge storage layer 116 is used to store charge. The sacrificial material layer 108 is removed prior to forming the charge storage layer 116. In one embodiment, the sacrificial material layer 108 is removed by a wet etching process.

Referring to fig. 8, fig. 8 is an enlarged schematic structural view of the charge storage layer 116 formed in fig. 7, where the charge storage layer 116 includes a blocking oxide layer 116a, a charge trapping layer 116b on the blocking oxide layer 116a, and a tunneling oxide layer 116c on the charge trapping layer 116 b.

The material of the blocking oxide layer 116a and the tunneling oxide layer 116c is silicon oxide, and the material of the charge trapping layer 116b is silicon nitride. The charge trapping layer 116b, the tunnel oxide layer 116c and the blocking oxide layer 116a are formed by a chemical vapor deposition process.

Referring to fig. 9, a first channel layer 117 is formed on the charge storage layer 116.

The first channel layer 117 may be a part of a channel layer, and the first channel layer 117 may also protect the charge storage layer 116 from being etched when the charge storage layer 116 and the metal silicide layer 137 at the bottom of the first channel hole 105 are subsequently etched.

In this embodiment, the material of the first channel layer 117 is polysilicon.

Referring to fig. 10, the first channel layer 117 and the charge storage layer 116 on the first channel hole bottom 105 are etched, with the metal silicide layer 137 as a stop layer, to form an opening 125 exposing the metal silicide layer 137.

An anisotropic dry etching process is used for etching the first channel layer 117 and the charge storage layer 116 on the first channel hole bottom 105. In one embodiment, the anisotropic dry etching process is a plasma etching process, and the gas used in the plasma etching process includes a fluorocarbon-containing gas.

When the first channel layer 117 and the charge storage layer 116 on the bottom 105 of the first channel hole are etched, the amount of the metal silicide layer 137 which is removed by etching is small, the etching stop process can be well controlled, and the metal silicide layer 137 which is used as the etching stop layer can well protect the surface of the semiconductor epitaxial layer 137, so that the surface of the semiconductor epitaxial layer 137 is not over-etched.

Referring to fig. 11, the metal silicide layer 137 is removed, so that the opening 125 exposes the surface of the semiconductor epitaxial layer 107.

And removing the metal silicide layer 137 by dry etching or wet etching.

In this embodiment, the metal silicide layer 137 is removed by dry etching, and in an embodiment, the dry etching is anisotropic plasma etching. When the metal silicide layer 137 is removed, the metal silicide layer 137 has a high etching selection ratio (at least greater than 2:1) relative to the first channel layer 117, the charge storage layer and the semiconductor epitaxial layer 107, so that the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at two sides of the opening are etched by a small amount, thereby further ensuring the stability of the characteristic dimension of the channel hole, and meanwhile, the flatness of the semiconductor epitaxial layer 137 is further ensured when the metal silicide layer 137 is removed by a small amount and the semiconductor epitaxial layer 137 at the bottom is etched.

When the metal silicide layer 137 is removed by anisotropic plasma etching, a portion of the metal silicide layer 137 under the charge storage layer 116 is remained.

It should be noted that, when the first channel layer 117 and the charge storage layer 116 at the bottom of the first channel hole 105 are removed by etching, the first channel layer 117 and the charge storage layer 116 on the surface of the dielectric layer 114 may be removed at the same time.

In another embodiment, referring to fig. 12, the metal silicide layer 137 is removed by wet etching.

When the metal silicide layer 137 is removed, the metal silicide layer 137 has a high etching selection ratio (at least greater than 2:1) relative to the first channel layer, the charge storage layer and the semiconductor epitaxial layer 107, so that the first channel layer and the charge storage layer in the channel hole and the first channel layer and the charge storage layer exposed at two sides of the opening are etched by a small amount, the stability of the characteristic dimension of the channel hole is further ensured, and meanwhile, the etching amount of the metal silicide layer 137 on the semiconductor epitaxial layer 137 at the bottom is small when the metal silicide layer 137 is removed, and the flatness of the semiconductor epitaxial layer 137 is further ensured.

When wet etching is used, the metal silicide layer 137 is completely removed.

Referring to fig. 13, fig. 13 is performed on the basis of fig. 11, and a second channel layer 120 is formed on the bottom and sidewall surfaces of the first channel layer 117 and the opening 125.

The second channel layer 120 is made of polysilicon, and the formation process is chemical vapor deposition. The second channel layer 120 and the first channel layer 117 together constitute a first channel layer of the NAND memory.

In another embodiment, the first channel layer 117 is removed before the second channel layer 120 is formed.

In another embodiment, referring to fig. 14, fig. 14 is performed on the basis of fig. 12, the first channel layer 117 (refer to fig. 12) is removed, and the second channel layer 120 is formed on the surface of the charge storage layer 116 and the bottom and sidewall surfaces of the opening 125.

Referring to fig. 15 or 16, fig. 15 is performed on the basis of fig. 13, and fig. 16 is performed on the basis of fig. 14, and a filling layer 121 is formed on the channel layer 120, the filling layer 121 filling the first channel hole and the second channel hole.

The material of the filling layer 121 is silicon oxide or other suitable materials.

Referring to fig. 15 or 16, after forming the channel layer 120 or forming the filling layer 121, the sacrificial layer 103 and the sacrificial layer 109 in the first stack structure 111 and the second stack structure 112 are removed (refer to fig. 13 or 14); control gate 123 and control gate 129 are formed at positions where sacrificial layer 103 and sacrificial layer 109 are removed.

Wet etching may be used to remove the sacrificial layer 103 and the sacrificial layer 109.

The material of control gate 123 and control gate 129 may be metal or other conductive material (e.g., polysilicon, etc.). In this embodiment, the conductive material is a metal, and the metal is one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

In an embodiment, a high-K dielectric layer is further formed between the control gate 123 and the control gate 129 and the corresponding isolation layer 104 and isolation layer 110, and the material HfO of the high-K dielectric layer₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃Or BaSrTiO.

In an embodiment, when the sacrificial layer 103 and the sacrificial layer 109 are removed, the silicon nitride layer in the dielectric layer 102 is simultaneously removed, and the selection gate 132 is correspondingly formed at the position where the silicon nitride layer is removed, and the formation process of the selection gate 132 is the same as the formation steps of the control gate 123 and the control gate 129.

Another embodiment of the present invention further provides a 3D NAND memory, referring to fig. 10, including:

a semiconductor substrate 100, a first stacked structure 111 on the semiconductor substrate 100, wherein the first stacked structure 111 is formed by alternately stacking a sacrificial layer 103 and an isolation layer 104, the first stacked structure 111 has a first channel hole 105 penetrating through the thickness of the first stacked structure 111, the semiconductor substrate 100 at the bottom of the first channel hole 105 has a groove therein, and a semiconductor epitaxial layer 107 is formed in the groove;

a metal silicide layer 137 on the surface of the semiconductor epitaxial layer 107;

a charge storage layer 116 on sidewalls and a bottom of the first channel hole 105;

the charge storage layer 116 at the bottom of the first channel hole 105 exposes the opening 125 of the metal silicide 137.

In one embodiment, the charge storage layer 116 further has a first channel layer 117, and the opening 125 is located in the first channel layer 117 and the charge storage layer 116 on the bottom of the first channel hole 105, exposing the metal silicide layer 137.

The metal silicide layer is formed by the following process: forming metal layers on the surface of the semiconductor epitaxial layer, the surface of the side wall of the first channel hole and the surface of the first stacking structure; annealing to enable the metal layer to react with the semiconductor epitaxial layer to form a metal silicide layer; removing the unreacted metal.

The metal silicide layer 137 has a high etch selectivity with respect to the first channel layer 117, the charge storage layer 116, and the semiconductor epitaxial layer 107.

The charge storage layer 116 includes a blocking oxide layer, a charge trapping layer on the blocking oxide layer, and a tunneling oxide layer on the charge trapping layer.

In one embodiment, the method further comprises:

a second stacked structure 112 on the first stacked structure 111, wherein the sacrificial layer 109 and the isolation layer 110 are alternately stacked, the second stacked structure 112 has a second channel hole 115 penetrating through a thickness of the second stacked structure, and the second channel hole 115 is communicated with the first channel hole 105; a charge storage layer 116 is positioned on sidewalls and a bottom of the first and second channel holes 105 and 115.

The definition or description of the same or similar structure in this embodiment as that in the foregoing embodiment is omitted, and for details, refer to the definition or description of the corresponding parts in the foregoing embodiment.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.