阅读说明：本技术 一种高速adc并串转换电路 (High-speed ADC parallel-serial conversion circuit ) 是由 王媛 李冬 胡孔阳 莫啸 章钰 刘先博 于 2020-12-31 设计创作，主要内容包括：本发明提出一种高速ADC并串转换电路,包括时钟复位管理单元、n个时序控制单元和数据选择输出单元,时钟复位管理单元为每个时序控制单元提供时钟信号和复位信号,每个时序控制单元用于各自通道内i路数据和q路数据的采样、校正和交织输出,数据选择输出单元用于按各通道数据的输出时序交织输出各通道的采样数据。本发明可以实现多路并行m位数据到单路m位数据的并串转换,完成低采样数据率到高采样数据率的转换,相比于现有并串转换电路的实现方式,有效降低电路面积和功耗。(The invention provides a high-speed ADC parallel-serial conversion circuit, which comprises a clock reset management unit, n time sequence control units and a data selection output unit, wherein the clock reset management unit provides a clock signal and a reset signal for each time sequence control unit, each time sequence control unit is used for sampling, correcting and interweaving output of i-path data and q-path data in each channel, and the data selection output unit is used for interweaving and outputting sampling data of each channel according to the output time sequence of the data of each channel. The parallel-serial conversion circuit can realize the parallel-serial conversion from multi-path parallel m-bit data to single-path m-bit data, and complete the conversion from low sampling data rate to high sampling data rate.)

1. A high-speed ADC parallel-serial conversion circuit is characterized by comprising a clock reset management unit, n time sequence control units and a data selection output unit, wherein the clock reset management unit provides a clock signal and a reset signal for each time sequence control unit;

the clock reset management unit provides a channel working clock, an i-path working clock and a q-path working clock for each time sequence control unit, the i-path m-bit data of the time sequence control unit is sampled and corrected in an i-path working clock domain, the q-path m-bit data is sampled and corrected in a q-path working clock domain, single-channel parallel-serial conversion is counted by a single-bit counter, sampling is carried out by the channel working clock, and sampling data of a corresponding channel is output in an interlaced mode;

the channel working clocks of each time sequence control unit have a difference of 360 DEG/n, the i-path working clock is generated by frequency division of the channel working clock 2, and the q-path working clock is generated by frequency division and phase inversion of the channel working clock 2.

2. The high-speed ADC parallel-serial conversion circuit of claim 1, wherein the timing control unit comprises a working mode control module and a correction output module, the working mode control module is used for switching the working modes of the ADC, and the correction output module corrects m-bit data input by the i-path and the q-path according to the weight and alternately outputs the corrected m-bit data of the i-path and the q-path according to the clock phase relationship.

3. The high-speed ADC parallel-serial conversion circuit of claim 1, wherein the data selection output unit outputs a slave clock while interleaving the sampled data of each channel.

4. The high-speed ADC parallel-to-serial conversion circuit of claim 1, wherein the clock reset management unit turns off the clock when the ADC is in a sleep and low power consumption state when the ADC is in a working state.

Technical Field

The invention relates to the technical field of parallel-serial conversion circuits, in particular to a high-speed ADC parallel-serial conversion circuit based on a synchronous sequential logic circuit.

Background

The rapid development of computer technology, communication technology and microelectronic technology has greatly promoted the development of ADC technology. The ADC is a key component of an analog-to-digital interface, is widely applied to various fields, and plays an important role in information technology. Like computers, ADCs undergo a progression from low speed to high speed. The low-speed (conversion time is more than 300us) structure of the ADC is an integral type, a slope type and a tracking type; the ADC medium-speed (the conversion time is 1-300us) structure has a successive approximation type; the high-speed (switching time less than 1us) architecture of adc is of the blinking type, of the zoned type and of the sigma-delta type of the high-resolution architecture. ADCs of different structures meet the requirements of universality and diversity in practical applications, wherein high-speed ADCs have become an important link in determining the performance of modern electronic devices (such as radars, communications, electronic countermeasure, aerospace, missiles, measurement and control, ground exhibition, medical treatment, instruments and meters, images, high-performance controllers, digital communication systems, and the like).

Due to the limited sampling data rate of the single-core ADC, a time alternative sampling technology, also called a parallel multi-channel sampling technology, is developed, and is the best way for realizing a data acquisition system with high-frequency sampling at present. In order to facilitate the subsequent processing of the collected data, the data input in parallel needs to be converted into serial output data, i.e. parallel-serial conversion. In an implementation manner of an existing parallel-to-serial conversion circuit, when n paths of parallel data are input, n triggers and n switches are required to be consumed, and when an ADC is m bits, n × m triggers and n × m switches are required to be consumed, so that the defects of large occupied area and high manufacturing cost exist.

Disclosure of Invention

Aiming at the defects of the implementation mode of the existing parallel-serial conversion circuit, the invention provides a high-speed ADC parallel-serial conversion circuit based on a synchronous sequential logic circuit.

A high-speed ADC parallel-serial conversion circuit comprises a clock reset management unit, n time sequence control units and a data selection output unit, wherein the clock reset management unit provides a clock signal and a reset signal for each time sequence control unit;

the clock reset management unit provides a channel working clock, an i-path working clock and a q-path working clock for each time sequence control unit, the i-path m-bit data of the time sequence control unit is sampled and corrected in an i-path working clock domain, the q-path m-bit data is sampled and corrected in a q-path working clock domain, single-channel parallel-serial conversion is counted by a single-bit counter, sampling is carried out by the channel working clock, and sampling data of a corresponding channel is output in an interlaced mode;

the channel working clocks of each time sequence control unit have a difference of 360 DEG/n, the i-path working clock is generated by frequency division of the channel working clock 2, and the q-path working clock is generated by frequency division and phase inversion of the channel working clock 2.

Further, the time sequence control unit comprises a working mode control module and a correction output module, wherein the working mode control module is used for switching the working mode of the ADC, and the correction output module corrects m-bit data input by the i path and the q path according to the weight and alternately outputs the corrected m-bit data of the i path and the q path according to the clock phase relation.

Further, the data selection output unit outputs the channel associated clock while interleaving the sampling data of each channel.

Furthermore, when the ADC is in a working state, the clock reset management unit turns off the clock when the ADC is in a sleep and low power consumption state.

The high-speed ADC parallel-serial conversion circuit based on the synchronous sequential logic circuit can realize parallel-serial conversion from multi-path parallel m-bit data to single-path m-bit data, and complete conversion from a low sampling data rate to a high sampling data rate; meanwhile, clock signals can be generated or turned off according to the working state of the ADC, and the power consumption of the circuit is reduced.

Drawings

FIG. 1 is a schematic diagram of a high-speed ADC parallel-to-serial conversion circuit;

FIG. 2 is a clock reset management unit CRMU clock block diagram;

FIG. 3 is a diagram of CRMU clock phase relationship;

FIG. 4 is a timing diagram of single channel output data;

fig. 5 is a timing diagram of data output of the data selection output unit MUX.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The embodiments of the present invention have been presented for purposes of illustration and description, and are not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.

Example 1

A high-speed ADC parallel-serial conversion circuit includes a clock reset management unit, n timing control units, and a data selection output unit, where n is 4 in this embodiment, and the specific structure refers to fig. 1.

The clock reset management unit CRMU provides a clock signal and a reset signal for each timing control unit, and its clock diagram is shown in fig. 2, and the main clock Clk generates the channel working clocks Clk _ dig _ master _ ch1, Clk _ dig _ master _ ch2, Clk _ dig _ master _ ch3, and Clk _ dig _ master _ ch4 corresponding to the four timing control units through 4 frequency division and phase shift. The four channel working clocks generate clk _ dig _ sar _ i _ ch1, clk _ dig _ sar _ i _ ch2, clk _ dig _ sar _ i _ ch3 and clk _ dig _ sar _ i _ ch4 through frequency division by 2 respectively; the divided-by-2 and inverted signals clk _ dig _ sar _ q _ ch1, clk _ dig _ sar _ q _ ch2, clk _ dig _ sar _ q _ ch3, and clk _ dig _ sar _ q _ ch 4.

The channel working clocks of each time sequence control unit have a difference of 360 DEG/n, the i-path working clock is generated by frequency division of the channel working clock 2, and the q-path working clock is generated by frequency division and phase inversion of the channel working clock 2. The phase relationship of the CRMU clock is shown in figure 3. The phases of the working clocks of the four channels after frequency division and phase shift of the master clock Clk are sequentially different by 90 degrees, and the phases of the corresponding i-path working clock and q-path working clock after frequency division of the working clocks of the four channels are different by 180 degrees.

The time sequence control unit comprises a working mode control module and a correction output module. The working mode control module is used for switching the working mode of the ADC. The correction output module corrects m-bit data input by the i-path and the q-path according to the weight, and alternately outputs the m-bit data of the i-path and the m-bit data of the q-path after correction according to the clock phase relationship, specifically, the clock reset management unit provides a channel working clock clk _ dig _ master, an i-path working clock clk _ dig _ sar _ i and a q-path working clock clk _ dig _ sar _ q for each time sequence control unit. The time sequence control unit samples and corrects i paths of m-bit data in an i path of working clock domain, samples and corrects q paths of m-bit data in a q path of working clock domain, counts the data through a single-channel parallel-serial conversion by a single-bit counter, samples the data through a channel working clock clk _ dig _ master, and outputs sampling data of a corresponding channel in an interleaving manner, and the reference is made to fig. 4.

The data selection output unit is used for interweaving and outputting sampling data of each channel according to the output time sequence of data of each channel, specifically, the data selection output unit works in a clock domain of a master clock Clk, counts through a 2-bit counter, and interweaves and outputs sampling data of 4 channels, and referring to fig. 5, conversion from 8 paths of parallel m-bit data to 1 path of m-bit data is completed.

The data selection output unit outputs the channel associated clock clkout while interleaving the sampling data of each channel, which is convenient for the subsequent clock domain crossing processing.

In order to reduce power consumption, the clock reset management unit turns off the clock when the ADC is in a working state and when the ADC is in a sleep and low power consumption state.

It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by one of ordinary skill in the art and related arts based on the embodiments of the present invention without any creative effort, shall fall within the protection scope of the present invention.