阅读说明：本技术 一种具有抗辐照功能的8b/10b编解码电路 (8B/10B coding and decoding circuit with anti-radiation function ) 是由 陈飞翔 谢小东 王佳辉 于 2021-01-11 设计创作，主要内容包括：本发明提出了一种具有抗辐照功能的8B/10B编解码电路,包括抗辐照输入D触发器组、抗辐照输出D触发器组、抗辐照8B/10B编码组合逻辑电路以及抗辐照8B/10B解码组合逻辑电路,所述抗辐照输入D触发器组分别与所述抗辐照编码组合逻辑电路、所述抗辐照解码组合逻辑电路的输入端相连,所述抗辐照编码组合逻辑电路、所述抗辐照解码组合逻辑电路的输出端与所述抗辐照输出D触发器组的输入端相连。本发明具有成本低、抗辐照性能好以及灵活性高等优点。(The invention provides an 8B/10B coding and decoding circuit with an anti-irradiation function, which comprises an anti-irradiation input D trigger group, an anti-irradiation output D trigger group, an anti-irradiation 8B/10B coding combination logic circuit and an anti-irradiation 8B/10B decoding combination logic circuit, wherein the anti-irradiation input D trigger group is respectively connected with the input ends of the anti-irradiation coding combination logic circuit and the anti-irradiation decoding combination logic circuit, and the output ends of the anti-irradiation coding combination logic circuit and the anti-irradiation decoding combination logic circuit are connected with the input end of the anti-irradiation output D trigger group. The invention has the advantages of low cost, good radiation resistance, high flexibility and the like.)

1. An 8B/10B coding and decoding circuit with an anti-radiation function is characterized in that: the anti-radiation decoding circuit comprises an anti-radiation input D trigger group, an anti-radiation output D trigger group, an anti-radiation 8B/10B coding combination logic circuit and an anti-radiation 8B/10B decoding combination logic circuit, wherein the anti-radiation input D trigger group is respectively connected with the input ends of the anti-radiation coding combination logic circuit and the anti-radiation decoding combination logic circuit, and the output ends of the anti-radiation coding combination logic circuit and the anti-radiation decoding combination logic circuit are connected with the input end of the anti-radiation output D trigger group.

2. The 8B/10B codec circuit with radiation protection function according to claim 1, wherein: the anti-irradiation input D trigger group respectively samples and stores data to be coded and decoded, and respectively sends the data to be coded and decoded to the anti-irradiation coding combination logic circuit and the anti-irradiation decoding combination logic circuit, and after the coding and decoding are completed, the anti-irradiation output D trigger group samples and stores the coded and decoded data.

3. The 8B/10B codec circuit with radiation protection function according to claim 1, wherein: the anti-irradiation 8B/10B decoding circuit is formed by a group of anti-irradiation input D trigger groups, the anti-irradiation 8B/10B coding combination logic circuit and a group of anti-irradiation output D trigger groups; and the other group of the anti-irradiation input D trigger group, the anti-irradiation 8B/10B decoding combination logic circuit and the other group of the anti-irradiation output D trigger group form an anti-irradiation 8B/10B decoding circuit.

4. The 8B/10B codec circuit with radiation protection function according to claim 1, wherein: the anti-radiation input D trigger group and the anti-radiation output D trigger group are based on a DICE storage structure.

5. The 8B/10B codec circuit with radiation protection function according to claim 1, wherein: the anti-irradiation 8B/10B coding combinational logic circuit and the anti-irradiation 8B/10B decoding combinational logic circuit are composed of a plurality of basic anti-irradiation combinational logic units, such as an anti-irradiation inverter unit, an anti-irradiation two-input NAND gate, an anti-irradiation two-input NOR gate and the like.

6. The 8B/10B codec circuit with radiation protection function of claim 5, wherein: the basic anti-radiation combinational logic unit comprises six parts, namely a standard pull-up network, a standard pull-down network, a reinforced pull-up network, a reinforced pull-down network, a high-level error correction circuit and a low-level error correction circuit.

7. The 8B/10B codec circuit with radiation protection function of claim 6, wherein: the standard up/down-pull network is used as a front-stage circuit, the reinforced up/down-pull network and the error correction circuit form a rear-stage circuit, the high-level error correction circuit and the reinforced up-pull network form an up-pull network of the rear-stage circuit, and the low-level error correction circuit and the reinforced down-pull network form a down-pull network of the rear-stage circuit.

8. The 8B/10B codec with radiation protection function of claim 6, wherein: the standard network is connected with the input of the reinforcing network to form a logic input, the preceding stage circuit is connected with the output of the following stage circuit to form a logic output, and the logic output is positioned between the pull-up high-level error correction circuit and the pull-down low-level error correction circuit.

9. The 8B/10B codec circuit with radiation protection function of claim 6, wherein: the high-level error correction circuit is a PMOS tube which is normally open, and the low-level error correction circuit is an NMOS tube which is normally open.

Technical Field

The invention relates to the technical field of 8B/10B coding and decoding, in particular to an 8B/10B coding and decoding circuit with an anti-irradiation function.

Background

Currently, the mainstream high-speed serial bus communication standard generally adopts 8B/10B type coding for data transmission, such as USB3.0, SATA, PCI Express, Infini-band, Fibre Channel and SerDes. In wireless communication systems, 8B/10B coding is widely used for the interface between the base station radio frequency and the baseband (IR interface). With the development of military industry and aerospace industry in China, a great deal of demand is placed on an anti-irradiation circuit. However, most of the foreign radiation-resistant circuits are supplied by the whole chip, and a radiation-resistant module with a certain foundation is not provided; the domestic supply of a single radiation-resistant 8B/10B codec circuit is also close to the blank. Therefore, the 8B/10B coding and decoding circuit is used as a basic module of a mainstream high-speed serial bus communication interface, and an 8B/10B coding and decoding circuit with an anti-radiation function is urgently needed to be developed.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the lack of a single anti-irradiation 8B/10B coding and decoding circuit module at home and abroad, the invention provides the 8B/10B coding and decoding circuit with low cost, good anti-irradiation performance and high flexibility.

In order to solve the technical problems, the technical scheme adopted by the invention is as follows: an 8B/10B coding and decoding circuit with an anti-radiation function comprises an anti-radiation input D trigger group, an anti-radiation output D trigger group, an anti-radiation 8B/10B coding combination logic circuit and an anti-radiation 8B/10B decoding combination logic circuit, wherein the anti-radiation input D trigger group is respectively connected with the input ends of the anti-radiation coding combination logic circuit and the anti-radiation decoding combination logic circuit, and the output ends of the anti-radiation coding combination logic circuit and the anti-radiation decoding combination logic circuit are connected with the input end of the anti-radiation output D trigger group.

As a further improvement of the invention: the anti-irradiation input D trigger group respectively samples and stores data to be coded and decoded and respectively sends the data to the anti-irradiation coding combination logic circuit and the anti-irradiation decoding combination logic circuit, and after the coding and decoding are completed, the anti-irradiation output D trigger group samples and stores the coded and decoded data.

As a further improvement of the invention: the anti-irradiation 8B/10B decoding circuit is formed by a group of anti-irradiation input D trigger groups, the anti-irradiation 8B/10B coding combination logic circuit and a group of anti-irradiation output D trigger groups; and the other group of the anti-irradiation input D trigger group, the anti-irradiation 8B/10B decoding combination logic circuit and the other group of the anti-irradiation output D trigger group form an anti-irradiation 8B/10B decoding circuit.

As a further improvement of the invention: the anti-radiation input D trigger group and the anti-radiation output D trigger group are based on a DICE storage structure.

As a further improvement of the invention: the anti-irradiation 8B/10B coding combinational logic circuit and the anti-irradiation 8B/10B decoding combinational logic circuit are composed of a plurality of basic anti-irradiation combinational logic units, such as an anti-irradiation inverter unit, an anti-irradiation two-input NAND gate, an anti-irradiation two-input NOR gate and the like.

As a further improvement of the invention: the basic anti-radiation combinational logic unit comprises six parts, namely a standard pull-up network, a standard pull-down network, a reinforced pull-up network, a reinforced pull-down network, a high-level error correction circuit and a low-level error correction circuit.

As a further improvement of the invention: the standard up/down-pull network is used as a front-stage circuit, the reinforced up/down-pull network and the error correction circuit form a rear-stage circuit, the high-level error correction circuit and the reinforced up-pull network form an up-pull network of the rear-stage circuit, and the low-level error correction circuit and the reinforced down-pull network form a down-pull network of the rear-stage circuit.

As a further improvement of the invention: the standard network is connected with the input of the reinforcing network to form a logic input, the preceding stage circuit is connected with the output of the following stage circuit to form a logic output, and the logic output is positioned between the pull-up high-level error correction circuit and the pull-down low-level error correction circuit.

As a further improvement of the invention: the high-level error correction circuit is a PMOS tube which is normally open, and the low-level error correction circuit is an NMOS tube which is normally open.

The invention has the advantages that: based on the 0.13 mu m technology, the invention designs a single anti-radiation 8B/10B coding and decoding circuit on the basis of an anti-radiation basic unit, on one hand, the invention is compatible with a common commercial process line and has the characteristics of better performance and lower price than a special anti-radiation process line; on the other hand, the method has the performance characteristic of radiation resistance while accurately realizing the 8B/10B coding and decoding functions.

Drawings

FIG. 1 is a schematic diagram of the structure principle of an 8B/10B codec circuit with an anti-radiation function according to this embodiment.

FIG. 2 is a schematic circuit diagram of an embodiment of an 8B/10B codec circuit with an anti-radiation function according to the present invention.

Fig. 3 is a schematic circuit diagram of an irradiation-resistant D flip-flop employed in an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of an irradiation-resistant combinational logic circuit unit adopted in a specific application example of the invention.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

As shown in fig. 1, the 8B/10B codec circuit with radiation-resistant function of the present embodiment includes two radiation-resistant input D flip-flop groups and two radiation-resistant output D flip-flop groups, the output end of the anti-irradiation coding combination logic circuit is connected with the input end of one anti-irradiation output D trigger group, the output end of the anti-irradiation decoding combination logic circuit is connected with the input end of the other anti-irradiation output D trigger group, and the output end of the anti-irradiation decoding combination logic circuit is connected with the input end of the other anti-irradiation output D trigger group to register and output the coded and decoded data.

In the embodiment, the 8B/10B coding and decoding circuit is formed by the anti-irradiation input D trigger group, the anti-irradiation output D trigger group, the anti-irradiation 8B/10B coding and combining logic circuit and the anti-irradiation 8B/10B decoding and combining logic circuit. The anti-irradiation input D trigger group samples input data, and the D trigger group carries out anti-irradiation reinforcement, so that the single event effect caused by irradiation during sampling is effectively inhibited. The sampled data is output to the anti-irradiation 8B/10B coding and decoding circuit, the anti-irradiation 8B/10B coding and decoding circuit can code and decode the input data, the 8B/10B coding and decoding circuit carries out anti-irradiation reinforcement, and the single event effect caused by irradiation during coding and decoding is effectively inhibited. The coded and decoded data is input into the D trigger group for anti-irradiation, and the input data is sampled, so that the single event effect caused by irradiation during sampling is effectively inhibited due to the anti-irradiation reinforcement of the D trigger group.

As shown in fig. 2, in the embodiment of the present invention, the radiation-resistant input D flip-flop group connected to the radiation-resistant 8B/10B encoding circuit includes 8 radiation-resistant D flip-flops, and the 8 radiation-resistant D flip-flops transmit the sampled 8-bit data to be encoded to the radiation-resistant 8B/10B encoding circuit for encoding. The anti-radiation input D trigger group connected with the anti-radiation 8B/10B decoding circuit comprises 10 anti-radiation D triggers, and the 10 anti-radiation D triggers transmit the sampled 10-bit data to be decoded to the anti-radiation 8B/10B decoding circuit for decoding. And the anti-radiation output D trigger group connected with the anti-radiation 8B/10B coding circuit comprises 10 anti-radiation D triggers and is used for registering and outputting coded 10-bit data. And the anti-radiation output D trigger group connected with the anti-radiation 8B/10B decoding circuit comprises 8 anti-radiation D triggers and is used for registering and outputting decoded 8-bit data.

As shown in fig. 3, the radiation-resistant D flip-flop in the embodiment of the present invention is based on dual DICE structures, and each DICE structure employs four-point redundant latch. The first stage is a DICE based master latch and the second stage is a DICE based slave latch. The circuit based on the DICE structure can inhibit the single event effect caused by irradiation in the circuit, and the corresponding D trigger group can effectively inhibit the single event effect caused by irradiation in use.

As shown in fig. 4, the combinational logic unit constituting the radiation-resistant 8B/10B codec circuit in the present embodiment includes six parts, namely a standard pull-up network, a standard pull-down network, a reinforced pull-up network, a reinforced pull-down network, a high-level error correction circuit and a low-level error correction circuit. The standard up/down-pull network is used as a front-stage circuit, the reinforced up/down-pull network and the error correction circuit form a rear-stage circuit, the high-level error correction circuit and the reinforced up-pull network form an up-pull network of the rear-stage circuit, and the low-level error correction circuit and the reinforced down-pull network form a down-pull network of the rear-stage circuit. The pull-up network consists of a PMOS circuit, the pull-down network consists of an NMOS, the high-level error correction circuit is a normally-on PMOS tube, and the low-level error correction circuit is a normally-on NMOS tube. The standard network is connected with the input of the reinforcing network to form a logic input, the preceding stage circuit is connected with the output of the following stage circuit to form a logic output, and the logic output is positioned between the pull-up high-level error correction circuit and the pull-down low-level error correction circuit. When the output generates single event upset, the normally open error correction network can inhibit the single event effect caused by irradiation, and correct output is realized.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention, unless the contents of the technical solution of the present invention.