阅读说明：本技术 一种基于硅衬底的石墨烯场效应管直流模型及建模方法 (Graphene field effect transistor direct-current model based on silicon substrate and modeling method ) 是由 田径 陆平 钟宏涛 胡皓全 唐璞 陈波 包永芳 雷世文 于 2021-01-13 设计创作，主要内容包括：本发明提供一种基于硅衬底的石墨烯场效应管直流模型及建模方法,属于场效应晶体管技术领域。该直流模型在常规石墨烯场效应管扩散漂移载流子运输模型的基础上,考虑硅衬底提供的硅载流子参与导电情况,对常规模型进行修正,从而建立了基于硅衬底的石墨烯场效应管直流模型,该模型能较为准确地预测硅衬底石墨烯场效应管直流特性。本发明利用数学模型揭示了物理原理,为硅衬底的石墨烯场效应管直接应用于电路设计奠定了基础。(The invention provides a graphene field effect transistor direct-current model based on a silicon substrate and a modeling method, and belongs to the technical field of field effect transistors. The direct current model considers the condition that silicon carriers provided by a silicon substrate participate in conduction on the basis of a conventional graphene field effect transistor diffusion drift carrier transport model, and corrects the conventional model, so that the graphene field effect transistor direct current model based on the silicon substrate is established, and the direct current characteristic of the graphene field effect transistor based on the silicon substrate can be accurately predicted by the direct current model. The invention discloses a physical principle by using a mathematical model, and lays a foundation for the direct application of the graphene field effect transistor of the silicon substrate to circuit design.)

1. The utility model provides a graphite alkene field effect transistor direct current model based on silicon substrate which characterized in that, on the basis of conventional graphite alkene field effect transistor diffusion drift carrier transport model, introduces the charge density in the silicon substrate and revises the total charge density of channel, and graphite alkene field effect transistor direct current model formula based on the silicon substrate after the correction specifically is:

wherein, I_dsIs drain current, W is channel width, L is channel length, μ is electron mobility at low field, v_satIs the carrier saturation velocity, V_dsIs the drain-source voltage difference, Q_graIs the charge density, Q, of the graphene channel_siIs the charge density in the silicon substrate.

2. The silicon substrate-based graphene field effect transistor direct current model as claimed in claim 1, wherein the charge density in the silicon substrate introduces a silicon carrier threshold voltage V during calculation_THCorrecting the charge density Q in the silicon substrate_siThe specific calculation formula of (A) is as follows:

Q_si＝C_ox×(V_gx±V_TH)，

wherein, C_oxIs an insulated gate capacitor, V_gxIs a gate voltage V_gsAnd the channel potential V.

3. A modeling method of a graphene field effect transistor direct-current model based on a silicon substrate is characterized by comprising the following steps:

step 1, establishing a graphene field effectSetting basic element parameters in the graphene field effect transistor according to the tube capacitance equivalent model, and calculating to obtain the graphene surface potential V_cSo as to obtain the charge density Q of the graphene channel_gra(ii) a Graphene surface potential V_cThe capacitance equivalent circuit is used for solving, and the concrete formula is as follows:

wherein the content of the first and second substances,C_tis a gate capacitance, V_gsIs a gate-source voltage, V_gs0Is the Dirac point voltage, V is the channel potential;

step 2, establishing a model for solving the charge density in the silicon substrate, setting basic element parameters required for solving the charge density of the silicon, and introducing a threshold voltage V of a silicon carrier_THSolving for charge density Q in a silicon substrate_siThe specific calculation formula is as follows:

Q_si＝C_ox×(V_gx±V_TH)，

wherein, V_gxPotential difference (V) between gate voltage and channel potential_gs-V) with a gate voltage of V_gsV is the channel potential, C_oxIs an insulated gate capacitor in a MOS structure;

step 3, solving the total charge density Q of the silicon substrate graphene field effect transistor channel_totThe concrete formula is as follows:

Q_tot＝Q_gra+Q_si；

step 4, setting scanning ranges of grid source voltage and drain source voltage by adopting a diffusion drift carrier transport model, and calculating the total charge density Q obtained in the step 3_totSubstituting into a carrier transport model to solve a drain-source current I_dsTo obtain an output characteristic curve I_ds-V_ds；

Step 5, introducing a parameter drain contact resistance R_dAnd source contact resistance R_sBuilding self-metallurgical solving modelObtaining the final output characteristic curve I according to the output characteristic curve obtained in the step 4_ds-V_ds。

4. The modeling method of the silicon substrate-based graphene field effect transistor direct current model according to claim 3, wherein the basic element parameters in the step 1 include an insulated gate capacitor C_tGate source voltage V_gsDirac point voltage V_gs0And drain-source voltage V_ds(ii) a The basic element parameters in step 2 include insulated gate capacitance C_oxGrid source voltage V_gsAnd drain-source voltage V_dsWherein C in step 1_tAnd C in step 2_oxAnd (5) the consistency is achieved.

5. The silicon substrate-based graphene field effect transistor direct current model according to claim 3, wherein the channel potential V in step 1 ranges from 0V to V_ds。

6. The modeling method of the silicon substrate-based graphene field effect transistor direct current model according to claim 3, wherein the graphene channel charge density Q in step 1_graThe specific calculation formula of (A) is as follows:

wherein q is the electron charge amount, p and n represent the hole and electron densities, respectively,is a first-order approximation of the Fermi Dirac integral, and has a kT of 0.026eV and v_FIn order to be at the fermi speed,is reduced Planck constant.

7. Graphene based on silicon substrate according to claim 3The modeling method of the field effect transistor direct current model is characterized in that the grid source voltage V in the step 4_gsThe scanning range is-5 to 1V, and the drain-source voltage V_dsThe scanning range of (2) is 0 to-7V.

8. The method for modeling the silicon-substrate-based graphene field effect transistor direct current model according to claim 3, wherein the self-metallurgical model solving in step 5 comprises: given external drain voltage V_d,extAnd a source voltage V_s,extIn the presence of a known R_dAnd R_sIn the case of (1), by setting a threshold value, the drain-source current I can be obtained when the cycle condition reaches the threshold value_ds。

9. The silicon substrate-based graphene field effect transistor direct-current model modeling method according to claim 3, wherein the silicon substrate graphene field effect transistor leakage conductance g is solved according to the output characteristic curve obtained in the step 5_dsLeakage current parameter g_dsIs defined as:

Technical Field

The invention belongs to the technical field of field effect transistors, and particularly relates to a graphene field effect transistor direct-current model based on a silicon substrate and a modeling method.

Background

With the rapid development of integrated circuits and the approaching limit of moore's law, the traditional silicon-based devices are difficult to break through higher performance. The advent of new nano-devices, carbon-based materials based on carbon nanotubes and graphene, has led to extensive research and scrutiny. Due to the fact that the graphene field effect transistor is ultrahigh in intrinsic carrier mobility, high in carrier saturation speed and unique in bipolar transmission characteristic, the graphene field effect transistor has a wide development prospect, and related research and application of the graphene field effect transistor in the fields of radio frequency circuits and terahertz are also conducted.

The graphene field effect transistor direct current model is a foundation for circuit designers, and with the improvement of the preparation of the graphene field effect transistor, many researchers have developed related modeling works, wherein the related works typically include a Jan Stake topic group, a d.ji menez topic group, a s.fregonese topic group and an i.meric topic group. The method for establishing the graphene field effect transistor model is characterized in that the graphene field effect transistor model is subjected to modeling work of a direct current model and continuously perfects the model to meet the requirements of circuit-level simulation design, the modeling methods used by the graphene field effect transistor model are different, specifically, a diffusion drift model, a Boltzmann equation model and a thin-layer charge model are involved, and the established model is well verified with experimental results.

However, with the intensive research on the graphene field effect transistor, many structures are proposed to solve the defect problem of the graphene field effect transistor. The double gate GFET structure proposed by the family of merics subjects increases gate coupling by increasing gate capacitance, and performs electrostatic doping on the back gate, thereby controlling contact resistance and threshold voltage of the top gate channel (Meric I, Dean cr, Young a, et al]IEEE, 2011) is provided. Furthermore, Szafranek B N et al use hexagonal boron nitride (h-BN) material as the back gate dielectric to reduce the residual carrier concentration N₀Because of the traditionSiO of (2)₂Compared to the substrate, h-BN has lower charged impurities and higher optical phonon energy (Szafranek B N, Fiori G, Schall D, et al. Current failure and volume e gain in bilayer field effect transducers, [ J]Nano Letters,2012,12(3): 1324.). The two methods improve the performance of the graphene field effect transistor, but adopt an insulating substrate.

In order to solve the problem of insufficient Saturation Current of the Graphene Field Effect transistor, Silicon is adopted as a substrate of the Graphene Field Effect transistor in a related structure to improve the output characteristic (Song S M, Bong J H, Hwang W S, et al. Corrigidum: Improved driven Drain Current efficiency and Voltage Gain in Graphene-on-Silicon Field Effect Transistors [ J ]. Scientific Reports,2016,6(1):28412.), but the structure is lack of a mathematical model to explain physical phenomena, and cannot be directly applied to circuit design.

Therefore, for structures such as a silicon substrate graphene field effect transistor, a relevant mathematical model is urgently needed to be established, and further the field effect transistor of the type can be industrially applied on a large scale.

Disclosure of Invention

Aiming at the problems in the background art, the invention aims to provide a graphene field effect transistor direct-current model based on a silicon substrate and a modeling method. The direct current model considers the condition that silicon carriers provided by a silicon substrate participate in conduction on the basis of a conventional graphene field effect transistor diffusion drift carrier transport model, and corrects the conventional model, so that the graphene field effect transistor direct current model based on the silicon substrate is established, and the direct current characteristic of the graphene field effect transistor based on the silicon substrate can be accurately predicted by the direct current model.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a graphene field effect transistor direct-current model based on a silicon substrate introduces charge density in the silicon substrate to correct total charge density of a channel on the basis of a conventional graphene field effect transistor diffusion drift carrier transport model, and the corrected graphene field effect transistor direct-current model based on the silicon substrate has the following formula:

wherein, I_dsIs drain current, W is channel width, L is channel length, μ is electron mobility at low field, v_satIs the carrier saturation velocity, V_dsIs the drain-source voltage difference, Q_graIs the charge density, Q, of the graphene channel_siIs the charge density in the silicon substrate.

Further, the charge density in the silicon substrate introduces a silicon carrier threshold voltage V in the calculation_THCorrecting the charge density Q in the silicon substrate_siThe specific calculation formula of (A) is as follows:

Q_si＝C_ox×(V_gx±V_TH)，

wherein, C_oxIs an insulated gate capacitor whose size depends on the relative dielectric constant and thickness of the insulating medium, V_gxIs a gate voltage V_gsPotential difference from channel potential V (V)_gs-V)。

A modeling method of a graphene field effect transistor direct-current model based on a silicon substrate comprises the following steps:

step 1, establishing a graphene field effect transistor capacitance equivalent model, setting parameters of basic elements in the graphene field effect transistor, and calculating to obtain a graphene surface potential V_cSo as to obtain the charge density Q of the graphene channel_gra(ii) a Wherein, the surface potential V of the graphene_cThe capacitance equivalent circuit is used for solving, and the concrete formula is as follows:

wherein the content of the first and second substances,C_tis a gate capacitance, V_gsIs a gate-source voltage, V_gs0Is the Dirac point voltage, V is the channel potential;

step 2, establishing a silicon liningModel for solving charge density in substrate, setting parameters of basic elements needed for solving charge density of silicon, and threshold voltage V of introduced silicon carrier_THSolving for charge density Q in a silicon substrate_siThe specific calculation formula is as follows:

Q_si＝C_ox×(V_gx±V_TH)，

wherein, V_gxPotential difference (V) between gate voltage and channel potential_gs-V) with a gate voltage of V_gsV is the channel potential, C_oxIs an insulated gate capacitor in a MOS structure;

step 3, solving the total charge density Q of the silicon substrate graphene field effect transistor channel_totThe concrete formula is as follows:

Q_tot＝Q_gra+Q_si；

step 4, setting scanning ranges of grid source voltage and drain source voltage by adopting a diffusion drift carrier transport model, and calculating the total charge density Q obtained in the step 3_totSubstituting into a carrier transport model to solve a drain-source current I_dsThereby obtaining an output characteristic curve (I)_ds-V_ds)；

Step 5, introducing a parameter drain contact resistance R_dAnd source contact resistance R_sBuilding a self-metallurgical solution model, perfecting the output characteristic curve obtained in step 4 to obtain a final output characteristic curve (I)_ds-V_ds)。

Further, the basic element parameters in step 1 include insulated gate capacitance C_tGate source voltage V_gsDirac point voltage V_gs0And drain-source voltage V_dsThe basic element parameters in step 2 include insulated gate capacitance C_oxGrid source voltage V_gsAnd drain-source voltage V_dsWherein C in step 1_tAnd C in step 2_oxAnd (5) the consistency is achieved.

Further, the channel potential V varies in a range of 0 to V_ds。

Further, the charge density Q of the graphene channel in the step 1_graThe concrete formula of (1) is as follows:

wherein q is the electron charge amount, p and n represent the hole and electron densities, respectively,is a first-order approximation of the Fermi Dirac integral, and has a kT of 0.026eV and v_FIn order to be at the fermi speed,is reduced Planck constant.

Further, in step 4, the gate source voltage V_gsThe scanning range is preferably-5 to 1V, and the drain-source voltage V_dsThe scanning range of (2) is preferably 0 to-7V.

Further, the step 5 of solving the model from the metallurgical model specifically includes: given external drain voltage V_d,extAnd a source voltage V_s,extIn the presence of a known R_dAnd R_sIn the case of (3), the drain-source current I can be determined by setting a threshold value when the cycle condition reaches the threshold value_ds。

Further, the leakage conductance g of the silicon substrate graphene field effect transistor can be solved according to the output characteristic curve obtained in the step 5_dsLeakage current parameter g_dsIs defined as:

the mechanism of the invention is as follows:

on the conduction principle of a conventional graphene field effect transistor, the insulating substrate has no influence on a graphene channel (substrate leakage current is not considered). However, in the silicon substrate graphene field effect transistor, the silicon substrate has obvious influence on the graphene channel, so that the difference between the silicon substrate graphene field effect transistor and the conventional graphene field effect transistor is brought by considering that the carrier density of the silicon substrate participates in the conduction of the graphene field effect transistor. However, on the basis of the traditional MOS structure, solving the carrier density of the silicon substrate cannot be directly applied to a field effect transistor model (no practical effect) byThe invention introduces a silicon threshold voltage V_THThe influence of the silicon surface charge density distribution on the total channel charge density, corrected for the silicon substrate surface charge distribution, also explains the reason for the actual saturation phenomenon.

In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:

the field effect transistor direct current model is combined with two semiconductor conduction modes of graphene and silicon, the actual possible charge distribution conditions of the graphene and silicon channels are analyzed, the silicon carrier migration condition brought by a silicon substrate is considered, and the silicon carrier threshold voltage V is introduced_THThe parameters are used for correcting the charge density in the silicon substrate, so that the established model can accurately predict the direct-current characteristic of the graphene field effect transistor on the silicon substrate, the physical principle is disclosed by utilizing a mathematical model, and a foundation is laid for the direct application of the graphene field effect transistor on the silicon substrate to circuit design.

Drawings

Fig. 1 is a schematic circuit diagram of a graphene field effect transistor with a silicon substrate.

Fig. 2 is a schematic diagram of a graphene field effect transistor capacitance equivalent circuit model.

FIG. 3 is V_TH-V_gsThe relationship is shown schematically.

FIG. 4 is a schematic diagram of self-solving the current steps.

Fig. 5 is a schematic diagram of an output characteristic curve of the graphene field effect transistor.

Fig. 6 is a schematic diagram of leakage conductance of the graphene fet.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following embodiments and accompanying drawings.

Fig. 1 is a schematic circuit diagram of a graphene field effect transistor with a silicon substrate, and as shown in fig. 1, the field effect transistor is composed of metal electrodes (a source electrode, a gate electrode and a drain electrode), a gate insulating oxide layer, a graphene conducting channel and a micro-doped silicon substrate, wherein the doping concentration of the silicon substrate is in a micro-doping level, the resistivity after doping is 1-5 Ω · cm, and the silicon substrate is n-type doped.

Aiming at the circuit structure, a field effect tube direct current model is established.

A graphene field effect transistor direct current model based on a silicon substrate is characterized in that on the basis of a conventional graphene field effect transistor diffusion drift carrier transport model, the charge density in the silicon substrate is introduced to correct the total charge density of a channel; wherein the charge density in the silicon substrate is calculated to introduce a silicon carrier threshold voltage V_THAnd (6) correcting. Reference is made to the parameters of the basic elements of the Graphene Field Effect Transistor in this example (Song S M, Bong J H, Hwang W S, et al. Corrigidum: advanced d Drain Current practice and Voltage Gain in Graphene-on-Silicon Field Effect transistors [ J]Scientific Reports,2016,6(1): 28412).

A modeling method of a graphene field effect transistor direct-current model based on a silicon substrate comprises the following steps:

step 1, establishing a graphene field effect transistor capacitance equivalent model, wherein the specific formula of the model is as follows:

wherein, I_dsW is the drain current, W is the channel width, L is the channel length, μ is the electron mobility at low field (the strength of the electric field is below 30k V/cm), Q_totIs the channel total charge density, v_satIs the carrier saturation velocity, V_dsThe scanning range of the drain-source voltage is 0 to-7V; specifically, W is 10 μm, L is 20 μm, and μ is an electron mobility μ_nAnd hole mobility μ_pTwo cases, μ_nIs 500cm²/(V·s)，μ_pIs 1150cm²/(V·s)，ν_satThe concrete expression is as follows:

wherein the Fermi velocity v_FIs 10⁶m/s，Critical carrier density ρ_crit＝(Ω/ν_F)²/(2 π), effective energyIs at a value of 75meV,in order to approximate the constant of planck,the Planck constant h is 6.63X 10^-34J · s, electron charge amount q of 1.6 × 10^-19C, net charge density Q_netThe calculation formula is as follows:

wherein p and n represent hole and electron densities, respectively,is a first order approximation of the Fermi Dirac integral, with a kT of 0.026 eV;

step 2, setting parameters of basic elements in the graphene field effect transistor, and calculating to obtain the surface potential V of the graphene_cSo as to obtain the charge density Q of the graphene channel_gra；

Specifically, the capacitance equivalent circuit is used for solving, the equivalent circuit model is shown in FIG. 2, and C in the diagram_qIs the quantum capacitance of graphene, which is defined as:

wherein, V_chChannel potential for graphene, defined as C_qVoltage drop over, C_qThe exact expression of (c) is:

at q × V_ch＞＞k_BUnder the condition of T, the above formula can be approximately simplified as follows:

applying kirchhoff's circuit law to an equivalent capacitance circuit, the following relation can be obtained:

Q_top＝[V_gs-V_gs0-V(x)+V_c]C_t

Q_gra＝α(V_c)C_qV_c

wherein Q is_topTo be stored in C_tCharge of (5), V_gsIs the top gate voltage. V_gs0Is the top gate voltage when the drain current reaches a minimum value, V (x) is the voltage drop at the graphene channel x, C_tIs a top gate oxide capacitor, alpha (V)_c) The capacitance weight factor is defined as the following specific expression:

the system is electrically neutral and can obtain:

Q_gra＝-Q_top

substituting the above three formulas into the above formula to obtain V_cExpression:

wherein, in the circuit V: (_X) Is the channel potential V in relation to a. When q × | V_cWhen | < kT, alpha is approximately equal to 1, qx | V_cAlpha is approximately equal to 0.5 when | is > kT; many existing GFET models use the constant α ≈ 0.5 as the calculation constant of the above equation. At qx | V_cQuantum capacitor C under condition of | > kT_qCan be calculated by approximate expression, and V can be obtained by substituting the approximate expression into the above formula and arranging_c：

Wherein the content of the first and second substances,solving for V_cTime, grid capacitance C_t＝ε₀κ/d，ε₀The dielectric constant in vacuum, k is 6, the thickness d of the gate oxide is 20nm,gate source voltage V_gsThe scanning range is-5 to 1V, V_gs0＝0.8V；

Charge density Q of graphene channel_graThe specific calculation formula of (A) is as follows:

step 3, establishing the charge density Q in the silicon substrate_siModel of solution, carrier density Q provided by the silicon substrate for the conduction channel_siCan be given by the definition of the channel charge density in MOS transistors, Q_siThe specific expression is as follows:

Q_si＝C_ox×V_gx

wherein, C_oxIs an insulated gate capacitor in MOS structure, the size of which depends on the relative dielectric constant and thickness of the insulating medium, V_gxPotential difference (V) between gate voltage and channel potential_gs-V) with a gate voltage of V_gsThe variation range of the channel potential V is 0-V_ds；

Considering that the carriers of the silicon substrate are not completely controlled by the longitudinal electric field formed by the gate voltage, the charge density Q of the silicon substrate is calculated_siIn the process, a potential barrier effect is formed between the graphene channel and the silicon substrate, namely, the channel where the silicon substrate is located can allow carriers in the substrate to participate in transportation only when the channel reaches a specific potential; the specific potential followsChannel position variation, magnitude thereof and gate voltage V_gsIn connection with this, we introduce the silicon carrier threshold voltage V for this purpose_THBy applying a parameter V_THThe control of the MOS transistor is used for representing the actual possible distribution situation of the silicon channel charge, and the carrier density Q of the silicon channel is calculated by the definition of the MOS transistor_siThe correction is the following equation:

Q_si＝C_ox×(V_gx±V_TH)

C_oxand C_tSame calculation method, V_THAnd V_gsThe corresponding relation curve is shown in FIG. 3;

step 4, obtaining the charge density Q of the graphene channel according to the step 2_graAnd step 3, obtaining the carrier density Q of the silicon channel_siSolving total charge density Q of silicon substrate graphene field effect transistor channel_totThe calculation formula is as follows:

Q_tot＝Q_gra+Q_si；

step 5, setting scanning ranges of grid-source voltage and drain-source voltage based on the graphene field effect transistor diffusion drift carrier transport model established in the step 1, and calculating the total charge density Q obtained in the step 4_totSubstituting the model into a graphene field effect transistor diffusion drift carrier transport model to solve a drain-source current I_dsThereby obtaining an output characteristic curve (I)_ds-V_ds)；

Step 6, introducing a parameter drain contact resistance R_dAnd source contact resistance R_sBuilding a self-metallurgical solution model, perfecting the output characteristic curve obtained in step 5 to obtain a final output characteristic curve (I)_ds-V_ds)；

In the actual calculation of the graphene field effect transistor direct-current model based on the silicon substrate, the actual ohmic contact should be considered, and the actual ohmic contact is mainly reflected in the drain contact resistance R_dAnd source contact resistance R_sTo create the self-metallurgical solution model, calculation is performed by giving an external leakage voltage V_d,extAnd a source voltage V_s,extIn the presence of a known R_dAnd R_sIn this case, a threshold value may be set, and when the loop condition reaches the threshold value, the loop condition may be evaluatedOutput current I_dsThe specific solving flow is shown in FIG. 4,

V_d,ext＝V_d+I_dsR_d

V_s,ext＝V_s+I_dsR_s

when calculating the model, R_dAnd R_sEqual, neglecting the gate resistance R due to small gate leakage current_gThus V_g,ext＝V_g，I_dsInitial value is set to 0, V_s,extUsually the ground is also 0, then in actual calculations:

V_ds,ext＝V_ds+2×I_dsR_d

finally obtained I_ds-V_dsThe curve results are shown in FIG. 5, in which the dashed line corresponds to the curve as the modeling result (Calc), the scattered point symbol corresponds to the curve as the experimental result (Expe), and different curves correspond to different V_gsAs can be seen from the figure, the model data of the corrected graphene field effect transistor model is integrally matched with the experimental data, so that the accuracy of the model is reflected;

step 7, solving leakage conductance g of silicon substrate graphene field effect transistor_dsParameter, leakage conductance parameter g_dsIs defined as:

utilizing the drain-source current I solved in the step 6_dsAnd a drain-source voltage V_dsThe leakage conductance may be calculated, and the result is shown in fig. 6. The dotted line part in fig. 6 is a result of the leakage conductance being around 0, and is also a part corresponding to current saturation of the silicon substrate graphene field effect transistor, i.e. I_dsHardly following V_dsChange of_dsSubject to V only_gsThe control, in which case the transistor can be considered as a voltage controlled current source, should operate in that region if it is operated as an amplifier device.

While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.