阅读说明：本技术 具有垂直触发和放电路径的晶体管注入式可控硅整流器(scr) (Transistor injection Silicon Controlled Rectifier (SCR) with vertical trigger and discharge path ) 是由 任俊杰 于 2021-01-15 设计创作，主要内容包括：一种静电放电(ESD)保护电路具有可控硅整流器(SCR),其放电电流路径在第一方向上。触发晶体管的触发电流在垂直于第一方向的第二方向上流动。触发晶体管可以是鳍式场效应晶体管(FinFET)晶体管,其电流沿着鳍片长边方向流动。触发电流流入连接N+漏极,并流入连接N+漏极中心部分下方的N-阱,将载流子注入PNPN SCR的N-基极。注入的电流流过基极,产生一个电压梯度,该电压梯度导通与FinFET晶体管平行但隔开的P+发射极中的PN结,导致垂直于鳍片流动的放电电流。垂直的放电电流流过衬底,衬底可以处理比小鳍片更大的电流。(An electrostatic discharge (ESD) protection circuit has a Silicon Controlled Rectifier (SCR) with a discharge current path in a first direction. The trigger current of the trigger transistor flows in a second direction perpendicular to the first direction. The trigger transistor may be a fin field effect transistor (FinFET) transistor, the current of which flows in the long side direction of the fin. The trigger current flows into the N + drain and into the N-well under the center portion of the N + drain, injecting carriers into the N-base of the PNPN SCR. The injected current flows through the base creating a voltage gradient that turns on the PN junction in the P + emitter parallel to but spaced from the FinFET transistor, resulting in a discharge current flowing perpendicular to the fin. A vertical discharge current flows through the substrate, which can handle larger currents than small fins.)

1. A triggered Silicon Controlled Rectifier (SCR) electrostatic discharge (ESD) protection structure, comprising:

a trigger transistor having a gate for controlling a trigger current flowing between a source and a connecting drain, wherein the gate, the source, and a first portion of the connecting drain are formed over a substrate of a first polarity type, wherein the source and the connecting drain are of a second polarity type;

wherein the connecting drain extends across a well boundary, the connecting drain having the first portion over the substrate of the first polarity type and a second portion over the well of the second polarity type;

a first SCR region having the first polarity type formed in the well;

a first terminal connected to the first SCR region;

a second terminal connected to the source;

wherein the first SCR region provides a discharge current from the first terminal, the discharge current flowing from the first SCR region, through the well, to the substrate under the source, and to the source to the second terminal;

wherein the discharge current flows in a first direction;

wherein the trigger current flows from the source to the connecting drain in a second direction under the gate;

wherein the first direction is orthogonal to the second direction;

so that the trigger current and the discharge current are orthogonal.

2. The triggered SCR ESD protection structure of claim 1, further comprising:

a first tap having the first polarity type, the first tap being formed in the substrate, the first tap biasing the substrate by being connected to a second power supply;

a second tap having the second polarity type, the second tap formed in the well, the second tap biasing the well by being connected to a first power supply.

3. The triggered SCR ESD protection structure of claim 2, wherein the first SCR region is substantially parallel to a line containing the trigger transistor, the source, and the connecting drain, wherein the first SCR region is separated from the trigger transistor, the source, and the connecting drain by the well.

4. The triggered SCR ESD protection structure of claim 3, wherein the first SCR region is located between the second tap and the trigger transistor.

5. The triggered SCR ESD protection structure of claim 2, wherein the gate and the source and the first portion of the connecting drain are formed within an island of the substrate of the first polarity type;

wherein the island is surrounded by wells of the second polarity type.

6. The triggered SCR ESD protection structure of claim 5, further comprising:

a plurality of islands, each island having a first portion of the gate, the source, and the connecting drain;

wherein the plurality of islands are arranged along the second direction;

wherein the connecting drains of adjacent islands are connected together, a first portion of the connecting drains being in a first island, a second first portion of the connecting drains being in a second island, the second portion of the connecting drains being between the first portion and the second first portion.

7. The triggered SCR ESD protection structure of claim 2, further comprising:

a second gate between the source and an end drain having the second polarity type;

wherein the end drain extends across the well boundary, a first portion of the end drain being over the substrate of the first polarity type and a second portion of the end drain being over the well of the second polarity type;

wherein the end drain, the source, and the connection drain are all located on a line parallel to the second direction.

8. The triggered SCR ESD protection structure of claim 2, wherein the source and the connecting drain are formed in a fin over the substrate surface, a long side direction of the fin being parallel to the second direction;

wherein the trigger current flows in the second direction in the fin;

wherein the gate is formed on the top of the fin and on both sides of the fin, the gate being formed between the source and the connecting drain;

wherein the gate, the source, and the first portion of the connecting drain form a fin field effect transistor (FinFET) transistor.

9. The triggered SCR ESD protection structure of claim 8, wherein a plurality of fins are formed in parallel along the second direction, each fin having a FinFET transistor that carries a portion of the trigger current in the second direction;

wherein the sources of adjacent fins are connected together by lateral diffusion of a second polarity type in the substrate between adjacent fins;

wherein the gates on adjacent fins are connected together;

wherein the connecting drains of adjacent fins are connected together by lateral diffusion of a second polarity type in the substrate between the adjacent fins.

10. The triggered SCR ESD protection structure of claim 9, wherein the first SCR region further comprises a plurality of fins formed over the well surface, wherein the plurality of fins comprises fins that are parallel to each other, and a long side of each fin is parallel to the second direction.

11. The triggered SCR ESD protection structure of claim 2, wherein the first polarity type is p-type and the second polarity type is n-type.

12. The triggered SCR ESD protection structure of claim 11, wherein the gate is connected to a trigger signal generator that activates the gate to conduct the trigger current upon detection of an electrostatic discharge (ESD).

13. The triggered SCR ESD protection structure of claim 2, further comprising:

a first diode region of a first polarity type connected to the second terminal;

a second diode region of a second polarity type connected to the first terminal;

wherein the second tap is located between the first SCR region and the first diode region;

wherein the first diode region is located between the second tap and the second diode region.

14. An electrical protection device comprising:

a substrate of a first polarity type;

a well of a second polarity type formed in the substrate;

wherein the first polarity type is opposite to the second polarity type;

a substrate island surrounded by the well;

a first emitter region of a first polarity type formed in said well as a continuous emission band wider than and extending beyond said island on either side of said island, said first emitter region being spaced from said island;

a gate formed in the island, the gate for controlling a trigger current flowing in a channel under the gate;

a diffusion strip parallel to a continuous emitter strip of the first emitter region, the diffusion strip intersecting the gate to form a channel under the gate;

a source region on a first end of the diffusion strip, the source region being entirely within the island and having the gate at one end;

a drain region on the diffusion strip at the other end of the gate, the gate passing through the diffusion strip, the drain region being within the island;

an extension of the diffusion strip connected to the drain region and extending beyond the island to connect with the well;

wherein the diffusion strip is doped with a dopant of a second polarity type in addition to the channel under the gate;

a well tap of a second polarity type formed in the well and further from the island than the first emitter region;

a substrate tap of a first polarity type formed outside the well and outside the island;

wherein an x-section orthogonal to the substrate plane intersects the substrate plane at a line in an x-direction;

wherein the x-section passes through the island, the source region in the island, the gate in the island, the channel under the gate, the drain region in the island, and an extension of the diffusion strip;

wherein a y-section orthogonal to the substrate plane and orthogonal to the x-section intersects the substrate plane at a line in a y-direction, the line in the y-direction being orthogonal to the line in the x-direction;

wherein the y-section passes through the island, the source region in the island, the well, and the first emitter region;

a first terminal for electrical connection to the first emitter region;

a second terminal for electrical connection to the source region;

wherein a trigger voltage applied across the first and second terminals turns on the gate and conducts a trigger current from the source region through the channel to the drain region and the extension of the diffusion strip;

wherein the trigger current flows in the x-direction;

wherein the trigger current injects charge from the extended portion of the diffusion strip into the well, causing a voltage gradient, turning on the first emitter region to conduct a discharge current;

wherein said discharge current flows from said first emitter region through said well to an island of said substrate to said source region in said island;

wherein the discharge current flows in the y-direction, perpendicular to the trigger current flowing in the x-direction.

15. The electrical protection device of claim 14, further comprising:

a second island formed within the well;

a second gate formed within the second island;

wherein the diffusion strip extends to the second island and forms a second channel under the second gate;

a second source region formed in the diffusion strip, beyond the second gate, and within the second island;

wherein the first emitter region is formed in the well as a continuous emission band extending beyond the island and beyond the second island, the first emitter region being spaced apart from the island and the second island;

a second emitter region of the first polarity type formed in the well as a second continuous emission band extending beyond the island and beyond the second island, the second emitter region being spaced apart from the island and the second island;

wherein the first emitter region and the second emitter region are on opposite sides of the diffusion strip that intersects the island and the second island.

16. The electrical protection device of claim 15, further comprising:

a third gate formed in the island with the third gate cross spanning the diffusion zone and having a third channel;

a third drain formed in the diffusion strip adjacent the third gate and opposite the source region, the third drain region extending to one end of the island to make electrical contact with the well;

wherein a third trigger current flows from the source region through the third channel to the third drain region, the third trigger current being in a direction opposite to the trigger current, the third trigger current flowing in a negative x-direction;

a fourth gate formed in the second island, wherein the fourth gate crosses the diffusion strip and has a fourth channel;

a fourth drain formed in the diffusion strip adjacent the fourth gate and opposite the source region, the fourth drain extending to an end of the second island to make electrical contact with the well.

17. The electrical protection device of claim 16, wherein the diffusion strip further comprises a plurality of fins extending over the substrate surface and over the surface of the well, the plurality of fins being parallel to each other in the x-direction;

wherein the gate is formed over the plurality of fins with the channel within the fin under the gate;

wherein the source region and the drain region are formed in the fin on an island and an extension of the drain region is formed in the fin above the well.

18. The electrical protection device of claim 17, wherein the first polarity type is n-type and the second polarity type is p-type, wherein the gate, the channel, the source region, and the drain region form a p-channel fin field effect transistor (FinFET).

19. A fin field effect transistor (FinFET) electrostatic discharge (ESD) protection device, comprising:

a substrate of a first polarity type;

a well of a second polarity type formed within the substrate;

an island aperture within the well, the island aperture being part of the substrate surrounded by the well;

a plurality of fins formed over the substrate, each of the plurality of fins having a longest dimension in an x-direction, wherein the plurality of fins are formed along imaginary line portions that are parallel to each other;

a gate formed over one of the plurality of fins;

a first fin of the plurality of fins having a second polarity type for a fin portion not covered by the gate and a first polarity type for a fin portion covered by the gate;

a source region of the first fin, the source region formed over the island hole, the source region adjacent to the gate;

a drain region in the first fin, the drain region formed over the island hole, the drain region adjacent the gate on a side opposite the source region;

an extension region of the first fin extending from the drain region and beyond the island aperture and over the well, the extension region for injecting carriers into the well from a trigger current flowing from the source region, under the gate and through the drain region and into the extension region;

wherein the trigger current flows in the x-direction;

a first emitter fin of the plurality of fins formed over the well and longer in length than the first fin, the first emitter fin being parallel to the first fin, the first emitter fin having a first polarity type;

wherein when the trigger current injects carriers into the well, a discharge current is initiated that flows from the first emitter fin through the well in the y-direction, into the substrate in the island hole, and into the source region of the first fin;

wherein the first emitter fin is electrically connected to the first terminal;

wherein a source region of the first fin is electrically connected to the second terminal;

wherein the trigger current flows in the x-direction to trigger the discharge current to flow in the y-direction when an electric shock is applied between the first terminal and the second terminal.

20. The FinFET ESD protection device of claim 19, further comprising:

a second island aperture within the well, the second island aperture being part of the substrate surrounded by the well;

wherein the first fins have a second polarity type for fin portions not covered by the gate or a second gate, the first fins have a first polarity type for fin portions covered by the gate or covered by the second gate;

wherein the first fin further comprises:

a second source region of the first fin, the second source region formed over the second island hole, the second source region adjacent to the second gate;

a second drain region in the first fin formed over the second island hole, the second drain region adjacent the second gate on a side of the second gate opposite the second source region;

a second extension region of the first fin extending from the second drain region and beyond the second island hole and over the well, the extension region for injecting carriers into the well from a second trigger current flowing in a negative x-direction from the second source region, under the second gate, and through the second drain region and into the extension region;

wherein the extension region and the second extension region are adjacent to each other and contact each other on the well between the island hole and the second island hole.

Technical Field

The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit with a vertical trigger and discharge device in a Fin-Field-Effect Transistor (FinFET) process.

Background

Integrated Circuits (ICs) are susceptible to damage from electrostatic discharge (ESD) pulses. Various ESD protection structures are placed near the input, output or bidirectional I/O pins of an IC. Many of these protection structures use passive components such as series resistors, diodes, and thick oxide transistors. Other ESD structures use active transistors to safely shunt ESD current.

As manufacturing capabilities increase and device dimensions shrink, lower voltages are applied to transistors during normal operation. These smaller transistors are more prone to overvoltage faults, but can operate at lower supply voltages and therefore consume less power and generate less heat.

Such smaller transistors are typically placed in the internal "core" of the IC, while larger transistors with gate lengths exceeding a minimum value may be placed in peripheral devices around the core. ESD protection structures are placed in the peripheral devices using these larger transistors.

The thinner gate oxide of the core transistor is shorted by the smaller capacitive coupling current applied to the tiny core devices, and the substrate junction melts. Static electricity from a person or machine can create such damaging currents that are only partially blocked by the peripheral input protection circuitry.

Fig. 1 shows a chip with several ESD protection clamps. The core circuit 21 includes core transistors 22, 24, and the core transistors 22, 24 have a small channel length and can be damaged by a relatively low voltage current. Core circuitry 21 receives a supply voltage VDD, such as 1.8 volts, 1.2 volts, or some other value. There may be thousands of core transistors in core circuitry 21.

Protection from ESD pulses may be provided on each I/O pad by a power clamp 26. The power clamp 26 is connected between VDD and ground (VSS) and shunts ESD pulses between the power rails.

Each I/O pad 10 may be provided with one or more ESD protection devices 12, 16 to prevent various possibilities. For a positive ESD pulse applied from ground to I/O pad 10, ESD protection device 16 turns on, and for a positive ESD pulse applied from ground to I/O pad 11, ESD protection device 18 turns on. Similarly, ESD protection device 12 is turned on for a positive ESD pulse applied from I/O pad 10 to VDD, and ESD protection device 14 is turned on for a positive ESD pulse applied from I/O pad 11 to VDD. In some cases, the power clamp 26 may also be switched on.

Recently, planar MOSFET devices are being replaced by finfets. Finfets use a more three-dimensional transistor structure in which the transistor gate is no longer in a single plane. Finfets use a smaller region with less leakage than conventional planar transistors.

Fig. 2 shows a prior art FinFET device. The N + regions 42, 44 are formed on the substrate 20 and are surrounded by the oxide 62. The substrate 20 may be a Silicon substrate, or an Insulator used in a Silicon-On-Insulator (SOI) process. The N + regions 42, 44 are very thin, having a fine fin-like appearance. Between N + region 42 and N + region 44 is a connection region of lightly doped p-type silicon that serves as a transistor channel. N + region 42, channel connection region, and N + region 44 may all be formed on the same fin of silicon.

A gate 52 is formed around the channel connection region. The gate 52 is not flat but has an inverted U-shape that surrounds the channel connection between the N + regions 42, 44. Gate oxide 60 is formed on three sides of the fin-shaped channel connection region rather than only on the top surface of the channel region.

Due to this 3-dimensional gate and channel structure, FinFET transistors may have better current drive than equivalent flat transistors for the same wafer area. However, when a FinFET transistor is used for ESD protection, high ESD currents can damage the FinFET transistor. In particular, extreme heat sometimes occurs near the N + region 42 of the junction (junction) to the channel region under the gate 52. When a large ESD current passes through N + region 42, this extreme heat can permanently damage gate oxide 60 and N + region 42, causing the device to leak or fail.

In addition, the thin or elongated size of the fin for the N + region 42 may result in current crowding to a narrow region, creating a localized hot spot. The elongated fins of N + region 42 impede heat dissipation and N + region 42 is surrounded by an insulator including oxide 62 and a passivation insulator covering everything, including N + region 42, oxide 62 and gate 52. Oxides and other insulators are generally poor thermal conductors.

When a FinFET device is used in an ESD structure, the on-resistance (turn-on resistance) and wiring resistance (routing resistance) of the device are higher compared to an ESD structure constructed using planar transistors.

It is desirable to have an ESD protection circuit that has a lower parasitic resistance even when FinFET devices are used. It is desirable to have an ESD input protection circuit that can carry large currents but still has low resistance. It is desirable to have an ESD circuit that can be used in both conventional planar and FinFET processes.

Drawings

Fig. 1 shows a chip with several ESD protection clamps.

Fig. 2 shows a prior art FinFET device.

Fig. 3 shows a planar process ESD SCR structure with vertical trigger and discharge paths.

Fig. 4 highlights the horizontal and vertical current flow in the ESD SCR structure.

Fig. 5 is a horizontal cross section along the trigger transistor.

Fig. 6 is a vertical cross-section along the discharge current path.

Fig. 7 is a schematic diagram of the structure of PNPN in SCR.

Fig. 8 is a vertical cross-sectional view of a FinFET process.

Fig. 9 is a horizontal cross-sectional view through a FinFET trigger transistor.

Fig. 10 is a FinFET transistor for triggering the SCR.

Fig. 11 is an ESD SCR structure of a FinFET process with vertical trigger and discharge paths.

Fig. 12 is another SCR for a double well process.

Fig. 13 is an SCR device with parallel diodes for bi-directional ESD protection.

Fig. 14 is an electrical diagram of an SCR having the p-diode of fig. 13.

Fig. 15 is a gate trigger of the SCR.

Detailed Description

The present invention relates to improvements in ESD protection structures. The following description is presented to enable one of ordinary skill in the art to make and use the invention in the context of a particular application and its requirements. Various modifications to the preferred embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The inventors have recognized that FinFET devices are ideal for use as trigger devices in ESD structures, but are less than ideal for use as discharge devices. Large ESD currents flowing through the discharge device can quickly heat up and damage the miniaturized FinFET device having a channel within the tiny FinFET fin. However, FinFET transistors are ideal trigger devices because the channel within the fin of a FinFET device is small and therefore has a very fast turn-on speed.

The inventors have further recognized that FinFET processing tends to form all fins in the same direction. For example, a FinFET process may have all fins aligned in the horizontal direction and no fins aligned in the vertical direction. The FinFET process itself may require fin alignment and parallelism because the various processing steps can only form fins in one direction.

The ESD structure may use a Silicon-Controlled Rectifier (SCR). The SCR may have a trigger device (e.g., a MOSFET transistor) and a discharge device (e.g., an NPN or PNP bipolar transistor) that are part of the PNPN or NPNP structure of the SCR. These bipolar transistors may be formed in substrate diffusion regions and wells.

The inventors have further recognized that FinFET devices aligned in the horizontal direction may be used to trigger the SCR, while discharge devices in the substrate may be formed in the vertical direction. The trigger current may flow through the fins in the horizontal direction, while a larger discharge current may flow through the substrate in the vertical direction. The discharge current is perpendicular to the trigger current flowing in the fin, so the discharge current does not overheat the FinFET fin because the discharge current flows perpendicular to the fin. Thus, the FinFET fin is not damaged by large discharge currents.

The ESD device can be tuned by adjusting the characteristics or geometry of the horizontal FinFET device to achieve fast triggering, while the ESD discharge current can be individually tuned by adjusting the size and geometry of the vertical current path through the substrate. Large structures in the substrate may provide low on-resistance for discharge current without damaging the delicate FinFET transistors used for triggering. Since the current paths for firing and discharging are perpendicular, they can be optimized separately.

Fig. 3 shows a planar process ESD SCR structure with vertical trigger and discharge paths. The device can be implemented in FinFET and planar processes. A simpler planar process device is first introduced.

The gates 30, 32 may be polysilicon, forming MOS transistors between the source N + source 34 and the N + drains 36, 38. The connecting N + drains 38 are connected to both gates 30, while the end N + drains 36 are each connected to only one gate 32. The openings in the N-well 90 form islands of the p-substrate 20 that surround and underlie the formed transistors whose gates 30, 32 intersect between the N + source 34 and the N + drains 36, 38.

The current flowing through these trigger transistors formed by gates 30, 32 is in a horizontal direction, along or parallel to horizontal cross-section 110. The central region of the N + drain 38, which is outside the island of the p-substrate 20 and above the N-well 90, serves as a tap (tap) for the N-well 90 to inject the trigger current into the N-well 90.

The P + emitter 86 is formed in the N-well 90 above and below the center trigger transistor a distance along the horizontal cross section 110 such that the P + emitter 86 does not intersect the horizontal cross section 110. An N + tap 92 is formed to bias the N-well 90 further away from the P + emitter 86. A P + tap 84 is formed out of the N-well 90 to bias the P-substrate 20. Since the P-substrate 20 extends under the shallower N-well 90, the island of P-substrate 20 with transistor gates 30, 32 is electrically connected to the region of P-substrate 20 with the P + tap 84.

The PNPN SCR structure is formed by the P + emitter 86, the N-well 90, the P-substrate 20 and the N + source 34. This is a vertical configuration because current flows primarily in a vertical direction, along or parallel to vertical cross-section 120. Since the diffusion area in the substrate is large, a large discharge current can flow in the vertical direction parallel to the vertical cross section 120. A smaller trigger current flows through the transistor in the horizontal direction parallel to the horizontal cross section 110.

Fig. 4 highlights horizontal and vertical currents in the ESD SCR structure. The IO pad is connected to the N + source 34 between the gates 30, 32. When an ESD pulse is applied to the IO pad, the voltage at N + source 34 rises rapidly and turns on the transistor, causing a trigger current to flow under gate 30, from N + source 34 to the connecting N + drain 38. The gates 30, 32 may be grounded. A power supply or VDD may be applied 92 to bias the N-well 90 and to the P + emitter 86. Current flowing through gate 30 to connecting N + drain 38 may flow through N-well 90 to N + tap 92 and VDD.

When this current flows through the relatively high resistance of the N-well 90, a voltage gradient or drop is created. Once this voltage gradient exceeds the PN junction diode voltage by about 0.5 volts, the PN junction from the P + emitter 86 to the N-well 90 conducts, injecting positive charges (holes) back into the N-well 90, collected by the P-substrate 20, and flowing through the N + source 34 to the IO pad. The holes collected by the p-substrate 20 pull up the potential of the region of the p-substrate 20 that is the base of the NPN Bipolar Junction Transistor (BJT) of the N-well 90, the p-substrate 20 and the N + source 34. This higher potential of the P-substrate 20 triggers the turn on of the NPN BJT, which further pulls down the potential of the N-well 90. With the NPN and PNP structures turned on, the SCR becomes self-sustaining.

Fig. 5 is a horizontal cross section along the trigger transistor. The horizontal cross section 110 (fig. 3) includes transistors with gates 30, 32 having gate oxides above the p-substrate 20. Gate 30 forms a transistor between N + sources 34, connected to IO pad, and connected to connecting N + sources 38, whose central region is connected to N-well 90. The gate 32 forms a transistor between an N + source 34 and an end N + drain 36. The end drain 36 and the connecting N + drain 38 form a symmetrical transistor structure with the gates 32, 30. The terminal N + drain 36 may also be connected to the N-well 90 depending on process alignment so that the trigger current may also flow under the gate 32 and into the N-well 90 to enhance triggering. The P + tap 84 biases the P-substrate 20 to VSS (ground). Since the P-substrate 20 is deeper than the N-well 90, the island of P-substrate under the gates 30, 32 is electrically biased by the P + tap 84. The gates 30, 32 may also be connected to VSS.

Fig. 6 is a vertical cross section along the discharge current path. Vertical section 120 is perpendicular to horizontal section 110, and horizontal section 110 passes centrally through N + source 34 and the trigger device (not shown), tangential to the plane of fig. 6.

The central island of the p-substrate 20 surrounds the N + source 34, which is connected to the IO pad. N-wells 90 are formed on either side of the central island and include a P + emitter 86 and an N + tap 92, both connected to VDD. The P + tap 84 biases the P-substrate 20.

After triggering, the SCR conducts a discharge current from VDD, P + emitter 86, N-well 90, P-substrate 20 to N + source 34, i.e., the PNPN structure. The relatively large diffusion structure of N + source 34, P + emitter 86, N-well 90 can carry large discharge currents.

Fig. 7 is a structure diagram of PNPN in SCR. The SCR 100 has a P + emitter 86 connected to VDD, an N-well 90, a P-substrate 20, and an N + source 34 connected to an IO pad, forming a PNPN SCR structure. The P-substrate 20 is biased to VSS by P + tap 84, while the N-well 90 is biased to VDD by N + tap 92. However, the large resistivity of the P-substrate 20 and N-well 90 causes a voltage gradient to be created when the trigger current flows, turning on the pn junction.

The gate 30 forms a trigger transistor that causes current to flow through a channel in the p-substrate 20 from the N + source 34, through the channel to a connecting N + drain 38 (not shown), the connecting N + drain 38 being connected to the N-well 90. The gate 30 causes a trigger current to be injected into the N-well 90. This injected trigger current causes a voltage gradient across the N-well 90, turning on the pn junction, triggering SCR operation and discharge current flow.

Fig. 8 is a vertical cross-section of a FinFET process. Fin 2 is formed over the surface of a substrate that includes p-substrate 20 and N-well 90. N + and P + diffusion regions are formed in fin 2 above the substrate, and N-well 90 and P-substrate 20 are formed in the substrate.

The fins 2 extend up and down in the plane of fig. 8. Only a small cross-section of the fin 2 is shown in fig. 8. The vertical section 120 is perpendicular to the length of the fin and cuts through the fin as a cross-section.

An N + source 34 is formed in fin 2 near the center and connected to the IO pad. P + emitter 86 and N + tap 92 are formed in the other fin 2 above N-well 90 and are connected to VDD. A P + tap 84 is formed in the other fin 2 above the P-substrate 20 and connected to VSS.

Fig. 9 is a horizontal cross section through a FinFET trigger transistor. The horizontal section 110 is parallel to the length of the fin. In fig. 9, a horizontal section 110 cuts through one long fin and two isolated partial fins. During the manufacturing process, fin 2 may be all the same fin, and then a portion is cut or etched to form 3 portions of the fin. The end fin 2 is implanted with P + dopant to form a P + tap 84 that biases the P-substrate 20 to VSS. The central fin 2 has four gates 30, 32, which may be polysilicon, surrounding the top and upper sides of the fin. Gates 30, 32 are connected to VSS.

An N + source 34 is formed in fin 2 between gates 30, 32 and is connected to the IO pad. An end N + drain 36 is formed at the end of the central fin 2 adjacent the gate 32. A connecting N + drain 38 is formed on the central fin 2 between the gates 30. An N-well 90 is located below the central portion connecting the N + drains 38 and a p-substrate 20 is located below the end connecting the N + drains 38.

The trigger current flows along the length of the central fin 2 from the N + source 34 under the gate 30 to the connecting N + drain 38 and from the N + source 34 under the gate 32 to the terminal N + drain 36. The terminal N + drain 36 contacts the N-well 90.

Fig. 10 shows a FinFET transistor used to trigger SCR. Fin 2 may be formed on p-substrate 20 by epitaxial growth, etching of a thicker p-substrate 20, deposition, or a combination of any of the methods. The substrate may be a silicon substrate or may be an insulator used for a silicon-on-insulator (SOI) process. The gate oxide 60 under the gate 30 may be an oxide, such as hafnium oxide (HfO)₂) And may be a composite of several layers, e.g. formed on silica SiO₂HfO over a layer₂A layer, or various other advanced gate oxides. The exact cross-sectional profile may be idealized as shown in the figuresAnd a simplified cross section.

Fin 2 is made of relatively light p-type doped silicon. A gate 30 is then formed over the middle portion of the fin and a gate oxide 60 is formed between the gate 30 and the fin. Gate 30 is wound around fin 2.

Once gate 30 is formed, N-type dopant ions can be implanted into fin 2 using ion implantation to form N + source 34 adjacent gate 30 and an N + region connecting N + drain 38. When the energy of the ion implantation is high enough, the implanted ions may reach the p-substrate 20 to form N + regions 94, 96 in the p-substrate 20 and in the N + source 34 and connecting N + drain 38 in fin 2. Alternatively, lower energy ions may be implanted into fin 2 and then diffused into p-substrate 20 to form N + regions in fin 2 and p-substrate 20. This deeper N + implant than normal may improve the characteristics of the hybrid device.

The N-well 90 formed in the p-substrate 20 may be connected to the N + drain 38 by the N + region 96 or by direct contact. N + regions 94, 96 may extend up and down in the plane of fig. 10, connecting the N + regions in adjacent parallel fins together.

Fig. 11 shows a FinFET process ESD SCR structure with vertical trigger and discharge paths. The P + emitter 86 is formed from a plurality of parallel fins 2, each fin 2 being implanted with P +. Similarly, an N + tap 92 is formed by a plurality of parallel fins 2, all implanted with N +. Each P + tap 84 is formed by a plurality of parallel fins 2, wherein P + is implanted into the fins 2. The parallel fins 2 in N + tap 92 are electrically connected together by diffusing N + region 96 into N-well 90 under fin 2. Likewise, all fins 2 in P + emitter 86 are connected together by a P + diffusion region under fin 2 that diffuses away from fin 2 to form a larger P + region under all fins 2 in P + emitter 86. Other adjacent and parallel fins 2 in other regions are likewise connected together by diffusion under the fins and out the sides of the fins, or by metal lines and contacts or vias.

The gates 30, 32 may be polysilicon lines that span multiple parallel fins 2, forming MOS transistors between the N + source 34 and N + drain 36, 38 in each parallel fin 2. The connecting N + drain 38 has a plurality of parallel fins 2 that are connected to two gates 30, respectively. The openings in the N-well 90 form islands of the p-substrate 20 that surround and underlie the transistors with their gates 30, 32 intersecting between the N + source 34 and the N + drains 36, 38.

The current flowing through these trigger transistors formed by gates 30, 32 flows in a horizontal direction, along the direction of each parallel fin 2 that intersects gate 30. The trigger current is along or parallel to the horizontal cross section 110.

The PNPN SCR structure is formed by P + emitter 86, N-well 90, P-substrate 20 and fin 2 in N + source 34. This is a vertical configuration because current flows primarily in a vertical direction, either along vertical section 120 or parallel to vertical section 120. The discharge current flows mainly in the substrate, not along the long side direction of the fin 2. The discharge current flows through fin 2 to metal contacts (not shown) on the fin, and does not have to flow along the length of the fin when the contacts are closely spaced.

Since the diffusion area in the substrate is large, a large discharge current can flow in the vertical direction parallel to the vertical cross section 120, perpendicular to the fins 2. The smaller trigger current flows horizontally along the long dimension of fin 2, parallel to the horizontal cross section 110 through the transistor. Multiple parallel fins 2 increase the available trigger current through the channel in fin 2 under gate 30.

Fig. 12 is another SCR for a twin well process. P and N diffusions and regions are reversed. The N + tap 85 is connected to an N-well 91 forming a P-channel transistor with gates 30, 32 cross-adjacent to the P + source 35, end P + drain 37, and connecting N + drain 39. An N + emitter 87 and a P + tap 93 are formed on the P-well 91.

Fig. 13 shows an SCR device with parallel diodes for bi-directional ESD protection. A diode in parallel with the SCR can provide ESD pulse protection in the opposite direction. A p-diode may be connected between the IO pad and VDD. A P + diode region 142 and an N + diode region 144 are formed outside the P + emitter 86 and the N + tap 92. P + diode region 142 is connected to the IO pad, while N + diode region 144 is connected to VDD. The remaining SCR structures are as described previously with respect to fig. 3-4. While the p-diode conducts from the IO pad to VDD, the SCR conducts from VDD to the IO pad.

Fig. 14 is an electrical diagram of an SCR having the p-diode of fig. 13. The P + diode region 142 is connected to the IO pad and the N + diode region 144 is connected to VDD. When a positive ESD pulse raises the IO pad above VDD, the p-diode conducts from the IO pad to VDD.

A negative ESD pulse below VSS turns on the trigger device of gate 30, injecting carriers into N-well 90. The voltage gradient formed across the N-well 90 turns on the pn junction between the P + emitter 86 and the N-well 90 turning on the SCR PNP device. This current will be self-sustaining when the NPN device is also on. The SCR discharge current flows from VDD to the IO pad.

Fig. 15 shows the gate triggering of the SCR. Clamp 150 detects VDD or another input below VSS, indicating a negative ESD event. Clamp 150 then drives trigger signal TRIG high, driving gates 30, 32 high to turn on their transistors. The trigger current flows from the IO pad through the N + source 34, through the transistor gate to the connecting N + drain 38, and the trigger current is injected into the N-well 90, triggering the SCR discharge. When TRIG is applied to the gates 30, 32 instead of VSS, the trigger transistor will turn on faster and more fully because the voltage of TRIG is higher than VSS when the clamp 150 detects an ESD event. The clamp 150 may be implemented using various circuits, such as a capacitor between TRIG and VDD, and a leakage transistor between TRIG and VSS. The clamp 150 may be an RC gate trigger, a diode chain, or a resistance detection circuit, to name a few examples. Many alternative clamping circuits may be substituted.

Alternative embodiments

Several other embodiments are also contemplated by the inventors. For example, the P + taps 84 may be separate as shown in FIG. 3, or may be combined into a ribbon or even a ring. The P + tap 84 may surround the SCR device on all four sides rather than just the right as shown in fig. 3. The trigger device may be an array or replica, for example a structure of repeating gates 30, 32 with an N + source 34 between each pair of gates 30, 32. Other islands of P-substrate 20 may be arranged on the left side of fig. 3, each island having a gate 30 and a gate 32 with an N + source 34 connected to the IO pad between them. The four gates 30, 32 of fig. 3 may be arranged or repeated on the left side of fig. 3, with each pair of islands of p-substrate 20 having one connecting N + drain 38 therebetween and each pair having two terminal N + drains 36, or the terminal N + drains 36 may be converted to connect the N + drains 38 by connecting adjacent terminal N + drains 36 to each other. Other regions such as the P + emitter 86 and the N + tap 92 may also be extended to the left to achieve a larger (wider) SCR structure. The horizontal trigger structures of gates 30, 32 in an island of P-substrate 20 having N + regions 34, 36, 38 may also be aligned in the y-direction with another P + emitter 86 stripe between each aligned horizontal instance of gates 30, 32 in an island of P-substrate 20. When the trigger devices and islands along horizontal cross-section 110 are arranged twice in the vertical direction (y), vertical cross-section 120 may have, from top to bottom, an N-well 90, an N + tap 92, an N-well 90, a P + emitter 86, an N-well 90, one island of P-substrate 20 with an N + source 34 in between, an N-well 90, another P + emitter 86, another island of P-substrate 20 with an N + source 34 in between, an N-well 90, a P + emitter 86, an N-well 90, an N + tap 92, an N-well 90.

The device can be simplified by deleting gate 32 and deleting terminal N + drain 36. The device can be further simplified by having only one island of p-substrate 20 and only one gate 30. The N + source 34 terminates within the island of the p-substrate 20 and is connected to the IO pad, while the connecting N + drain 38 will extend across the island of the p-substrate 20 and into the N-well 90 to form a well contact to inject charge.

There may be only one p-substrate 20 island instead of the 2 islands shown in fig. 3. Additional islands may also be added. A void may be placed in the middle of the connecting N + drain 38 rather than being continuous between the two islands.

The number of parallel FinFET fins within N + source 34 may be 5 or other numbers depending on design rules and layout and the required trigger current. Some regions may have more fins and be wider than other regions. The spacing between the regions may vary and depend on process design rules and may be tailored to the desired discharge and triggering characteristics of the discharge and trigger device. Diffusion regions of different horizontal widths, such as N + source 34, may be used. Gates of different channel lengths can be used to adjust the trigger voltage and dc leakage. An unbalanced number of fins may be provided between the N + source 34 and the N + drains 36, 38 to increase robustness. Various parasitic capacitances may be present. The layout and geometry of the ESD device can affect its performance.

The P + and N + diffusions in the substrate and the defined boundary between the N-well 90 and the P-substrate 20 region may extend down to the substrate or up to the fin. As shown in fig. 8-9, the boundary need not be precisely at the fin-substrate boundary. The N + or P + regions on the separate but parallel fins may be connected by lateral diffusion from the N + regions 94, 96 or similar P + regions under the fins, or may be electrically connected by direct implantation of dopants into the substrate between adjacent fins, particularly when the adjacent fins are spaced far apart.

Terms such as upper, lower, above, below, horizontal, vertical, inside, outside, and the like are relative and are not intended to limit the present invention to a particular angle depending on the point of view. The device can be rotated so that vertical is horizontal and horizontal is vertical, and thus these terms are dependent on the viewer. One line or direction may be considered vertical and the other line or direction may be considered horizontal, as long as the two directions are substantially perpendicular to each other.

The gates 30, 32 are shown as small rectangles, but may have various shapes, and may be interconnected on the gate or polysilicon layer or by contact with a metal layer. The gates 30, 32 may be connected to VSS by these metal-to-metal contacts, which are not shown. The gates 30, 32 may also be floating or may be capacitively coupled to a trigger or supply node. The gates 30, 32 may be standard polysilicon, or various other gate materials. The oxide under the gates 30, 32 may be gate oxide, or may be thicker field oxide or isolation oxide, or a combination of both, such as thick oxide near the well boundary and thin gate oxide near the P +, N + regions or near the fins. The gate oxide may be replaced with shallow trench isolation or oxide to allow a deeper discharge path. A gate may be added extending across the well boundary between the p-substrate 20 and the N-well 90.

Various materials may be used. The substrate 20 may be silicon, or may be silicon germanium, or may be other compounds such As Ga-As, and various dopants may be added. Also, the N + fin and the P + fin may be made of the same material as the P-type substrate 20, or may be a different material such as SiGe and may have different dopants in different concentrations or distributions. Although the dopant concentration tends to vary within a region, the dopant concentration may still be considered relatively constant as compared to the rapid variation of the dopant concentration near the boundaries of the region.

The substrate, p-substrate 20, is substantially planar, although its upper surface may vary due to features etched into the top surface. The fin structures are substantially perpendicular to the plane of the substrate. The sidewalls of the fins may be slightly sloped, perhaps within 20 degrees of normal to the substantially planar surface of the substrate. The centerline between the two sidewalls may be nearly vertical, not more than 20 degrees perpendicular to the plane of the substrate.

The semiconductor process used to fabricate the finfets may have a number of variations. The VDD supply voltage may be 1.8 volts or other values. These alternatives may be combined in various ways, either alone or in other combinations.

Although an N-well 90 in a P-type substrate 20 has been described, a deep P-well in an N-type substrate may be used instead, or a double or multiple well process may be used. Various alternative transistor technologies may be added, such as bipolar or BiCMOS.

Although described with respect to current flow and operation, these are theoretical and the theory may be incomplete or even incorrect. Regardless of the physical mechanism and theoretical explanation, this structure does provide protection against ESD pulses. Especially for small devices, the current may flow in an unusual manner and use mechanisms that have not been well studied and understood.

Currents may be considered perpendicular or orthogonal to each other even when they are not exactly 90 degrees between them, such as when they are within 10% or 20% of 90%. The current itself may be spread or gathered at different locations and thus the current may not flow in a straight line, or some of the current may flow in a straight line, but the edge of the current flow may be curved or curved around obstacles such as the edge of the spreading region. The current may flow in different planes but still be considered perpendicular or orthogonal. For example, current flowing through a FinFET transistor flows in a fin above the substrate surface, while a discharge current flows in the substrate below the fin, except for a small area, up through the P + or N + fin and out the metal contact to an IO pad, VDD, VSS, or some other node. Thus, the flow direction of the current is simplified and averaged, and end point connections, such as contacts to external metal lines and edge and boundary effects, can be ignored.

Cutouts for diffusion regions and other areas may be used. Other shapes and physical layouts may be substituted, such as staggered fingers. The layout may merge the isolated N-well with the floating N-well such that they are both an interconnected N-well. For example, the wells or substrate regions may be merged together by forming a ring or doughnut shape (when the layout is viewed from above).

The device may be implemented using n-channel, p-channel or bipolar transistors or junctions within these transistors. A capacitor may be added to the resistor to provide R-C time delay or more complex circuitry such as active flip-flop circuitry may be added. In some embodiments, high voltage transistors may be used instead of low voltage transistors with appropriate bias conditions. The gate length may be increased to provide better protection from damage.

Different sized transistors, capacitors, resistors, and other devices may be used, and various layout arrangements may be used, such as multi-pin, ring, donut, or irregularly shaped transistors. Additional taps, guard rings, transistors, and other components may be added. The power supply node may be a common-discharge line (CDL) that is normally floating, rather than a power line. While a simple inversion of the core transistors 22, 24 has been shown, more complex gates and interconnects may drive the internal nodes, with several internal nodes connected to different input or output pads. The input/output pads may be connected to input buffers, test scan logic, and other circuitry. Multiple power supplies may be used.

The P and N wells may be reversed and NPNP ESD devices may be used instead of PNPN ESD devices. Deep P-wells or deep N-wells may be used. Some embodiments may use additional deep N + or P + implant regions, or the location and depth of the implant regions may be shifted. The final profile and shape of the various layers may vary depending on the process used. In particular, deeper layers may be shifted with respect to the mask layout. In addition, the mask edges and the final process boundaries may vary from process step to process step.

The ESD device may be shaped differently, such as having a more rounded bottom or field oxide boundary. The protective ring may be continuous or have openings or cutouts for various reasons. P + and N + guard rings may be used. The P + and N + guard rings may be electrically connected together so that they float or are connected to a fixed voltage, such as power or ground, or may be connected to different voltages, such as connecting the P + guard ring to ground and the N + guard ring to power. The voltage bias to the guard ring can be actively switched or multiplexed for various operating modes and conditions.

Additional leakage devices, such as resistors and small transistors, may be added. Depending on the process used and the device dimensions, parasitic capacitances and resistances may be used for some components.

The ESD protection circuit may be combined with other input protection circuits, such as power clamp circuits, other pad protection circuits, or series resistor protection circuits for the input buffer gates. Grounded gates and thick oxide protection transistors and diodes may also be added at various points to enhance ESD protection. One, two or four ESD structures may be added on each I/O pin, or only on the input pins.

Both thick oxide transistors and thin oxide transistors may be protected by power clamps and ESD protection devices. Alternatively, several power clamps with different combinations of transistors and supply voltages may be used. There may be only one ESD protection device per pad, two ESD protection devices per pad, or four ESD protection devices per pad, as shown in fig. 1. The anode and cathode (a and K) nodes may be reversed to exchange protection directions.

Bias, VDD, and voltage values may vary due to process, temperature, and design differences. The snapback or punch-through voltage may vary with process, temperature, and the precise geometry of the transistor. Although the operational descriptions have been given based on theoretical understanding of the physical process, these theoretical descriptions may be incorrect. Second and third order effects may also be present. Under different conditions, various mechanisms may lead to breakdown and conduction.

For some ESD tests and conditions, the large output driver transistor also acts as a large diode. For example, when an ESD pulse is applied to the I/O pad and the power supply pad, a positive ESD pulse turns on the parasitic p-n drain-substrate junction of the drain of the large p-channel drive transistor. The n-type substrate or well of the p-channel drive transistor is typically connected to an I/O power supply. Thus, the p-n junction is forward biased by a positive ESD pulse. Although output pads have been described, other connection techniques may be substituted, such as ball-grid-array (BGA), flip-chip, etc., and the term pads is considered to apply to all such balls, pads, lands, etc. for external connection.

Likewise, a negative ESD pulse may turn on the parasitic n-p drain-substrate junction of the drain of the large n-channel drive transistor when the ESD pulse is applied to the I/O pad and the ground pad. The p-type substrate or well of the n-channel drive transistor is typically connected to I/O ground. Thus, the p-n junction is forward biased by a negative ESD pulse. Various cross-domain coupling paths and mechanisms may exist that couple an ESD pulse applied to one power domain to another power domain.

The background of the invention may contain background information related to the problem or environment of the invention rather than the prior art described in connection with others. Accordingly, the inclusion of material in the background section is not an admission of prior art by the applicant.

Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by a machine, computer, or other device, and not merely by a human being without machine assistance. The tangible results produced may include reports or other machine-generated displays on display devices such as computer displays, projection devices, audio generation devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another tangible result.

Any advantages and benefits described herein are not necessarily applicable to all embodiments of the invention. In general, when the word "means" is stated in a claim element, applicants intend for the claim element to conform to 35USC, chapter 112, paragraph 6. The word "device" is preceded by one or more words of labels. The word or words preceding the word "means" is a label intended to facilitate the recitation of claim elements, and not intended to convey a structural limitation. The means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different configurations, they are equivalent structures in that they both perform the fastening function. Claims that do not use the word "device" are not intended to comply with 35USC, chapter 112, paragraph 6. The signals are typically electronic signals, but may also be optical signals, which may be transmitted, for example, over fiber optic lines.

The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.