Memory and device comprising same

文档序号：567663 发布日期：2021-05-18 浏览：11次中文

阅读说明：本技术 一种存储器以及包括该存储器的设备 (Memory and device comprising same ) 是由不公告发明人于 2019-11-15 设计创作，主要内容包括：本公开涉及一种存储器以及包括该存储器的设备。该存储器可以包括在组合处理装置中,该组合处理装置还可以包括计算装置、通用互联接口和其他处理装置。所述计算装置与其他处理装置进行交互,共同完成用户指定的计算操作。存储装置分别与计算装置和其他处理装置连接,用于存储计算装置和其他处理装置的数据。本公开的方案能够广泛地应用于各种数据存储领域中。(The present disclosure relates to a memory and a device including the same. The memory may be included in a combined processing device that may also include computing devices, general purpose interconnect interfaces, and other processing devices. The computing device interacts with other processing devices to jointly complete computing operations specified by a user. The storage device is respectively connected with the computing device and the other processing devices and is used for storing data of the computing device and the other processing devices. The scheme of the present disclosure can be widely applied to various data storage fields.)

1. A memory, comprising:

at least two dies (D1-Dn), each die comprising a termination resistance (ODT1-ODTn), the at least two dies (D1-Dn) having a communication path disposed therebetween;

wherein the content of the first and second substances,

one of the at least two dies (D1-Dn) is a target die (T-D) having a termination resistance of a target termination resistance (T-ODT) and the others are non-target dies (NT-D) having termination resistances of non-target termination resistances (NT-ODT), the operating modes of the target die (T-D) including a read mode and a write mode;

the target die (T-D) sends a pulse signal to the non-target die (NT-D) through the communication path to set a non-target termination resistance (NT-ODT) of the non-target die (NT-D) to a first resistance value matching the read mode or a second resistance value matching the write mode.

2. The memory according to claim 1, wherein the non-target die (NT-D) is configured to set the non-target termination resistance (NT-ODT) to a first resistance value matching the read mode or to a second resistance value matching the write mode in response to receiving the pulse signal from the target die (T-D).

3. The memory according to claim 1 or 2,

the read mode includes a read mode entry time (Tr1), a read mode data transfer start time (Tr2) and a read mode data transfer end time (Tr 3);

the write mode includes a write mode entry time point (Tw1), a write mode data transfer start time point (Tw2), and a write mode data transfer end time point (Tw 3); and

the pulse signals include a first pulse signal (P1) and a second pulse signal (P2).

4. The memory according to claim 3, wherein,

the first pulse signal (P1) is issued after the read mode entry time (Tr1) and before a read mode data transfer start time (Tr2) so that the non-target termination resistance (NT-ODT) is set to the first resistance value before data transfer of the read mode starts;

the second pulse signal (P2) is issued after the read mode data transmission end point (Tr3) such that the non-target termination resistance (NT-ODT) is set to a second resistance value after the read mode data transmission ends.

5. The memory according to claim 3, wherein,

the second pulse signal (P2) is issued after the write mode entry time point (Tw1) and before a write mode data transfer start time point (Tw2), so that the non-target termination resistance (NT-ODT) is set to a second resistance value before the start of data transfer of the write mode.

6. The memory according to claim 3, wherein,

the first pulse signal (P1) is issued after the write mode entry time point (Tw1) and before a write mode data transfer start time point (Tw2), so that the non-target termination resistance (NT-ODT) is set to the second resistance value before the start of data transfer of the write mode;

the second pulse signal (P2) is issued after the write mode data transfer end time point (Tw3) such that the non-target termination resistance (NT-ODT) is set to a first resistance value after the start of the write mode data transfer.

7. The memory according to any one of claims 1 to 6, wherein the resistance value of the target termination resistance (T-ODT) is set to be not lower than the resistance value of the non-target termination resistance (NT-ODT).

8. The memory of claim 7, wherein the target termination resistance (T-ODT) is turned off.

9. The memory according to any one of claims 1 to 8, wherein in the read mode, the first resistance value of the non-target termination resistance (NT-ODT) is set to not less than 60 ohm.

10. The memory of claim 9, wherein the non-target termination resistance (NT-ODT) is set to off in the read mode.

11. The memory according to any of claims 1-10, wherein in the write mode, the second resistance value of the non-target termination resistance (NT-ODT) is set to not more than 120 ohm.

12. The memory of claim 11, wherein the second resistance value of the non-target termination resistance (NT-ODT) is set to any one of 240/N ohm, where N is any one integer from 2-10.

13. The memory of any one of claims 1-12, wherein the communication path is a single bidirectional communication path.

14. A memory as recited in any one of claims 1-12, wherein the communication paths are two opposite unidirectional communication paths.

15. The memory according to any of claims 1-14, further comprising a Mode Register (MR) in which a parameter list is stored, such that the memory is capable of setting the at least two dies (D1-Dn) according to the parameter list.

16. The memory according to any of claims 1-15, further comprising a memory controller connected with the at least two dies (D1-Dn) and configured to control a resistance value of a target termination resistance (T-ODT) of the target die (T-D).

17. The memory of claim 16, wherein the controller is further configured to control a resistance value of a non-target termination resistance (NT-ODT) of the non-target die (NT-D).

18. The memory of any one of claims 1-14, wherein the memory is a low power dual data rate memory (LPDDR).

19. A package comprising a memory according to any of claims 1-18, wherein the communication path is arranged inside the package directly connecting the at least two dies (D1-Dn).

20. A package comprising a memory according to any of claims 1-18, wherein external terminals are provided outside the package, the communication path connecting at least two dies (D1-Dn) through the external terminals.

21. Processor system comprising a processor chip and a memory according to any of claims 1-18, said processor chip being connected to at least two dies (D1-Dn), wherein said processor chip sets the resistance value of said target termination resistance (T-ODT), said non-target termination resistance (NT-ODT), and/or the termination resistance of said processor chip depending on the operating mode of said target die (T-D).

22. The processor system according to claim 21, wherein the processor chip comprises a CPU chip, a GPU chip, or a SoC chip.

23. The processor system according to claim 21, wherein in a read mode, a termination resistance of the processor chip is set to not greater than 120 ohms.

24. The processor system according to claim 23, wherein the processor system is set to 240/N, where N is an integer between 2-10.

25. The processor system according to any of claims 21-24, wherein in the write mode a termination resistance of the processor system is set to off.

26. A board card, comprising:

the memory of any one of claims 1-18; or

A package according to claim 19 or 20; or

The processor system of any one of claims 21 to 25.

27. An electronic device, comprising:

the memory of any one of claims 1-18; or

A package according to claim 19 or 20; or

The processor system of any one of claims 21-25; or

A card as in claim 26.

28. A memory method performed on a memory device, the memory device comprising at least two dies (D1-Dn), each die comprising a termination resistance (ODT1-ODTn), the at least two dies (D1-Dn) having a communication path arranged therebetween; wherein one of the at least two dies (D1-Dn) is a target die (T-D) having a termination resistance of a target termination resistance (T-ODT), and the others are non-target dies (NT-D) having termination resistances of non-target termination resistances (NT-ODT), and the operating modes of the target die (T-D) include a read mode and a write mode;

the method comprises the following steps:

sending a pulse signal through the target die (T-D) to the non-target die (NT-D) to set a non-target termination resistance (NT-ODT) of the non-target die (NT-D) to a first resistance value matching the read mode or a second resistance value matching the write mode.

29. The memory method according to claim 28, wherein, at the non-target die (NT-D), the non-target termination resistance (NT-ODT) is set to a first resistance value matching the read mode or to a second resistance value matching the write mode in response to receiving the pulse signal from the target die (T-D).

30. The storage method according to claim 28 or 29,

the read mode includes a read mode entry time (Tr1), a read mode data transfer start time (Tr2) and a read mode data transfer end time (Tr 3);

the write mode includes a write mode entry time point (Tw1), a write mode data transfer start time point (Tw2), and a write mode data transfer end time point (Tw 3); and

the pulse signals include a first pulse signal (P1) and a second pulse signal (P2).

31. The storage method as claimed in claim 30,

issuing the first pulse signal (P1) before a read mode data transfer start time (Tr2) after the read mode entry time (Tr1) such that the non-target termination resistance (NT-ODT) is set to the first resistance value before data transfer of the read mode starts;

the second pulse signal (P2) is issued after the read mode data transmission end time point (Tr3) such that the non-target termination resistance (NT-ODT) is set to a second resistance value after the read mode data transmission ends.

32. The storage method as claimed in claim 30,

the second pulse signal (P2) is issued before a write mode data transfer start time point (Tw2) after the write mode entry time point (Tw1) such that the non-target termination resistance (NT-ODT) is set to a second resistance value before the start of data transfer of the write mode.

33. The storage method as claimed in claim 30,

issuing the first pulse signal (P1) before a write mode data transfer start time point (Tw2) after the write mode entry time point (Tw1) such that the non-target termination resistance (NT-ODT) is set to the second resistance value before data transfer of the write mode starts;

34. The memory method according to any one of claims 28 to 33, wherein the resistance value of the target termination resistance (T-ODT) is set to not lower than the resistance value of the non-target termination resistance (NT-ODT).

35. The memory method according to claim 34, wherein the target termination resistance (T-ODT) is turned off.

36. The memory method according to any one of claims 28 to 35, wherein the first resistance value of the non-target termination resistance (NT-ODT) is set to not less than 60ohm in the read mode.

37. The memory method of claim 36, wherein the non-target termination resistance (NT-ODT) is set to off in the read mode.

38. The memory method according to any of claims 28-37, wherein in the write mode, the second resistance value of the non-target termination resistance (NT-ODT) is set to not more than 120 ohm.

39. The memory method of claim 38, wherein the non-target termination resistance (NT-ODT) is set to any one of 240/N ohm, where N is any one integer from 2 to 10.

40. The storage method of any of claims 28-39, wherein the communication path is a single bidirectional communication path.

41. The storage method of any of claims 28-39, wherein the communication paths are two opposite unidirectional communication paths.

42. Method of storing according to any of claims 28-41, the memory further comprising a Mode Register (MR) in which a parameter list is stored, such that at least the at least two dies (D1-Dn) can be set according to the parameter list.

43. The memory method according to any of claims 28-42, further comprising controlling a resistance value of a target termination resistance (T-ODT) of the target die (T-D) by a memory controller connected with the at least two dies (D1-Dn).

44. The memory method of claim 43, further comprising controlling, by the controller, a resistance value of a non-target termination resistance (NT-ODT) of the non-target die (NT-D).

45. The storage method of any of claims 28-44, wherein the memory is a low power dual data rate memory (LPDDR).

Technical Field

The present disclosure relates to the field of memories, and more particularly to the field of DDR memories.

Background

In the terminal resistance (ODT) control method of Low Power double Data Rate (LPDDR 4), there is a unique operation mode that a Die (Die) accessed at the time of writing and a System On Chip (SOC) accessed at the time of reading can select to turn On ODT or turn off ODT.

In the ODT control method of LPDDR5, however, there is a more resilient operation of selecting whether to turn on ODT or turn off ODT during a write, whether on a die that is accessed or a die that is not accessed. The main reason for this flexible operation mode is that as the operation speed of LPDDR5 gradually increases to 6.4Gbps, the Integrity of Signal (SI) and the quality of Signal transmission on the channel gradually deteriorate, so to obtain better Signal quality, LPPDR develops that in a two-die architecture, ODT can be selectively turned on and off for the accessed and unaccessed die, respectively, and different ODT values can be set. However, this operation, which seems to solve the signal quality of the writing process, has the following disadvantages: during the transition from write to read, the die that is not being accessed cannot be turned off ODT and thus tends to affect the signal quality of the read process. The final setting method cannot use the ODT setting value with the best signal quality due to the defect, which results in poor signal quality and no increase in operation speed.

Disclosure of Invention

One objective of the present disclosure is to solve the problem of the prior art that the data access speed in the memory cannot be increased continuously.

According to a first aspect of the present disclosure, there is provided a memory comprising: at least two dies D1-Dn, each die comprising termination resistances ODT1-ODTn, the at least two dies D1-Dn having a communication path disposed therebetween; one of the at least two dies D1-Dn is a target die T-D, the termination resistance of the target die T-D is a target termination resistance T-ODT, the other dies are non-target dies NT-D, the termination resistance of the non-target dies NT-D is a non-target termination resistance NT-ODT, and the working mode of the target die T-D comprises a reading mode and a writing mode; the target die T-D sends a pulse signal to the non-target die NT-D through the communication path to set a non-target termination resistance NT-ODT of the non-target die NT-D to a first resistance value matching the read mode or a second resistance value matching the write mode.

According to a second aspect of the present disclosure, there is provided a package comprising a memory as described above, wherein the communication path is provided inside the package directly connecting the at least two dies D1-Dn.

According to a third invention of the present disclosure, there is provided a package comprising the memory as described above, wherein an external terminal is provided outside the package, and the communication path connects at least two dies D1-Dn through the external terminal.

According to a fourth aspect of the present disclosure, there is provided a processor system comprising a processor chip and a memory as described above, the processor chip being connected with at least two dies D1-Dn, wherein the processor chip sets the target termination resistance T-ODT, the resistance value of the non-target termination resistance NT-ODT, and/or the termination resistance of the processor chip according to a difference in an operation mode of the target die T-D.

According to a fifth aspect of the present disclosure, a board card is provided, which includes: a memory as described above; or a package as described above; or include a processor system as described above.

According to a sixth aspect of the present disclosure, there is provided an electronic device comprising: a memory as described above; or a package as described above; or a processor system as described above; or a board card as described above.

According to a seventh aspect of the present disclosure, there is also provided a memory method performed on a memory device, the memory device comprising at least two dies D1-Dn, each die comprising a termination resistance ODT1-ODTn, the at least two dies D1-Dn having a communication path disposed therebetween; one of the at least two dies D1-Dn is a target die T-D, the termination resistance of the target die T-D is a target termination resistance T-ODT, the other dies are non-target dies NT-D, the termination resistance of the non-target dies NT-D is a non-target termination resistance NT-ODT, and the working mode of the target die T-D comprises a reading mode and a writing mode; the method comprises the following steps: sending a pulse signal to the non-target die NT-D through the target die T-D to set a non-target termination resistance NT-ODT of the non-target die NT-D to a first resistance value matching the read mode or a second resistance value matching the write mode.

The technical scheme provided by the disclosure has the beneficial effect that the data transmission speed rate of the memory can be improved.

Drawings

The foregoing and other objects, features and advantages of exemplary embodiments of the present disclosure will be readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the disclosure are illustrated by way of example and not by way of limitation, and like or corresponding reference numerals indicate like or corresponding parts and in which:

FIG. 1a shows the basic architecture of a conventional LPDDR5 memory in read mode.

FIG. 1b shows the basic architecture of a conventional LPDDR5 memory in write mode.

FIG. 2A shows a timing diagram for a write mode in the LPDDR5 specification (Item #1854.99A) according to the present disclosure.

FIG. 2b illustrates a timing diagram for the read mode in the LPDDR5 specification (Item #1854.99A) according to the present disclosure.

FIG. 3 illustrates a schematic diagram of a memory in accordance with an aspect of the present disclosure.

Fig. 4a and 4b show schematic diagrams of communication paths according to an embodiment of the present disclosure.

Fig. 5a and 5b show schematic diagrams of a communication path according to another embodiment of the present disclosure.

FIG. 6 shows a schematic diagram of a memory according to another embodiment of the present disclosure.

Fig. 7a to 7d show simple timing diagrams of pulse signals according to an embodiment of the present disclosure.

Fig. 8a to 8d show various connection relationships between a plurality of dies.

FIG. 9 shows a schematic block diagram of a processor system according to another embodiment of the present disclosure.

FIG. 10 illustrates a flow chart of a storage method performed on a memory according to another aspect of the disclosure.

FIG. 11 is a schematic diagram of a combined processing device according to one aspect of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is to be understood that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.

It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.

As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted depending on the context to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".

FIG. 1a shows the basic architecture of a conventional LPDDR5 memory in read mode.

In FIG. 1a, die D1 is in operation, e.g., in read mode, and thus die D1 may be referred to as target die T-D; and die D2 is inactive, so die D2 may be referred to as non-target die NT-D. The SoC is accordingly also in operation. It is to be understood that the target die T-D and the non-target die NT-D may vary, and that die D1 is denoted as target die T-D and die D2 is denoted as non-target die NT-D for exemplary reasons only, without any limitation as to the functionality of die D1 and D2.

In the read mode shown in FIG. 1a, the receive terminal Rx1 in the target die T-D is in a non-operational state and the transmit terminal Tx1 is in an operational state. In fig. 1a, the input terminals and the output terminals in the non-operating state are set to gray representation for the convenience of understanding and reading.

The transmission terminal Txs in the system-on-chip SoC is in a non-operational state, while the reception terminal Rxs in the SoC is in an operational state.

In non-target die NT-D, both its transmit terminal Tx2 and receive terminal Rx2 are in a non-operative state.

As further shown in fig. 1a, in the read mode, the termination resistance (referred to herein as T-ODT) in the target die T-D is turned off (which may also be understood as the termination resistance having an infinite resistance value), while the SoC-ODT in the system-on-chip SoC is active.

FIG. 1b shows the basic architecture of a conventional LPDDR5 memory in write mode.

In FIG. 1b, die D1 is in an active state, e.g., in write mode, so we still refer to die D1 as target die T-D; while die D2 is inactive, we will still refer to die D2 as non-target die NT-D. The SoC is accordingly also in operation.

In the write mode shown in FIG. 1b, the receive terminal Rx1 in the target die T-D is active and the transmit terminal Tx1 is inactive. In fig. 1b, the input terminals and the output terminals in the non-operating state are also set to gray representation for the convenience of understanding and reading.

The transmit terminal Txs in the system-on-chip SoC is in an active state while the receive terminal Rxs in the SoC is in an inactive state.

In non-target die NT-D, both its transmit terminal Tx2 and receive terminal Rx2 are in a non-operative state.

As further shown in FIG. 1b, in the write mode, the termination resistance (referred to herein as the T-ODT) in the target die T-D is closed, while the SoC-ODT in the system-on-chip SoC is open and inactive.

As can be seen from FIGS. 1a and 1b, the non-target termination resistance NT-ODT of the non-target die NT-D does not change with the operation mode of the target die T-D because the operation mode of the target die T-D is not directly known, i.e., the non-target termination resistance NT-ODT of the non-target die NT-D does not change whether the target die T-D is in the read mode or the write mode.

FIG. 2A shows a timing diagram for a write mode in the LPDDR5 specification (Item #1854.99A) according to the present disclosure.

In FIG. 2A (see also diagram 164 of Item #1854.99A of the LPDDR5 specification), in the non-target ODT enabled mode, the ODT timing (ODTLon and ODTLoff) is referenced to the WL after the write command, and the ODT value in the target die may be updated in the tODton. Max time slot, the target ODT value should be restored to the preset non-target ODT value after the write operation.

FIG. 2b illustrates a timing diagram for the read mode in the LPDDR5 specification (Item #1854.99A) according to the present disclosure.

In FIG. 2b (see also diagram 165 of Item #1854.99A of the LPDDR5 specification), in the non-target ODT enabled mode, the ODT timing (ODTLoff _ RD/RD _ DQ/RDQS) references the RL after the read command and the ODT value in the target die may be disabled in the tODT _ RDoff, max slot. After a read operation, the disabled ODT should revert to a predetermined, non-target ODT value in the tdod _ RDon, max time slot.

In fig. 2a and 2b above, ODT _ Rank0 may represent a target termination resistance, T-ODT, for target die T-D, and ODT _ Rank1 may represent a non-target termination resistance, NT-ODT, for non-target die NT-D. Which will be further described later.

As can be seen from FIGS. 1a, 1b, 2A and 2b, in the specification of LPDDR5 (Item #1854.99A), the non-target termination resistance NT-ODT in the non-target die NT-D is always in an active state, in which case the effect is not great at low speed data transfer, but the effect of the non-target termination resistance NT-ODT in the non-target die NT-D increases gradually as the data transfer rate increases. In addition, in the existing specification, the target die T-D does not have any influence on the non-target die NT-D, and the non-target die NT-D cannot directly acquire the working state of the target die T-D.

FIG. 3 illustrates a schematic diagram of a memory in accordance with an aspect of the present disclosure.

As shown in FIG. 3, according to one aspect of the present disclosure, a memory device is provided that includes at least two dies D1-Dn that include respective termination resistances ODT 1-OTDN.

In FIG. 3, one of the at least two dies D1-Dn is a target die T-D (e.g., die D1 is the target die), the termination resistance ODT1 of the target die T-D is the target termination resistance T-ODT, the others are non-target dies NT-D, the termination resistances of the non-target dies NT-D are the non-target termination resistances NT-ODT, and the operating modes of the target die T-D may include a read mode and a write mode.

In fig. 3, the target die T-D sends a pulse signal to the non-target die NT-D through the communication path to set the non-target termination resistance NT-ODT of the non-target die NT-D to a first resistance value matching the read mode or a second resistance value matching the write mode.

In the structure shown in fig. 1a and 1b, the target die T-D and the non-target die NT-D are in an isolated state, and when the operation mode of the target die T-D changes, the target die does not inform the non-target die NT-D, and the non-target die NT-D does not know the change of the operation mode of the target die T-D, so that the target die T-D and the non-target die NT-D do not form a good fit.

In the structure shown in fig. 3, a communication path exists between the target die T-D and the non-target die NT-D, so that after the operation mode of the target die T-D changes, the target die T-D can send a notification signal to the non-target die NT-D through the communication path, so as to notify the non-target die NT-D of the operation mode of the target die T-D, so that the non-target die NT-D can perform corresponding setting. It is to be understood that there are many ways in which the connections between the various dies may be made, and that fig. 3 is merely an example, and the particular manner in which the connections between the dies will be described in detail later.

Fig. 3 also shows an exemplary SoC chip, which includes SoC terminal resistors SoC-ODT, and which is connected to the dies D1-Dn, wherein the SoC-ODT is set to have different resistance values according to the operating mode. It should be understood that although an SoC chip is shown in fig. 3, it may alternatively be any processing unit with control function, such as a CPU chip, a GPU chip, and the like.

In connection with the description of fig. 1a and 1b, the termination resistance T-ODT in the target die T-D may be set to off (infinity) in the read mode and the termination resistance SoC-ODT of the system-on-chip SoC may be set to off (infinity) in the write mode.

According to one embodiment of the present disclosure, the non-target die NT-D may be configured to set the non-target termination resistance NT-ODT to a first resistance value matching the read mode or a second resistance value matching the write mode in response to receiving the pulse signal from the target die T-D.

The above-described communication paths are described in detail below with reference to the drawings.

Fig. 4a shows a schematic diagram of a communication path according to an embodiment of the present disclosure. According to this embodiment, the communication path is a single bidirectional communication path. For ease of description, the following description will be made with two dies, D1 and D2.

As shown in fig. 4a, pins Pin1 and Pin2 may be provided in the dies D1 and D2, respectively, and the two pins Pin1 and Pin2 are directly connected through a bidirectional path. Here, the Pin1 may be denoted as ODT _ Ctrl _ Rank0, and the Pin2 may be denoted as ODT _ Ctrl _ Rank1, which denotes that a notification signal or a control signal may be issued through the Pin.

Fig. 4b shows a schematic diagram of a communication path when 3 dies are included according to one embodiment of the present disclosure.

As shown in fig. 4b, pins Pin11 and Pin12, pins Pin21 and Pin22, and pins Pin31 and Pin32 may be provided in die D1-D3, respectively, directly connected to the above pins via a bidirectional path. Here, the pins Pin11 and Pin12 may be denoted as ODT _ Ctrl _ Rank0, the pins Pin21 and Pin21 may be denoted as ODT _ Ctrl _ Rank1, and the pins Pin31 and Pin32 may be denoted as ODT _ Ctrl _ Rank2, which means that a notification signal or a control signal may be issued through the pins.

This has the advantage that in a package comprising die D1-D3, no new connection points or terminals need to be added outside the package, thereby enabling minor modifications to be made to existing die and specifications, and thus reducing costs. In addition, with the above embodiment, only one pin needs to be added to the original die, which reduces the complexity of modifying the die.

In addition, the single bidirectional communication path is beneficial to reducing the number of pins, thereby further reducing the manufacturing procedures and reducing the chip area.

Fig. 5a shows a schematic diagram of a communication path according to another embodiment of the present disclosure. According to this embodiment, the communication paths are two opposite unidirectional communication paths.

As shown in fig. 5a, a Pin1 and a Pin3 may be provided in the die D1, and a Pin2 and a Pin4 may be provided in the die D2, respectively. One communication path may be connected from Pin1 to Pin2 and another communication path may be connected from Pin4 to Pin 3. Here, the Pin1 may be denoted as ODT _ Ctrl _ Rank0, and the Pin2 may be denoted as ODT _ Ctrl _ Rank1, which denotes that a notification signal or a control signal may be issued through the Pin.

Fig. 5b shows a schematic diagram of a communication path when 3 or more dies are included according to another embodiment of the present disclosure.

As shown in fig. 5b, a Pin11 and a Pin12 may be respectively disposed in the die D1, a Pin21, a Pin22, a Pin P23 and a Pin P24 may be respectively disposed in the die D2, and a Pin P31 and a Pin P32 may be respectively disposed in the die D3. One communication path may be connected from Pin11 to Pin21 and another communication path may be connected from Pin22 to Pin 12. Further, one communication path may be connected from Pin Pin23 to Pin Pin31, and another communication path may be connected from Pin P32 to Pin P24. Here, the Pin11 may be denoted as ODT _ Ctrl _ Rank0, the Pin21 may be denoted as ODT _ Ctrl _ Rank1, and the Pin31 may be denoted as ODT _ Ctrl _ Rank2, which means that a notification signal or a control signal may be issued or received through the Pin. Of course, after die D1, die D2, and Pin D3 are reversed in role (e.g., die D2 becomes the target die and die D1 and die D3 become non-target dies), then pins Pin22 and Pin23 may be represented as ODT _ Ctrl _ Rank0, while Pin12 and Pin31 may be represented as ODT _ Ctrl _ Rank1 and ODT _ Ctrl _ Rank2, respectively.

It is also understood that the connection between die D3 and die D1 is omitted from fig. 5b, and that the two may also be connected by a bi-directional or unidirectional communication path.

This has the advantage that in a package comprising die D1-D3, no new connection points or terminals need to be added outside the package, thus allowing minor modifications to be made on the basis of existing die and specifications, and thus reducing costs.

Further, by isolating the transmission and reception of the notification signal via the two communication paths, possible interference or collisions between the signals are reduced or eliminated.

FIG. 6 shows a schematic diagram of a memory according to another embodiment of the present disclosure.

As shown in fig. 6, the memories shown in fig. 1-5 are in one package. In the embodiment shown in fig. 6, the system-on-chip SoC is omitted for convenience of explanation.

In the package, Pin1 of die D1 is connected to terminal 1 outside the package, and Pin2 of die D2 is connected to terminal 2 outside the package. The terminals 1 and 2 may be formed as separate connection terminals outside the package so that a complete communication path may be formed when the terminals 1 and 2 are connected.

For more dies, one terminal may be provided for each die outside the package, so that when these terminals are connected, the internal dies are also connected, and a description of the package including more dies will be omitted here.

It is also to be understood that the connections between the multiple dies may not necessarily all be outside the die or all be within the die, but may be some outside the die and some inside the die.

It is to be understood that the arrangement in fig. 6 is only an example and that other numbers of terminals external to the package are possible, for example one terminal may be provided external to the package to which the bidirectional communication link is connected. In another example, two terminals may be provided external to the package, a unidirectional communication path from die D1 to die D2 passing through a first terminal, and a unidirectional communication path from die D2 to die D1 passing through a second terminal.

Further, similar to fig. 4 and 5, the pin or terminal from die D1 may be denoted as ODT _ Ctrl _ Rank0, while the pin or terminal from die D2 may be denoted as ODT _ Ctrl _ Rank 1.

Fig. 3-6 do not indicate which transmitting and receiving terminals are in an active state, which are in an inactive state, and which ODT is disconnected as in fig. 1a and 1b, but it should be understood by those skilled in the art that fig. 3-6 only show general connection conditions, and the specific operation of the components will be described in detail below.

As can be seen from the timing diagrams of fig. 2a and 2b, switching from one mode to another and completing data transmission in another mode requires a plurality of clock cycles, as shown in fig. 2a, entering WR mode between clock cycles Ta2 and Ta3, and after several clock cycles, data transmission is performed between clock cycles Td0 and Te 1. Thus, as long as the non-target termination resistance NT-ODT is set to an appropriate resistance value before data transmission, the advantageous effects intended by the present disclosure can be achieved.

Fig. 7a shows a schematic timing diagram according to an embodiment of the present disclosure.

As shown in fig. 7a, the read mode includes a read mode entry time Tr1, a read mode data transfer start time Tr2, and a read mode data transfer end time Tr 3; the write pattern includes a write pattern entry time point Tw1, a write pattern data transfer start time point Tw2, and a write pattern data transfer end time point Tw 3.

It should be immediately understood that the term "time point" mentioned above does not mean an exact time point, but may indicate a time period, for example, the read mode entry time point Tr1 may indicate that the read mode has been entered in the read mode, for example, in the timing diagram shown in fig. 2b, which may indicate a time point after the end of the RD period, for example, Ta 3. The read mode data transmission start time Tr2 may correspond to Tc3 in fig. 2b, or Td0 in fig. 2 b. Between the time points Tr2 and Tr3 is a period of data transmission. After Tr3, the data transfer in the read mode is completed, and the time point Tr3 may correspond to Te1 or Tf0 in fig. 2 b.

For the time point Tw1 in the write mode, it may correspond to the time point after the end of the WR period, for example, the time point T3a in fig. 2a, and the write mode data transmission start time Tw2 may correspond to Tc3 in fig. 2a and Td0 in fig. 2 a. Between time points Tw2 and Tw3 are periods of data transmission. After Tw3, data transfer in the write mode is completed, which time Tw3 may correspond to Te1 or Tf0 in fig. 2 a.

The pulse signals may include a first pulse signal P1 and a second pulse signal P2.

Fig. 7b shows a schematic diagram of a timing diagram according to an embodiment of the present disclosure.

As shown in fig. 7b, according to one embodiment of the present disclosure, the first pulse signal P1 is issued after the read mode entry time Tr1 and before the read mode data transfer start time Tr2, so that the non-target termination resistance NT-ODT is set to the first resistance value before the data transfer of the read mode starts; the second pulse signal P2 is issued after the end point Tr3 of the data transmission of the read mode, so that the non-target termination resistance NT-ODT is set to a second resistance value after the end of the data transmission of the read mode.

The non-target die NT-D, upon receiving the first pulse signal P1 from the target die T-D, sets the corresponding non-target termination resistance NT-ODT to a corresponding first resistance value to match the current read mode before data transmission begins; after the data transmission is finished, i.e., after the time point Tr3, the target die T-D may transmit a second pulse signal P2 to the non-target die NT-D, and since the data transmission is finished, the resistance value of the non-target termination resistance NT-ODT may be restored to the original resistance value. In other words, before the first pulse signal P1 and after the second pulse signal P2, the resistance value of the non-termination resistance NT-ODT may be maintained in the matched write mode, and between the first pulse signal P1 and the second pulse signal P2, the resistance value of the non-target termination resistance NT-ODT may be maintained in the matched read mode. Thus, when switching from the read mode to the write mode, the non-target termination resistance NT-ODT does not need to be adjusted again because its resistance value has already matched the current write mode.

The beneficial effect of the above scheme is that the above embodiment of the present disclosure can be formed only by appropriately modifying the write mode timing diagram in the current timing diagram, and the modification range of the current specification is reduced.

Fig. 7c shows a schematic diagram of a timing diagram according to yet another embodiment of the present disclosure.

In fig. 7c, the transmission timing of the first pulse signal is similar to the scheme described in fig. 7b, i.e., the first pulse signal P1 is transmitted after the read mode entry time Tr1 and before the read mode data transmission start time Tr2, so that the non-target termination resistance NT-ODT is set to the first resistance value before the read mode data transmission starts.

Unlike the scheme depicted in fig. 7b, the second pulse signal P2 is issued after the write mode entry time Tw1 and before a write mode data transfer start time Tw2, so that the non-target termination resistance NT-ODT is set to a second resistance value before the start of data transfer in the write mode.

In the embodiment depicted in fig. 7c, the timing diagram for both the read mode and the write mode is modified. The scheme has the advantages that the non-target termination resistor NT-ODT can be reliably ensured to be in the matched resistance value in the read mode and the write mode, and the times of switching the resistance value are reduced.

Fig. 7d shows a schematic diagram of a timing diagram of yet another embodiment.

As shown in fig. 7d, the first pulse signal P1 is issued after the write mode entry time Tw1 and before a write mode data transfer start time Tw2, so that the non-target termination resistance NT-ODT is set to the second resistance value before the start of data transfer of the write mode; the second pulse signal P2 is issued after the write mode data transfer end time Tw3 such that the non-target termination resistance NT-ODT is set to a first resistance value after the start of the write mode data transfer.

Similar to the embodiment of fig. 7b, the embodiment of fig. 7d only requires modification of the timing diagram of the write mode, simplifying the modification requirements for the existing standard.

As can be seen from the timing diagrams of fig. 7a to 7d, the pulse signal makes the setting of the timing diagram more flexible and various than other signals such as step signal, so that the developer can make proper adjustment to the working timing according to the actual requirement.

The non-target termination resistance NT-ODT, as well as the settings for the other termination resistances, are described in detail below in conjunction with a table.

The performance of data transmission in different resistance combinations of the termination resistance SoC-ODT of the system-on-chip SoC and the non-target termination resistance NT-ODT in the read mode is shown in table 1. It is understood that, in the read mode, the target termination resistance T-ODT may be turned off (the resistance value is infinity), or the resistance value of the target termination resistance T-ODT is set to be large enough so that the resistance value of the target termination resistance T-ODT is not lower than that of the non-target termination resistance NT-ODT.

TABLE 1

In Table 1, EW represents the eye width, DQ0-DQ7, DM10, and RDQS _ T represents the corresponding pin, respectively. As can be seen from table 1, in the read mode, when the SoC-ODT is 48ohm and the non-target termination resistance NT-ODT is turned off, the average eye width is 67.58 ps; when the Soc-ODT is 60ohm and the non-target termination resistance NT-ODT is 120ohm, the average eye width is 67.02 ps; when the Soc-ODT is 80ohm and the non-target termination resistance NT-ODT is 80ohm, the average eye pattern width is 64.09 ps; when the Soc-ODT is 120ohm and the non-target termination resistance NT-ODT is 60ohm, the average eye width is 60.01 ps; and when the Soc-ODT is turned off and the non-target termination resistance NT-ODT is 48ohm, the average eye width is 30.89 ps.

As can be seen from table 1, in the case where the target termination resistance T-ODT is set to be turned off in the read mode, the smaller the ratio of the SoC-ODT with respect to the non-target termination resistance NT-ODT, the better the Signal Integrity (SI) or the signal quality thereof, and when the resistance value of the SoC-ODT becomes gradually larger and the resistance value of the non-target termination resistance NT-ODT becomes gradually smaller, the signal quality may gradually deteriorate until the signal quality is seriously deteriorated after the SoC-ODT is turned off.

On the other hand, as can be seen from table 1, the resistance value (first resistance value) of the non-target termination resistance NT-ODT in the read mode may be set to not less than 60ohm, in which case the signal quality, although deteriorated, is still in an acceptable range. Preferably, in the read mode, the non-target termination resistance (NT-ODT) may be turned off, i.e., its resistance value is at infinity.

The performance of data transmission in write mode for different combinations of resistance values of the target termination resistance T-ODT and the non-target termination resistance NT-ODT of the target die T-D is shown in table 2. It is understood that, in the write mode, the SoC termination resistance SoC-ODT may be turned off (the resistance value is infinite), or the resistance value of the SoC termination resistance SoC-ODT is set to be sufficiently large.

TABLE 2

As can be seen from Table 2, in the write mode, when the T-ODT is 48 ohms and the non-target termination resistance NT-ODT is turned off, the average eye width is 64.97 ps; when the target termination resistance T-ODT is 60 ohms and the non-target termination resistance NT-ODT is 120 ohms, the average eye diagram width is 69.85 ps; when the target termination resistance T-ODT is 80 ohms and the non-target termination resistance NT-ODT is 80 ohms, the average eye diagram width is 71.13 ps; when the target termination resistance T-ODT is 120 ohms and the non-target termination resistance NT-ODT is 60 ohms, the average eye diagram width is 79.99 ps; and when the target termination resistance T-ODT is turned off and the non-target termination resistance NT-ODT is 48 ohms, the average eye width is 89.21 ps.

As can be seen from table 2, in the case where the SoC termination resistance SoC-ODT is set to be off in the write mode, the smaller the ratio of the target termination resistance T-ODT with respect to the non-target termination resistance NT-ODT, the worse the Signal Integrity (SI) or the signal quality thereof, and when the resistance value of the target termination resistance T-ODT becomes gradually larger and the resistance value of the non-target termination resistance NT-ODT becomes gradually smaller, the signal quality becomes gradually better; the signal quality becomes optimal when the target termination resistance, T-ODT, is turned off, rather than the target termination resistance, NT-ODT, being 48 ohms.

On the other hand, as can be seen from table 2, the resistance value (second resistance value) of the non-target termination resistance NT-ODT may be set to not more than 120ohm in the write mode. In this case, the signal quality, although not optimal, is still within an acceptable range. Thus, it is preferable that the target termination resistance T-ODT is set to be off in the write mode.

For the non-target termination resistance NT-ODT, the resistance value thereof is set to be any one of 240/N ohm, wherein N is an integer of 2-10, i.e. the resistance value of the non-target termination resistance may be 120ohm, 80ohm, 60ohm, 48ohm, 40ohm, 34ohm, 30ohm, 27ohm, 24ohm, etc.

It is to be understood that the above resistance values are merely examples, and those skilled in the art may adopt other resistance values within the above resistance value interval.

Table 3 shows a comparison of the resistance values of the target termination resistance T-ODT, the non-target termination resistance NT-ODT, and the Soc termination resistance SoC-ODT according to one embodiment of the present disclosure.

Mode of operation	T-ODT	NT-ODT	SoC-ODT
				Read mode	Disconnect	Disconnect	48ohm
Write mode	Disconnect	48ohm	Disconnect

TABLE 3

As can be seen from tables 1, 2 and 3, the target termination resistance T-ODT of the target die T-D, whether in read mode or write mode, may preferably be set large enough, and more preferably may be set to off; the non-target termination resistance NT-ODT may be set large enough, and preferably may be set off, in the read mode, and may be set small, and preferably may be set at 48 ohms, in the write mode; the SoC termination resistance SoC-ODT may be set small, preferably 48 ohms, in read mode, and large enough, preferably off, in write mode.

It can also be seen from the above description that the target termination resistance T-ODT, whether in read or write mode, preferably remains in the off state, while the non-target termination resistance NT-ODT preferably differs depending on the switching of the modes. There is therefore an additional benefit to the embodiment described in connection with figure 7 d. That is, in case of the write mode, the first pulse signal P1 will trigger the non-target termination resistance NT-ODT to become 48ohm, for example, and after the data transmission of the write mode is finished, the non-target termination resistance NT-ODT may be triggered to become turned off by the second pulse signal P2. Thereafter, if the non-target die NT-D becomes the target die T-D after the data transfer from the write mode, then the original NT-ODT remains off at this time without any trigger operation, which saves modifications to the timing diagram of the signals and reduces the complexity of the design.

In addition, to facilitate the mass production of components, it is preferable to uniformly set the termination resistance in the die to a fixed value (e.g., 48 ohms), and then control the resistance values of the T-ODT and NT-ODT by opening and closing the switches, e.g., infinity when the switches are open and 48 ohms when the switches are closed.

Further, it is to be understood that 48 ohms is merely an exemplary resistance value and that any other suitable resistance value or values specified in the LPDDR5 specification may be employed by one skilled in the art.

According to another embodiment of the present disclosure, the memory may further include a mode register MR (not shown in the figures) having a parameter list stored therein, such that the memory is capable of setting at least the die D1-Dn according to the parameter list.

The parameter list may include, for example, the state that the termination resistor should be in different operating modes, the magnitude of the resistance value in different states, etc., events that should occur under respective clock signals, etc. The mode register may be provided in a memory including die D1-Dn, or may be provided in each die.

According to another embodiment of the present disclosure, the memory device may further include a memory controller connected to the die D1-Dn and configured to control a resistance value of the target termination resistance T-ODT of the target die T-D. Optionally, the controller may be further configured to control the resistance value of the non-target termination resistor NT-ODT of the non-target die NT-D.

In this embodiment, the target die T-D and the target termination resistance T-ODT therein may be controlled by an external memory controller. The memory controller may also control the non-target die NT-D and its non-target termination resistance NT-ODT, which facilitates a reliable backup in case of a failure of the communication path.

The memory controller may be separate or integrated in an external processor chip, for example, a CPU chip, a GPU chip or an SoC chip.

The memory described above may be the low power dual data rate memory LPDDR or any other memory that satisfies this architecture. Where the memory is LPDDR storage, the memory control may be a DDR controller.

Fig. 8a to 8d are schematic diagrams showing various connection relationships among a plurality of dies, and for simplicity, fig. 8a and 8d are described by taking 4 dies as an example, and the internal structure of each die is omitted.

As shown in fig. 8a, the communication path is provided between every two dies. As shown in fig. 8a, die D1 is connected to die D2, D3, and D4, respectively; die D2 is connected to die D1, D3, and D4, respectively; die D3 is connected to die D1, D2, and D4, respectively; and die D4 is connected to die D1, D2, and D3, respectively.

The embodiment shown in fig. 8a described above is advantageous for forming a backup, and once a certain die is out of order or damaged, it will not affect the normal operation of other dies.

As shown in fig. 8b, the communication paths form the dies into a ring connection so that each die can communicate with its neighboring dies. As shown in fig. 8b, die D1 is connected to adjacent dies D2 and D3, respectively, die D2 is connected to adjacent dies D1 and D4, die D3 is connected to adjacent dies D1 and D4, respectively, and die D4 is connected to adjacent dies D2 and D3, respectively.

The connection mode shown in fig. 8b is beneficial to simplifying the connection relationship between the dies, and reducing the establishment of communication paths, thereby reducing the chip area. Meanwhile, signals can be conducted between the dies, for example, when the die D1 is the target die T-D, the dies can be directly informed of D2 and D3 as non-target dies, and can be informed of the die D4 through the transmission of the die D2 or D3. Furthermore, even if a problem occurs in one of the communication paths in fig. 8b, the signal transmission thereof is not affected.

As shown in fig. 8c, the communication paths form the dies into star connections, including a central die in a central position and edge dies connected to the central die. In fig. 8c, die D4 acts as the center die, making connections to the other edge dies D1-D3, respectively. When die D4 becomes the target die T-D, then the other dies D1-D3, which are non-target dies, may be notified directly; while when one of D1-D3 becomes the target die T-D, the other die may be notified via die D4. The connection mode can form communication paths as few as possible, and is beneficial to reducing the area of a chip.

As shown in FIG. 8D, the edge dies D1-D3 are connected such that each die has three communication paths with the other dies. Although fig. 8a and 8d are equivalent in practice in the case of 4 dies, the connection scheme of fig. 8a is more complicated for a larger number of dies, and the connection scheme of fig. 8d is also used to make the connection of the communication path as small as possible to avoid an excessive chip area while ensuring sufficient redundancy.

FIG. 9 shows a schematic block diagram of a processor system according to another embodiment of the present disclosure.

As shown in fig. 9, the present disclosure further provides a processor system, comprising a processor chip and the above memory, wherein the processor chip is connected to the dies D1-Dn, and wherein the processor chip sets the target termination resistance T-ODT, the resistance value of the non-target termination resistance NT-ODT, and/or the termination resistance of the processor chip according to the operating mode of the target die T-D.

The processor chip may include a CPU chip, a GPU chip, or an SoC chip.

According to one embodiment of the present disclosure, in a read mode, a termination resistance of the processor chip is set to not greater than 120 ohms.

According to one embodiment of the present disclosure, the processor system is set to 240/N, where N is an integer between 2-10.

According to one embodiment of the present disclosure, wherein in the write mode, a termination resistance of the processor system is set to off.

The present disclosure also provides a board card, including: the memory described above; or a package as described above; or include a processor system as described above.

The present disclosure also provides an electronic device, comprising: the memory described above; or comprises the above-mentioned package body; or a processor system as described above; or include the above-described board card.

FIG. 10 illustrates a flow chart of a storage method performed on a memory according to another aspect of the disclosure.

As shown in FIG. 10, the memory device includes at least two dies D1-Dn, each die including termination resistors ODT1-ODTn, with a communication path disposed between the at least two dies D1-Dn; one of the at least two dies D1-Dn is a target die T-D, the termination resistance of the target die T-D is a target termination resistance T-ODT, the other dies are non-target dies NT-D, the termination resistance of the non-target dies NT-D is a non-target termination resistance NT-ODT, and the working mode of the target die T-D comprises a reading mode and a writing mode; the method comprises the following steps: in operation S1010, a pulse signal is transmitted to the non-target die NT-D through the target die T-D to set a non-target termination resistance NT-ODT of the non-target die NT-D to a first resistance value matching the read mode or a second resistance value matching the write mode.

According to another embodiment of the present disclosure, the storage method may further include: in operation S1020, at the non-target die NT-D, the non-target termination resistance NT-ODT is set to a first resistance value matching the read mode or a second resistance value matching the write mode in response to receiving the pulse signal from the target die T-D.

Other operation steps of the storage method of the present disclosure can be obtained by combining the description of fig. 1a to fig. 9, and will not be described again here.

Fig. 11 also discloses a combined processing device 1100 to describe one specific application scenario of the memory of the present disclosure. The combined processing device 1100 includes a computing device 1102, a general interconnection 1104, other processing devices 1106, and a storage device 1108, which may be or include a memory as described above. The computing device interacts with other processing devices to collectively complete the operation specified by the user.

Other processing devices include one or more of general purpose/special purpose processors such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), neural network processors, and the like. The number of processors included in the other processing devices is not limited. The other processing devices are used as interfaces of the machine learning arithmetic device and external data and control, and comprise data transportation to finish basic control of starting, stopping and the like of the machine learning arithmetic device; other processing devices may cooperate with the machine learning computing device to perform computing tasks.

A universal interconnect interface for transferring data and control instructions between a computing device (including, for example, a machine learning computing device) and other processing devices. The computing device acquires required input data from other processing devices and writes the input data into a storage device on the computing device chip; control instructions can be obtained from other processing devices and written into a control cache on a computing device slice; the data in the storage module of the computing device can also be read and transmitted to other processing devices.

Storage 1108 is connected to the computing device and the other processing devices, respectively. The storage device 1108 is used to store data in the computing device and the other processing devices, and is particularly suitable for storing data that is not stored in the computing device or the other processing devices.

The combined processing device can be used as an SOC (system on chip) system of equipment such as a mobile phone, a robot, an unmanned aerial vehicle and video monitoring equipment, effectively reduces the core area of a control part, improves the processing speed and reduces the overall power consumption. In this case, the generic interconnect interface of the combined processing device is connected to some components of the apparatus. Some parts are such as camera, display, mouse, keyboard, network card, wifi interface.

In some embodiments, the present disclosure also discloses a chip including the above memory device or combined processing device.

In some embodiments, the disclosure also discloses a chip packaging structure, which includes the chip.

In some embodiments, the present disclosure also discloses an electronic device or apparatus including the memory described in the present disclosure.

Electronic devices or apparatuses include data processing apparatuses, robots, computers, printers, scanners, tablets, smart terminals, cell phones, automobile data recorders, navigators, sensors, cameras, servers, cloud servers, cameras, projectors, watches, headsets, mobile storage, wearable devices, vehicles, household appliances, and/or medical devices.

The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other ways of dividing the actual implementation, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some interfaces, and may be in an electrical, optical, acoustic, magnetic or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may also be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.

The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. With this understanding, when the technical solution of the present disclosure can be embodied in the form of a software product stored in a memory, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

The foregoing detailed description of the disclosed embodiments, and the specific examples used herein to illustrate the principles and implementations of the present disclosure, are presented solely to aid in the understanding of the methods and their core concepts; in addition, the disclosure should not be construed as limited to the particular embodiments set forth herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The present disclosure can be more clearly understood from the following clauses.

Clause a1. a memory, comprising:

at least two dies (D1-Dn), each die comprising a termination resistance (ODT1-ODTn), the at least two dies (D1-Dn) having a communication path disposed therebetween;

wherein the content of the first and second substances,

Clause a2. the memory device according to clause a1, wherein the non-target die (NT-D) is configured to set the non-target termination resistance (NT-ODT) to a first resistance value matching the read mode or a second resistance value matching the write mode in response to receiving the pulse signal from the target die (T-D).

Clause A3. the memory of clause a1 or a2, wherein,

the read mode includes a read mode entry time (Tr1), a read mode data transfer start time (Tr2) and a read mode data transfer end time (Tr 3);

the write mode includes a write mode entry time point (Tw1), a write mode data transfer start time point (Tw2), and a write mode data transfer end time point (Tw 3); and

the pulse signals include a first pulse signal (P1) and a second pulse signal (P2).

Clause a4. the memory according to any one of clauses a1-A3, wherein,

Clause a5. the memory according to any one of clauses a1-a4, wherein,

Clause a6. the memory according to any one of clauses a1-a5, wherein,

the second pulse signal (P2) is issued after the write mode data transmission end time point (Tw3) such that the non-target termination resistance (NT-ODT) is set to a first resistance value after the write mode data transmission starts.

Clause A7. the memory device of any one of clauses a1-a6, wherein the target termination resistance (T-ODT) is set to a resistance value not lower than the non-target termination resistance (NT-ODT).

Clause A8. is the memory device of any one of clauses a1-a7, wherein the target termination resistance (T-ODT) is turned off.

Clause A9. is the memory device of any one of clauses a1-a8, wherein the first resistance value of the non-target termination resistance (NT-ODT) is set to not less than 60 ohms in the read mode.

Clause a10. the memory according to any of clauses a1-a9, wherein the non-target termination resistance (NT-ODT) is set to off in the read mode.

Clause a11. the memory according to any one of clauses a1-a10, wherein, in the write mode, the second resistance value of the non-target termination resistance (NT-ODT) is set to not more than 120 ohm.

Clause a12. the memory according to any one of clauses a1-a11, wherein the second resistance value of the non-target termination resistance (NT-ODT) is set to any one of 240/N ohm, where N is any one integer from 2-10.

Clause a13. the memory of any one of clauses a1-a12, wherein the communication path is a single bidirectional communication path.

Clause a14. the memory of any one of clauses a1-a13, wherein the communication paths are two opposite unidirectional communication paths.

Clause a15. the memory according to any one of clauses a1-a14, further comprising a Mode Register (MR) having a parameter list stored therein, such that the memory is capable of setting the at least two dies (D1-Dn) according to the parameter list.

Clause a16. the memory device according to any one of clauses a1-a15, further comprising a memory controller connected with the at least two dies (D1-Dn) and configured to control a resistance value of a target termination resistance (T-ODT) of the target die (T-D).

Clause a17. the memory according to any one of clauses a1-a16, wherein the controller is further configured to control a resistance value of a non-target termination resistance (NT-ODT) of the non-target die (NT-D).

Clause a18. the memory according to any one of clauses a1-a17, wherein the memory is a low power dual data rate memory LPDDR.

Clause a19. a package comprising a memory according to anyone of clauses a1-a18, wherein the communication path is arranged inside the package directly connecting the at least two dies (D1-Dn).

Clause a20. a package comprising a memory according to any one of clauses a1-a18, wherein the package is externally provided with external terminals through which the communication path connects at least two dies (D1-Dn).

Clause a21. a processor system, comprising a processor chip connected to at least two dies (D1-Dn), and a memory according to any of clauses a1-a18, wherein the processor chip sets the target termination resistance (T-ODT), the resistance value of the non-target termination resistance (NT-ODT), and/or the termination resistance of the processor chip according to the operating mode of the target die (T-D).

Clause a22. the processor system according to clause a21, wherein the processor chip comprises a CPU chip, a GPU chip, or an SoC chip.

Clause a23. the processor system according to clause a21 or a22, wherein, in the read mode, the termination resistance of the processor chip is set to not more than 120 ohm.

Clause a24. the processor system according to any one of clauses a21-a23, wherein the processor system is set to 240/N, wherein N is an integer between 2-10.

Clause a25. the processor system according to any of clauses a21-a24, wherein in the write mode, a termination resistance of the processor system is set to open.

Clause a26. a board card comprising:

memory according to any one of clauses a1-a 18; or

The package of clause a19 or a 20; or

The processor system of any one of clauses a21-a 25.

Clause a27. an electronic device, comprising:

memory according to any one of clauses a1-a 18; or

The package of clause a19 or a 20; or

The processor system of any one of clauses a21-a 25; or

The card of clause a26.

Clause a28. a memory method performed on a memory device, the memory device comprising at least two dies (D1-Dn), each die comprising a termination resistance (ODT1-ODTn), the at least two dies (D1-Dn) having a communication path disposed therebetween; wherein one of the at least two dies (D1-Dn) is a target die (T-D) having a termination resistance of a target termination resistance (T-ODT) and the others are non-target dies (NT-D) having termination resistances of non-target termination resistances (NT-ODT), the operating modes of the target die (T-D) include a read mode and a write mode;

the method comprises the following steps:

Clause a29. the memory method according to claim 28, wherein, at the non-target die (NT-D), the non-target termination resistance (NT-ODT) is set to a first resistance value matching the read mode or a second resistance value matching the write mode in response to receiving the pulse signal from the target die (T-D).

Clause a30. the storage method according to clause a28 or a29, wherein,

the read mode includes a read mode entry time (Tr1), a read mode data transfer start time (Tr2) and a read mode data transfer end time (Tr 3);

the write mode includes a write mode entry time point (Tw1), a write mode data transfer start time point (Tw2), and a write mode data transfer end time point (Tw 3); and

the pulse signals include a first pulse signal (P1) and a second pulse signal (P2).

Clause a31. the storage method according to any one of clauses a28-a30, wherein,

Clause a32. the storage method according to any one of clauses a28-a31, wherein,

Clause a33. the storage method according to any one of clauses a28-a32, wherein,

Clause a34. the memory method according to any one of clauses a28-a33, wherein the resistance value of the target termination resistance (T-ODT) is set to be not lower than the resistance value of the non-target termination resistance (NT-ODT).

Clause a35. the memory method according to any one of clauses a28-a34, wherein the target termination resistance (T-ODT) is turned off.

Clause a36. the memory method according to any one of clauses a28-a35, wherein in the read mode, the first resistance value of the non-target termination resistance (NT-ODT) is set to not less than 60 ohm.

Clause a37. the memory method according to any one of clauses a28-a36, wherein in the read mode, the non-target termination resistance (NT-ODT) is set to off.

Clause a38. the memory method according to any one of clauses a28-a37, wherein, in the write mode, the second resistance value of the non-target termination resistance (NT-ODT) is set to not more than 120 ohm.

Clause a39. the memory method according to any one of clauses a28-a38, wherein the resistance value of the non-target termination resistance (NT-ODT) is set to any one of 240/N ohm, where N is any one integer from 2-10.

Clause a40. the storage method of any one of clauses a28-a39, wherein the communication path is a single bidirectional communication path.

Clause a41. the storage method of any one of clauses a28-a40, wherein the communication paths are two opposite unidirectional communication paths.

Clause a42. the storage method according to any one of clauses a28-a41, the memory further comprising a Mode Register (MR) in which a parameter list is stored, such that at least the at least two dies (D1-Dn) can be set according to the parameter list.

Clause a43. the memory method according to any one of clauses a28-a42, further comprising controlling a resistance value of a target termination resistance (T-ODT) of the target die (T-D) by a memory controller connected with the at least two dies (D1-Dn).

Clause a44. the memory method according to any one of clauses a28-a43, wherein further comprising controlling, by the controller, a resistance value of a non-target terminal resistance (NT-ODT) of the non-target die (NT-D).

Clause a45. the storage method according to any one of clauses a28-a44, wherein the memory is a low power dual data rate memory LPDDR.

37页详细技术资料下载

Memory and device comprising same

相关技术

网友询问留言