阅读说明：本技术 互联裸芯与dsp/fpga的通信方法及其通信系统 (Communication method and communication system for interconnecting bare chip and DSP/FPGA ) 是由 魏敬和 黄乐天 于宗光 曹文旭 丁涛杰 刘国柱 于 2021-02-05 设计创作，主要内容包括：本发明涉及互联裸芯与DSP/FPGA的通信方法及其通信系统。互联裸芯与DSP/FPGA的通信方法,包括多个数据接口,每个所述数据接口均设有不同的协议转换模块,所述数据接口通信时包括数据输入转换和数据输出转换；所述数据输入转换时,DSP/FPGA的外部数据经过协议转换模块转换成统一的数据协议格式传递至互联裸芯内部的裸芯级网络进行数据的统一传输；所述数据输出转换时,互联裸芯内部的内部数据根据数据自身的数据性质被协议转换模块转换成不同的数据协议格式进入不同的数据接口传输至DSP/FPGA。该方法通过将外部数据与内部数据相互转换使得每个设备和器件都能以任意的形态接入多裸芯系统中,提升了系统的灵活性,有利于系统的灵活组装、快速定义和快速实现。(The invention relates to a communication method and a communication system for interconnecting a bare chip and a DSP/FPGA. The communication method of the interconnected bare chip and the DSP/FPGA comprises a plurality of data interfaces, wherein each data interface is provided with a different protocol conversion module, and the data interfaces comprise data input conversion and data output conversion during communication; when the data is input and converted, external data of the DSP/FPGA is converted into a uniform data protocol format through the protocol conversion module and is transmitted to a die level network in the interconnected die for uniform transmission of the data; when the data output is converted, the internal data in the interconnected bare chip is converted into different data protocol formats by the protocol conversion module according to the data property of the data, enters different data interfaces and is transmitted to the DSP/FPGA. According to the method, each device and device can be connected into the multi-die system in any form by mutually converting external data and internal data, so that the flexibility of the system is improved, and the flexible assembly, the rapid definition and the rapid realization of the system are facilitated.)

1. The communication method of the interconnected bare chip and the DSP/FPGA is characterized by comprising a plurality of data interfaces, wherein each data interface is provided with a different protocol conversion module, and the data interfaces comprise data input conversion and data output conversion during communication;

when the data is input and converted, external data of the DSP/FPGA is converted into a uniform data protocol format through the protocol conversion module and is transmitted to a die level network in the interconnected die for uniform transmission of the data;

when the data output is converted, the internal data in the interconnected bare chip is converted into different data protocol formats by the protocol conversion module according to the data property of the data, enters different data interfaces and is transmitted to the DSP/FPGA.

2. The communication system of the interconnection bare chip and the DSP/FPGA is characterized in that the interconnection bare chip is provided with a plurality of data interfaces, the data interfaces are used for being connected with the DSP/FPGA, each data interface is provided with different protocol conversion circuits, and the protocol conversion circuits are used for converting different external data into a uniform data protocol format and entering the interconnection bare chip and converting the data in the interconnection bare chip into a corresponding data protocol format according to the target data interface of the data.

3. The interconnected die and DSP/FPGA communication system of claim 2 wherein said data interface comprises a master interface, a slave interface and a peer interface.

4. The interconnected die and DSP/FPGA communication system of claim 3, wherein said master interface comprises: the device comprises an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, wherein the interrupt interface is used for receiving an interrupt request transmitted from an interconnection bare chip; the DDR data interface is used for the DSP/FPGA to start data transmission in a master device mode; the SPI interface is used for loading BOOT ROM starting codes when the main equipment is started; the JTAG interface is used for debugging the main equipment.

5. The interconnected die and DSP/FPGA communication system of claim 3, wherein said slave interface comprises: the PCIe interface is used for transmitting data; the interrupt interface is used for issuing an interrupt request from a device.

6. The interconnected die and DSP/FPGA communication system of claim 3 wherein said peer device interface comprises a RapidIO interface for transmitting data.

Technical Field

The invention relates to a communication system with a DSP/FPGA, in particular to a communication method and a communication system for interconnecting a bare chip and the DSP/FPGA.

Background

With the development of digital integrated circuits, a System on Chip (SoC, which means that a plurality of functional modules are integrated on the same silicon Chip) has become a necessary scheme for implementing a high-performance System, and manufacturers meet the requirements of users on product performance by continuously enlarging the scale of the SoC. However, due to process engineering and the like, moore's law (i.e., the law that the number of transistors that can be accommodated on an integrated circuit doubles every 24 months) is becoming increasingly ineffective, which makes the cost and development cycle for scaling up integrated circuits on a single silicon wafer extremely high.

In the future, integrated circuits will be developed toward multi-Die (Die) integration, that is, a plurality of functional and verified, unpackaged chip components are interconnected and assembled together, and packaged as a whole chip in a same Package, so as to form a Network on Package (NoP). These dies can be made by different processes and from different manufacturers, thus greatly shortening and reducing the development cycle and difficulty.

With the arrival of a big data era and the development of technologies such as artificial intelligence, people have an increasing demand for computing power, and in the future, multi-die systems will not leave devices with powerful parallel computing power, such as an FPGA (Field Programmable Gate Array), a DSP (Digital Signal processor), and other special accelerators. The types of external interfaces of the devices are rich and different from each other, when the bare chips of the devices are assembled into a whole, the current multi-bare chip systems generally use a dedicated and fixed protocol interface to directly connect the bare chips, and the fixed protocol interface corresponds to a fixed hardware circuit, which means that the devices will play a fixed role in the system and perform a fixed function, which reduces the flexibility of the system and increases the reconfiguration time cost of the system.

Disclosure of Invention

In order to solve the problems, the invention provides a communication method for interconnecting a bare chip and a DSP/FPGA, which can overcome the defects of poor flexibility and poor reconfigurability of the traditional method and realize flexible assembly, rapid definition and rapid realization of a multi-bare chip system comprising the DSP/FPGA by arranging a plurality of data interfaces by means of an extensible high-speed interconnected bare chip.

The specific technical scheme is as follows:

the communication method of the interconnected bare chip and the DSP/FPGA comprises a plurality of data interfaces, wherein each data interface is provided with a different protocol conversion module, and the data interfaces comprise data input conversion and data output conversion during communication; when the data is input and converted, external data of the DSP/FPGA is converted into a uniform data protocol format through the protocol conversion module and is transmitted to a die level network in the interconnected die for uniform transmission of the data; when the data output is converted, the internal data in the interconnected bare chip is converted into different data protocol formats by the protocol conversion module according to the data property of the data, enters different data interfaces and is transmitted to the DSP/FPGA.

The communication system comprises an interconnection bare chip and a DSP/FPGA, wherein the interconnection bare chip is provided with a plurality of data interfaces, the data interfaces are used for being connected with the DSP/FPGA, each data interface is provided with different protocol conversion circuits, and the protocol conversion circuits are used for converting different external data into a uniform data protocol format and entering the interconnection bare chip and converting the data in the interconnection bare chip into a corresponding data protocol format according to the target data interface of the data.

Preferably, the data interface includes a master device interface, a slave device interface and a peer device interface.

Further, the master device interface includes: the device comprises an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, wherein the interrupt interface is used for receiving an interrupt request transmitted from an interconnection bare chip; the DDR data interface is used for the DSP/FPGA to start data transmission in a master device mode; the SPI interface is used for loading BOOT ROM starting codes when the main equipment is started; the JTAG interface is used for debugging the main equipment.

Further, the slave device interface includes: the PCIe interface is used for transmitting data; the interrupt interface is used for issuing an interrupt request from a device.

Further, the peer device interface includes a RapidIO interface for transmitting data.

Compared with the prior art, the invention has the following beneficial effects:

according to the communication method for interconnecting the bare chip and the DSP/FPGA, provided by the invention, the external data is converted into the uniform data protocol format for internal transmission, and the internal data is converted into the corresponding data protocol format for transmission to the DSP/FPGA, so that each device and apparatus can be accessed into the multi-bare chip system in any form, the flexibility of the system is improved, and the flexible assembly, the rapid definition and the rapid implementation of the system are facilitated.

Drawings

FIG. 1 is a schematic diagram of a communication method for interconnecting dies with a DSP/FPGA;

FIG. 2 is a schematic diagram of a communication system interconnecting die and DSP/FPGA.

Detailed Description

The invention will now be further described with reference to the accompanying drawings.

Example one

As shown in fig. 1 and fig. 2, the communication method of the interconnected die and the DSP/FPGA includes a plurality of data interfaces, each of the data interfaces is provided with a different protocol conversion module, and the data interfaces include data input conversion and data output conversion when communicating; when the data is input and converted, external data of the DSP/FPGA is converted into a uniform data protocol format through the protocol conversion module and is transmitted to a die level network in the interconnected die for uniform transmission of the data; when the data output is converted, the internal data in the interconnected bare chip is converted into different data protocol formats by the protocol conversion module according to the data property of the data, enters different data interfaces and is transmitted to the DSP/FPGA.

As shown in fig. 1, inside the interconnected Die is an internal Die-level Network (NoD), which is composed of data nodes, routers, and transmission buses, the protocol conversion modules are respectively connected to the boundary nodes of the internal Die-level Network, the protocol conversion modules are used for transmitting data packets from interfaces or other interconnected Die, and the interconnected Die realizes data transmission in a packet switching manner. NoD adopts uniform data protocol format, which gets various external data interfaces through various protocol conversion circuits, and interfaces 1 to 6 in fig. 1 all adopt different data protocol formats as data interfaces connected with other die. Meanwhile, the DSP/FPGA is also provided with various data interfaces corresponding to the DSP/FPGA, and the DSP/FPGA and the interconnected bare chip are connected together according to the mode shown in figure 1, so that the high-efficiency communication between the DSP/FPGA and the interconnected bare chip can be realized.

The communication method connects the DSP/FPGA to the interconnected bare chip based on the abundant external interface types of the expandable high-speed interconnected bare chip, so that each device and each device can be connected into the multi-bare chip system in any form, the flexibility of the system is improved, and the flexible assembly, the quick definition and the quick realization of the system are facilitated.

Example two

As shown in fig. 1 and fig. 2, in the communication system between an interconnection die and a DSP/FPGA, the interconnection die is provided with a plurality of data interfaces, the plurality of data interfaces are used for being connected with the DSP/FPGA, each data interface is provided with a different protocol conversion circuit, and the protocol conversion circuit is used for converting different external data into a uniform data protocol format and entering the interconnection die and converting data inside the interconnection die into a corresponding data protocol format according to a destination data interface of the data.

The data interfaces include a master device interface, a slave device interface, and a peer device interface.

The master device interface includes: the device comprises an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, wherein the interrupt interface is used for receiving an interrupt request transmitted from an interconnection bare chip; the DDR data interface is used for the DSP/FPGA to start data transmission in a master device mode; the SPI interface is used for loading BOOT ROM starting codes when the main equipment is started; the JTAG interface is used for debugging the main equipment.

The slave device interface includes: the PCIe interface is used for transmitting data; the interrupt interface is used for issuing an interrupt request from a device.

The peer device interface includes a RapidIO interface for transmitting data.

The invention can realize the multi-type interface communication between the extensible high-speed interconnected bare chip and the DSP/FPGA, and benefits from two advantages of the interconnected bare chip: firstly, NoD with a uniform protocol is adopted in the interconnected bare chip, so that interfaces with various forms can be supported and compatible; and the interconnection bare chip is provided with abundant external interface types, so that the interconnection bare chip can be butted with various interface types of various DSPs and FPGAs, and the DSPs and FPGAs are supported to be accessed into the system in different forms.

The communication between different devices generally adopts a Master-slave mode, that is, a Master device (Master) sends out data control information (a read command or a write command), a slave device responds, and then data transmission is completed (interrupt and debug exception, the Master device does not send control information but receives an interrupt request of the slave device when interrupt occurs, and other devices read register data of the Master device through a debug interface of the Master device when debugging occurs). Thus, each device generally has three possible morphologies in the system: a master device, a slave device, or a peer device, wherein the peer device may act as both a master device and a slave device in a transmission. For the same data protocol, there are three kinds of interfaces, namely, a master device interface, a slave device interface and a peer device interface, which are respectively connected to the three kinds of devices. The interconnection bare chip is provided with abundant interface types, which not only supports various data protocols, but also supports equipment interfaces with different properties for the same data protocol, thereby providing great convenience for the interconnection of DSP/FPGA. Table 1 shows the data protocols and their interface properties common in several DSPs/FPGAs.

Table 1 common interface protocol for DSP/FPGA and its properties:

data protocol format	Nature of the interface
		DDR3/4	Master/slave interface
SPI	Master device interface
		JTAG	Slave device interface
PCIe	Slave device interface
		RapidIO	Peer-to-peer device interface
Interruption of a memory	Slave device interface

DDR3/4 is third or fourth generation DDR.

As shown in fig. 2, in the communication system of the interconnected bare chip and the DSP/FPGA, the interconnected bare chip and the DSP/FPGA are respectively provided with three data interfaces, namely a master device interface, a slave device interface and a peer device interface, wherein the master device interface includes an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, the interrupt interface is used for receiving an interrupt request transmitted from the interconnected bare chip, the DDR data interface is used for the DSP/FPGA to initiate data transmission in a master device mode, the SPI interface is used for loading a BOOT ROM start code when the master device is started, and the JTAG interface is a debugging interface of the master device. The slave device interface includes a PCIe interface for transmitting data and an interrupt interface for issuing an interrupt request from the slave device. The peer device interface includes a RapidIO interface for transmitting data.

In the communication process of the DSP/FPGA and the interconnected bare chip, all data from the DSP/FPGA are converted into a uniform data protocol format through different types of data interfaces and enter NoD of the interconnected bare chip; meanwhile, the data from NoD can be converted into different data protocol formats according to its own destination address, enter different types of data interfaces, and finally be transmitted to the DSP/FPGA.

The functional bare chips such as the DSP and the FPGA are connected to one interconnected bare chip through the interconnected bare chip, interface conversion and data communication are realized by the interconnected bare chip in a unified mode, and when the system is constructed, each bare chip can be made into various devices and adopt any form, so that different roles can be played, different functions can be executed, flexible assembly, quick definition and quick realization of a multi-bare chip system are facilitated, the flexibility of system assembly is greatly improved, and the time cost for system reconstruction is reduced.

The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive step, which shall fall within the scope of the appended claims.