阅读说明：本技术 一种嵌入式存储器的参数测试的分类筛选方法 (Classification screening method for parameter test of embedded memory ) 是由 任栋梁 于 2021-02-05 设计创作，主要内容包括：本发明提供的一种嵌入式存储器的参数测试的分类筛选方法,包括以下步骤：设定存储器的电参数的修调档位的筛选手段；执行晶圆测试,以得到实测的电参数的实测修调档位；将所述电参数的实测修调档位记录到log文档中；以及对所述log文档中的记录的电参数的实测修调档位进行分析,并绘制测试晶圆图谱。本发明通过log文档记录的每个晶圆的电参数的实测修调档位,不仅可以将修调档位异常的芯片剔除,提供了可靠性风险预警机制,还有效提高了芯片的可靠性指标。(The invention provides a classified screening method for parameter test of an embedded memory, which comprises the following steps: a screening means for setting the trimming gear of the electrical parameter of the memory; executing a wafer test to obtain an actually measured trimming gear of the actually measured electrical parameter; recording the actually measured trimming gear of the electrical parameter into a log document; and analyzing the actually measured trimming gear of the recorded electrical parameters in the log document, and drawing a test wafer map. According to the invention, the chips with abnormal trimming gears can be removed through the actually measured trimming gears of the electrical parameters of each wafer recorded by the log file, so that a reliability risk early warning mechanism is provided, and the reliability indexes of the chips are effectively improved.)

1. A classification screening method for parameter test of an embedded memory is characterized by comprising the following steps:

a screening means for setting the trimming gear of the electrical parameter of the memory;

executing a wafer test to obtain an actually measured trimming gear of the electrical parameter;

recording the actually measured trimming gear of the electrical parameter into a log document; and

and analyzing the actually measured trimming gear of the recorded electrical parameters in the log document, and drawing a test wafer map.

2. The classification screening method of claim 1, wherein the electrical parameters include write, read, and erase related parameters.

3. The classification screening method according to claim 2, wherein the electrical parameters include in particular a write voltage, an erase voltage, a read voltage, a write current and an erase current.

4. The method of classification screening of claim 3, wherein performing a wafer test to obtain a measured trim level for the measured electrical parameter comprises:

and executing the wafer test to obtain a trimming write-in voltage value and a corresponding actual measurement trimming gear, a trimming erase voltage value and a corresponding actual measurement trimming gear, a trimming read-out voltage value and a corresponding actual measurement trimming gear, a trimming write-in current value and a corresponding actual measurement trimming gear, and a trimming erase current value and a corresponding actual measurement trimming gear.

5. The classification screening method of claim 4, wherein recording the measured modification gear of the electrical parameter into a log document specifically comprises:

and recording the modification writing voltage value and the corresponding actual measurement modification gear thereof, the modification erasing voltage value and the corresponding actual measurement modification gear thereof, the modification reading voltage value and the corresponding actual measurement modification gear thereof, the modification writing current value and the corresponding actual measurement modification gear thereof, and the modification erasing current value and the corresponding actual measurement modification gear thereof into a log document.

6. The method of classification screening of claim 5, wherein analyzing the recorded measured trim gears of the electrical parameters in the log document and mapping a test wafer comprises:

in analyzing the measured trim gears of the recorded electrical parameters in the log document,

if the chip with the abnormal actual measurement adjustment gear of the electrical parameter exists, the chip is removed, and a first test wafer map is drawn;

according to the ink track of the Sudoku, if a plurality of chips adjacent to a qualified chip have abnormal actually-measured adjustment gear positions of electrical parameters, the qualified chip is also removed, and a second test wafer map is drawn; and

if the chip failure rate of the abnormal actual measurement of the electrical parameters during the trimming process exceeds the preset standard, the processing of the chip on the wafer needs to be judged, and a third test wafer map is drawn.

7. The classification screening method of claim 6, further comprising, after drawing the test wafer map:

and merging and modifying the first test wafer map, the second test wafer map and the third test wafer map so as to obtain a final test wafer map.

8. The classification screening method of claim 7, wherein the final test wafer map includes a composite map of the first test wafer map, the second test wafer map, and the third test wafer map.

9. The classification screening method according to any one of claims 1 to 8, wherein the wafer includes a plurality of chips arranged in an array, and the chips are sequentially tested in a serpentine shape, or are tested in rows and columns during the test of the wafer.

10. The classification screening method according to any one of claims 1 to 8, wherein the embedded memory is an embedded flash memory.

Technical Field

The invention relates to the technical field of integrated circuit testing, in particular to a classified screening method for parameter testing of an embedded memory.

Background

Semiconductor memories are classified into volatile memories, which lose memorized data when power is turned off, and nonvolatile memories, which protect data even when power is turned off. The ROM is a nonvolatile memory, and the ROM is classified into two types according to whether a user can write data, one type is a user-writable ROM, and the other type is a Mask ROM written by a manufacturer in a manufacturing process. Among the user-writable ROMs, EEPROMs (Electrically Erasable Programmable ROM) and eflash (Embedded Flash Memory) are commonly used.

The flash is a product of the maturation of EEPROM, the development of semiconductor technology into sub-micron technology, and the demand for large capacity electrically erasable and programmable memories. The principle of storing data is that charge is formed and stored on the floating gate electrode. Compared with EEPROM, eflash has comparable superiority in integration level; its cell area is only one-fourth of that of a conventional EEPROM. EEPROM tends to be replaced by eflash due to its high cost, low demand, and low integration level.

In the eflash manufacturing process, there is an eflash testing step, which is to control the testing system hardware to ensure that the tested eflash meets or exceeds some of the design criteria defined in the device specification in a certain manner. Typically, classification of test items is based on a comparison of test parameter values for voltage or current with corresponding specifications. From the whole wafer, although the process procedures are distributed differently in the wafer, the trimming gears of the local positions of the wafer are relatively fixed, and in the same area position of the wafer, the trimming gears of the adjacent chips are close, if the skip gear fluctuation is large, the area is identified as a chip reliability risk area. However, this method only screens the embedded memories for chip functionality, which has a risk of reliability-related overlooks.

Disclosure of Invention

The invention aims to provide a classification screening method for parameter testing of an embedded memory, which aims to solve the problem of reliability-related overlooking risks brought by the existing classification screening method.

In order to solve the above technical problem, the present invention provides a classification screening method for parameter testing of an embedded memory, which comprises the following steps:

a screening means for setting the trimming gear of the electrical parameter of the memory;

executing a wafer test to obtain an actually measured trimming gear of the electrical parameter;

recording the actually measured trimming gear of the electrical parameter into a log document; and

and analyzing the actually measured trimming gear of the recorded electrical parameters in the log document, and drawing a test wafer map.

Optionally, the electrical parameters include write, read and erase related parameters.

Further, the electrical parameters specifically include a write voltage, an erase voltage, a read voltage, a write current, and an erase current.

Further, the performing the wafer test to obtain the measured trimming step of the measured electrical parameter includes:

and executing the wafer test to obtain a trimming write-in voltage value and a corresponding actual measurement trimming gear, a trimming erase voltage value and a corresponding actual measurement trimming gear, a trimming read-out voltage value and a corresponding actual measurement trimming gear, a trimming write-in current value and a corresponding actual measurement trimming gear, and a trimming erase current value and a corresponding actual measurement trimming gear.

Further, recording the measured trimming gear of the electrical parameter into a log document specifically includes:

and recording the modification writing voltage value and the corresponding actual measurement modification gear thereof, the modification erasing voltage value and the corresponding actual measurement modification gear thereof, the modification reading voltage value and the corresponding actual measurement modification gear thereof, the modification writing current value and the corresponding actual measurement modification gear thereof, and the modification erasing current value and the corresponding actual measurement modification gear thereof into a log document.

Further, analyzing the actually measured trimming gear of the recorded electrical parameter in the log document, and drawing a test wafer map comprises:

in analyzing the measured trim gears of the recorded electrical parameters in the log document,

if the chip with the abnormal actual measurement adjustment gear of the electrical parameter exists, the chip is removed, and a first test wafer map is drawn;

according to the ink track of the Sudoku, if a plurality of chips adjacent to a qualified chip have abnormal actually-measured adjustment gear positions of electrical parameters, the qualified chip is also removed, and a second test wafer map is drawn; and

if the chip failure rate of the abnormal actual measurement of the electrical parameters during trimming exceeds the preset standard, the processing of the chip on the wafer needs to be judged, and a third test wafer map is drawn.

Further, after the test wafer map is drawn, the method further comprises:

and merging and modifying the first test wafer map, the second test wafer map and the third test wafer map so as to obtain a final test wafer map.

Further, the final test wafer map includes a composite map of the first test wafer map, the second test wafer map, and the third test wafer map.

Furthermore, the wafer comprises a plurality of chips arranged in an array, and in the process of executing the test of the wafer, the chips are sequentially tested along a snake shape, or are tested in rows and columns.

Further, the embedded memory is an embedded flash memory.

Compared with the prior art, the method has the following beneficial effects:

the invention provides a classified screening method for parameter test of an embedded memory, which comprises the following steps: a screening means for setting the trimming gear of the electrical parameter of the memory; executing a wafer test to obtain an actually measured trimming gear of the actually measured electrical parameter; recording the actually measured trimming gear of the electrical parameter into a log document; and analyzing the actually measured trimming gear of the recorded electrical parameters in the log document, and drawing a test wafer map. According to the invention, the chips with abnormal trimming gears can be removed through the actually measured trimming gears of the electrical parameters of each wafer recorded by the log file, so that a reliability risk early warning mechanism is provided, and the reliability indexes of the chips are effectively improved.

Drawings

Fig. 1 is a flowchart of a classification screening method for parameter testing of an embedded memory according to an embodiment of the present invention.

Detailed Description

The classification screening method for parameter testing of an embedded memory according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the accompanying drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art may modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.

In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.

In order to make the objects and features of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.

Fig. 1 is a flowchart of a classification screening method for parameter testing of an embedded memory according to this embodiment. As shown in fig. 1, the present embodiment provides a classification screening method for parameter testing of an embedded memory, which includes the following steps:

step S10: a screening means for setting the trimming gear of the electrical parameter of the memory;

step S20: executing a wafer test to obtain an actually measured trimming gear of the electrical parameter;

step S30: recording the actually measured trimming gear of the electrical parameter into a log document; and

step S40: and analyzing the actually measured trimming gear of the recorded electrical parameters in the log document, and drawing a test wafer map.

The classification screening method for the parameter test of the embedded memory proposed by the present invention is described in detail below with reference to fig. 1.

First, step S10 is executed to set a selection means for the trimming step of the electrical parameter in the memory.

In this embodiment, the embedded memory is an embedded flash memory, and the electrical parameters include write, read and erase related parameters, such as voltage and current, specifically, write voltage, erase voltage, read voltage, write current and erase current, and the like, that is, parameters related to write, read and erase of eflash are modified. For each of the parameters, a plurality of design gears are set according to design specifications, for example, 16 design gears are set, wherein part of the design gears are safe gears, and part of the design gears are unsafe gears. In the embodiment, the classification of the test items is performed through the trimming gear of the electrical parameter of the memory, and the classification of the test items in the prior art only through the comparison of the voltage parameter value and the design specification or the comparison of the current parameter value and the design specification is replaced, so that the occurrence of the reliability-related omission risk is favorably avoided.

Then, in step S20, a wafer test is performed to obtain a measured trimming step of the electrical parameter. Specifically, a wafer test is executed to obtain a trimming write-in voltage value and a corresponding actual measurement trimming gear, a trimming erase voltage value and a corresponding actual measurement trimming gear, a trimming read-out voltage value and a corresponding actual measurement trimming gear, a trimming write-in current value and a corresponding actual measurement trimming gear, and a trimming erase current value and a corresponding actual measurement trimming gear.

The wafer comprises a plurality of chips arranged in an array, the chips are sequentially tested along a snake shape or are tested in rows and columns in the test process of the wafer, and in other embodiments, the chips can be sequentially tested from inside to outside along or from outside to inside in a thread sequence according to actual requirements.

In this embodiment, the number of the data of the electrical parameter is at most 16, and a set of data of write voltage, erase voltage, read voltage, write current or erase current, etc. is loaded into the computer, and the number of the data is usually 16, and the data is located in 16 gears of the calculator; and continuously adjusting to a proper voltage or current by blowing a corresponding fuse in the memory at the value under the shift position (this process is called trimming), in which a Precision Measurement Unit (PMU) is required for measurement, and then a relevant program is written in a corresponding computer language, and the measured value closest to the target value is selected from the 16 measured values as a final result, that is, a shift range closest to the target value is determined, for example: from the 16 gears, 5 gears are selected as a suitable gear range, such as gear 1 to gear 5, that is, from the 16 gears, gear 1 to gear 5 are safe gears, and 6-16 are unsafe gears.

And step S30 is executed, and the measured trimming gear of the electrical parameter is recorded into a log document so as to be convenient for a subsequent recording system to judge and analyze.

Specifically, the trimming write-in voltage value and the corresponding actual measurement trimming gear, the trimming erase voltage value and the corresponding actual measurement trimming gear, the trimming read-out voltage value and the corresponding actual measurement trimming gear, the trimming write-in current value and the corresponding actual measurement trimming gear, and the trimming erase current value and the corresponding actual measurement trimming gear are recorded in a log document.

And step S40 is executed, the actually measured trimming gear of the recorded electrical parameters in the log file is analyzed, and a test wafer map is drawn.

Specifically, in the step, when the recorded actually measured trimming gear of the electrical parameter in the log document is analyzed, if an abnormal chip exists in the actually measured trimming gear of the electrical parameter, the chip is removed (for example, the actually measured trimming gear of the chip is in an unsafe gear, i.e., 6-16), and a first test wafer map is drawn at the same time; according to the ink track of the Sudoku, if a plurality of chips adjacent to a qualified chip have abnormal actually-measured adjustment gear positions of electrical parameters, the qualified chip is also removed, and a second test wafer map is drawn; if the chip failure rate of the abnormal actual measurement of the electrical parameters during trimming exceeds a certain preset standard, the processing of the chip on the wafer needs to be judged, and a third test wafer map is drawn.

In the embodiment, the actual measurement of the electrical parameters of each wafer recorded by the log file is used for trimming the gears, so that not only can the chips with abnormal trimming gears be removed, but also a reliability risk early warning mechanism can be provided.

And then, modifying the test wafer map according to the analysis result. Specifically, the first test wafer map, the second test wafer map and the third test wafer map are merged and modified, so that a final test wafer map is obtained. The test wafer map comprises a composite map in the first test wafer map, the second test wafer map and the third test wafer map, so that the removed chips of the three test wafer maps are all contained, and the reliability index of the chips is effectively improved.

In summary, the classification and screening method for parameter testing of embedded memory provided by the present invention includes the following steps: a screening means for setting the trimming gear of the electrical parameter of the memory; executing a wafer test to obtain an actually measured trimming gear of the actually measured electrical parameter; recording the actually measured trimming gear of the electrical parameter into a log document; and analyzing the actually measured trimming gear of the recorded electrical parameters in the log document, and drawing a test wafer map. According to the invention, the chips with abnormal trimming gears can be removed through the actually measured trimming gears of the electrical parameters of each wafer recorded by the log file, so that a reliability risk early warning mechanism is provided, and the reliability indexes of the chips are effectively improved.

In addition, unless otherwise specified or indicated, the description of the terms "first" and "second" in the specification is only used for distinguishing various components, elements, steps and the like in the specification, and is not used for representing logical relationships or sequential relationships among the various components, elements, steps and the like.

It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.