阅读说明：本技术 对列平面压缩数据进行编码的装置和方法 (Apparatus and method for encoding column plane compressed data ) 是由 E·J·里奇-普洛特金 C·G·维杜威特 B·H·拉姆 G·S·亨德里克斯 S·M·希尔德 于 2020-11-09 设计创作，主要内容包括：本申请涉及对列平面压缩数据进行编码的装置和方法。一种示例性存储器包含：存储器单元阵列,所述存储器单元阵列配置为存储多个数据位,每个数据位与相应列平面相关联；和输入/输出电路,所述输入/输出电路包含压缩电路,所述压缩电路配置为基于从存储器单元阵列接收的多个数据位的位与期望值之间的比较以及基于存储器单元阵列的与所述位相关联的相应列平面,来提供错误数据。压缩电路进一步配置为基于错误数据对列平面误码进行编码,以提供给数据端子。(The present application relates to an apparatus and method for encoding column plane compressed data. An exemplary memory includes: a memory cell array configured to store a plurality of data bits, each data bit associated with a respective column plane; and input/output circuitry including compression circuitry configured to provide error data based on a comparison between a bit of a plurality of data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array associated with the bit. The compression circuit is further configured to encode the column plane bit error based on the error data for provision to the data terminal.)

1. An apparatus, comprising:

a compare circuit configured to receive a plurality of column plane read data bits during a test operation, each of the column plane read data bits associated with a respective column plane of a memory cell array, wherein the compare circuit is further configured to detect whether a value of a bit of the plurality of column plane read data bits differs from an expected value and provide error data based on the detection and based on the respective column plane of the memory cell array associated with the bit; and

an encoder circuit configured to encode a column plane error code based on the error data for provision to a data terminal.

2. The apparatus of claim 1, wherein the comparison circuit is configured to receive the expected value of the bit from a tester.

3. The apparatus of claim 1, wherein the comparison circuitry is configured to determine the expected value based on a logical bit-by-bit comparison between the plurality of column-plane read data bits.

4. The device of claim 3, wherein the logical bitwise comparison includes a bitwise XOR, comparison, a bitwise NAND comparison, or a combination thereof, between at least two of the plurality of column plane read data bits.

5. The device of claim 3, wherein the comparison circuitry is configured to select one of the first or second logical values as the expected value based on whether more than half of the group of the plurality of column plane read data bits have the first or second logical values.

6. The apparatus of claim 1, wherein the encoder circuitry is configured to, in response to the error data indicating that the value of the bits of the plurality of column-plane read data bits is different than the expected value and is associated with a first column plane:

encoding the column plane error code with a first value based on the first column plane, wherein the error data indicates that all other bits of the plurality of column plane read data bits match the expected value; and

in response to the error data indicating that the value of a second bit of the plurality of column plane read data bits associated with a second column plane is different than the expected value, encoding the column plane error code with a second value.

7. The apparatus of claim 1, further comprising a serializer configured to serialize bits of the column plane error to provide to the data terminal configured as a test data terminal.

8. A memory, comprising:

a memory cell array configured to store a plurality of data bits, each of the data bits associated with a respective column plane; and

input/output circuitry comprising compression circuitry configured to provide error data based on a comparison between bits of the plurality of data bits received from the memory cell array and expected values and based on respective column planes of the memory cell array associated with the bits, wherein the compression circuitry is further configured to encode column plane errors based on the error data for provision to data terminals.

9. The memory of claim 8, wherein the compression circuit is configured to:

in response to the error data indicating that the value of the bit of the plurality of data bits is different from the expected value and is associated with a first column plane, encoding the column plane error code with a first value; and

in response to the error data indicating that the value of the bit of the plurality of data bits is different from the expected value and is associated with a second column plane, encoding the column plane error code with a second value.

10. The memory of claim 8, wherein the compression circuit is configured to select one of the first logical value or the second logical value as the expected value based on whether more than half of the group of the plurality of data bits have the first logical value or the second logical value.

11. A method, comprising:

during a test operation of a compression circuit of a semiconductor device, receiving a plurality of column plane read data bits, each of the column plane read data bits associated with a respective column plane of a memory cell array of the semiconductor device;

detecting whether a value of a bit of the plurality of column plane read data bits differs from an expected value;

encoding a column plane error code based on detecting whether the value of the bit of the plurality of column plane read data bits has the value different from the expected value and based on the respective column plane associated with the bit; and

storing the column plane bit error at the semiconductor device.

12. The method of claim 11, further comprising receiving the expected value of the bit from a tester.

13. The method of claim 11, further comprising determining the expected value based on a logical bit-by-bit comparison between the plurality of column-plane read data bits.

14. The method of claim 13, wherein the logical bitwise comparison includes a bitwise XOR, a comparison, a bitwise NAND comparison, or a combination thereof between at least two of the plurality of column plane read data bits.

15. The method of claim 13, further comprising selecting one of the first logical value or the second logical value as the expected value based on whether more than half of a group of the plurality of column plane read data bits have the first logical value or the second logical value.

16. The method of claim 11, further comprising:

encoding the column plane error code with a first value in response to the value of the bit of the plurality of column plane read data bits being different from the expected value when the bit is associated with a first column plane; and

encoding the column plane error code with a second value in response to the value of the bit of the plurality of column plane read data bits being different from the expected value when the bit is associated with a second column plane.

17. The method of claim 11, further comprising, in response to the value of the bit of the plurality of column-plane read data bits being different from the expected value:

encoding the column plane bit error with a first value based on the respective column plane associated with the bit when all other bits of the plurality of column plane read data bits match the expected value; and

encoding the column plane error code with a second value in response to the value of the second bit of the plurality of column plane read data bits being different from the expected value when the second bit is associated with a respective column plane different from the bit.

18. The method of claim 11, further comprising serializing bits of the column plane error to provide to an output of the semiconductor device, internal logic for the semiconductor device, or any combination thereof.

19. The method of claim 11, wherein the output of the semiconductor device is a test data terminal.

20. The method of claim 11, further comprising: during a test operation, data is written to the array of memory cells of the semiconductor device prior to receiving the plurality of column plane read data bits.

Technical Field

The present application relates to semiconductor devices, and more particularly, to an apparatus and method for encoding column plane compression data.

Background

During production and prior to being placed into service, a semiconductor device (e.g., a device under test) may undergo a test operation to detect errors in the semiconductor device. In some examples, the test operation may include performing a write-read test that includes writing data to the memory cells, reading out the data, and verifying a match of the read data and the written data. However, for high density memory, reading all data from the semiconductor device can consume a significant amount of time and resources of the test equipment to send and process a large amount of memory during read-out.

Disclosure of Invention

An aspect of the present disclosure provides an apparatus, wherein the apparatus comprises: a compare circuit configured to receive a plurality of column plane read data bits during a test operation, each column plane read data bit associated with a respective column plane of the memory cell array, wherein the compare circuit is further configured to detect whether a value of a bit of the plurality of column plane read data bits differs from an expected value and provide error data based on the detection and based on the respective column plane of the memory cell array associated with the bit; and an encoder circuit configured to encode the column plane error based on the error data to provide to the data terminal.

Another aspect of the present disclosure provides a memory, wherein the memory includes: a memory cell array configured to store a plurality of data bits, each data bit associated with a respective column plane; and input/output circuitry including compression circuitry configured to provide error data based on a comparison between bits of a plurality of data bits received from the memory cell array and an expected value and based on respective column planes of the memory cell array associated with the bits, wherein the compression circuitry is further configured to encode column plane errors based on the error data for provision to the data terminals.

Another aspect of the present disclosure provides a method, wherein the method comprises: during a test operation of a compression circuit of a semiconductor device, receiving a plurality of column plane read data bits, each column plane read data bit associated with a respective column plane of a memory cell array of the semiconductor device; detecting whether a value of a bit of the plurality of column plane read data bits differs from an expected value; encoding a column plane error code based on detecting whether values of bits of a plurality of column plane read data bits have values different from expected values and based on respective column planes associated with the bits; and storing the column plane bit error at the semiconductor device.

Drawings

Fig. 1 is a block diagram of a semiconductor device according to a disclosed embodiment.

Fig. 2 is a schematic block diagram of a portion of an input/output circuit in accordance with an embodiment of the present disclosure.

Fig. 3 contains an exemplary timing diagram for serial transmission of column plane errors according to an embodiment of the present disclosure.

Fig. 4A-C contain tables of exemplary encodings of column-plane errors by an encoder circuit, according to embodiments of the present disclosure.

Fig. 5 is a flow diagram of an exemplary method of generating column plane errors in accordance with an embodiment of the present disclosure.

Detailed Description

Certain details are set forth below to provide a sufficient understanding of embodiments of the disclosure. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. Furthermore, the particular embodiments of the present disclosure described herein are provided by way of example and should not be used to limit the scope of the present disclosure to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring the disclosure.

Some materials described in this disclosure include circuitry of a semiconductor device including compression circuitry configured to compress output data during test operations. For example, during a test operation, data may be written to the memory cell array and then may be read out to verify whether the read data matches the write data. A mismatch between the read data and the write data may indicate a defect in a corresponding cell of the memory cell array. The semiconductor device may include column plane compression circuitry configured to perform a logical comparison between column plane read data bits or between column plane read data bits and expected data to detect errors. The expected data may be provided externally (e.g., via a tester) or may be stored internally in registers. Based on the comparison, the column plane compression circuitry may encode a column plane error code that provides an indication of the location of the error in the column plane data. Column plane errors may indicate whether there are no errors in the column plane data, which column plane has errors, whether there are errors on several column planes, error patterns, etc. Column plane errors may be provided to the tester via one or more input/output data terminals of the semiconductor device. In some examples, column plane errors may be provided to the tester via one or more test input/output data terminals dedicated to the semiconductor device during test operations. Providing a column plane error code that provides information about the detected error may improve the ability to determine the cause of the error as compared to test circuitry that provides a unit pass/fail flag for all column plane error data.

Fig. 1 is a schematic block diagram of a semiconductor device 100 according to an embodiment of the present disclosure. For example, the semiconductor device 100 may include a chip 135 and a ZQ Resistor (RZQ) 155. Chip 135 may include clock input circuit 105, internal clock generator 107, timing generator 109, address command input circuit 115, address decoder 120, command decoder 125, mode register data mask generator 126, a plurality of row decoders 130, memory cell array 145 including sense amplifiers 150 and transfer gates 195, a plurality of column decoders 140, a plurality of read/write amplifiers 165, input/output (I/O) circuitry 170, column plane compression circuitry 172, ZQ Resistors (RZQ)155, ZQ calibration circuitry 175, and voltage generator 190. The semiconductor device 100 may include a plurality of external terminals including address and command terminals coupled to a command/address bus 110, clock terminals CK and/CK, data terminals DQ, DQs and DM, power supply terminals VDD, VSS, VDDQ and VSSQ, and a calibration terminal ZQ. The chip 135 may be mounted on a substrate, such as a memory module substrate, a motherboard, or the like.

Memory cell array 145 includes a plurality of BANKs BANK0-N, each BANK0-N including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The number of BANKs BANK0-N may comprise a number of 2, 4, 8, 16, or any other BANKs. Each of BANKs BANK0-N may be divided into two or more memory planes (e.g., column planes). In some examples, each of BANKs BANK0-N may contain 2, 4, 8, 16, 32, etc. column planes. The selection of the word line WL of each bank is performed by the corresponding row decoder 130, and the selection of the bit line BL is performed by the corresponding column decoder 140. The plurality of sense amplifiers 150 are positioned for their corresponding bit lines BL and are coupled via transmission gates TG 195 that act as switches to at least one respective local I/O line that is further coupled to a respective one of at least two primary I/O line pairs.

The address/command input circuit 115 may receive an address signal and a bank address signal from the outside at a command/address terminal via the command/address bus 110 and transmit the address signal and the bank address signal to the address decoder 120. The address decoder 120 may decode address signals received from the address/command input circuit 115 and provide row address signals XADD to the row decoder 130 and column address signals YADD to the column decoder 140. The address decoder 120 may also receive bank address signals and provide the bank address signals BADD to the row decoder 130 and the column decoder 140.

Address/command input circuit 115 may receive command signals from the outside (e.g., memory controller 105) at command/address terminals via command/address bus 110 and provide the command signals to command decoder 125. The command decoder 125 may decode the command signals and provide various internal command signals. For example, the internal command signals may include a row command signal that selects a wordline, a column command signal (such as a read command or a write command) that selects a bitline, a mode register set command MRS that may cause a mode register to be set at the memory stored at the mode register data mask generator 126, and a ZQ calibration command ZQ _ com that may activate the ZQ calibration circuit 175.

Accordingly, when a read command is issued and provided to a row address and a column address in time, read data is read from the memory cells in the memory cell array 145 specified by the row address and the column address. The read/write amplifier 165 may receive read data DQ and provide the read data DQ to the IO circuit 170. The IO circuit 170 may supply read data DQ, and a data strobe signal at DQs and/or a data mask signal at DM to the outside via a data terminal DQ. Similarly, when a write command is issued and the row and column addresses are provided in time with the write command, and then input/output circuit 170 may receive the write data at data terminal DQ, as well as a data strobe signal at DQS and/or a data mask signal at DM, and provide the write data to memory cell array 145 via read/write amplifiers 165. Thus, write data can be written in the memory cell specified by the row address and the column address.

In some examples, IO circuitry 170 may include column plane compression circuitry 172 configured to compress output data during test operations. For example, during a test operation, data may be written to memory cell array 145 and then may be read out again to verify whether the read data matches the write data. A mismatch between the read data and the write data may indicate a defect in a corresponding cell of memory cell array 145. To detect errors, the column plane compression circuitry 172 may be configured to perform a logical comparison between bits of column plane read data read from the memory cell array 145, or between bits of column plane read data read from the memory cell array 145 and expected data. The expected data may be provided externally (e.g., via a tester) or may be stored internally in registers. Based on the comparison, the column plane compression circuit 172 may encode a column plane error code that provides an indication of the location of the error in the column plane data. Column plane errors may indicate whether there are no errors in the column plane data, which column plane has errors, whether there are errors on several column planes, error patterns, etc. The column plane compression circuit 172 and/or the IO circuit 170 may provide column plane errors to one or more data terminals DQ for access by a tester. In some examples, the column plane compression circuit 172 and/or the IO circuit 170 may provide column plane errors to one or more test input/output data terminals TDQs of the semiconductor device 100 that are dedicated during test operations. Providing column plane errors that provide information about detected errors may improve the ability to determine the cause of the error as compared to test circuitry that provides a unit pass/fail flag for all column plane error data and involves performing several separate column plane read operations to determine which column plane(s) fail.

Turning to the description of the external terminals included in the semiconductor device 100, the clock terminals CK and/CK may receive an external clock signal and a complementary external clock signal, respectively. An external clock signal (comprising a complementary external clock signal) may be provided to clock input circuitry 105. The clock input circuit 105 may receive an external clock signal and generate an internal clock signal ICLK. The clock input circuit 105 may provide the internal clock signal ICLK to the internal clock generator 107. The internal clock generator 107 may generate the phase-controlled internal clock signal LCLK based on the internal clock signal ICLK and the clock enable signal CKE received from the address/command input circuit 115. Although not limited thereto, a DLL circuit may be used as the internal clock generator 107. The internal clock generator 107 may provide the phase-controlled internal clock signal LCLK to the IO circuit 170 and the timing generator 109. The IO circuit 170 may determine the output timing of the read data using the phase controller internal clock signal LCLK as a timing signal. The timing generator 109 may receive the internal clock signal ICLK and generate various internal clock signals.

The power supply terminals may receive power supply voltages VDD and VSS. These power supply voltages VDD and VSS may be supplied to the voltage generator circuit 190. The voltage generator circuit 190 may generate various internal voltages based on the power supply voltages VDD and VSS: VPP, VOD, VARY, VPERI, and the like. The internal voltage VPP is mainly used for the row decoder 130, the internal voltages VOD and VARY are mainly used for the sense amplifiers 150 included in the memory cell array 145, and the internal voltage VPERI is used for many other circuit blocks. The power supply terminal may also receive supply voltages VDDQ and VSSQ. IO circuit 170 may receive supply voltages VDDQ and VSSQ. For example, the power supply voltages VDDQ and VSSQ may be the same voltages as the power supply voltages VDD and VSS, respectively. However, dedicated supply voltages VDDQ and VSSQ may be used for IO circuit 170 and ZQ calibration circuit 175.

The calibration terminal ZQ of the semiconductor memory device 100 may be coupled to the ZQ calibration circuit 175. The ZQ calibration circuit 175 may perform a calibration operation with reference to the impedance of the ZQ Resistor (RZQ) 155. In some examples, a ZQ Resistor (RZQ)155 may be mounted on a substrate coupled to the calibration terminal ZQ. For example, the ZQ Resistor (RZQ)155 may be coupled to a supply Voltage (VDDQ). The impedance code ZQCODE obtained by the calibration operation may be supplied to the IO circuit 170, and thus the impedance of an output buffer (not shown) included in the IO circuit 170 is specified.

Fig. 2 is a schematic block diagram of a portion of an IO circuit 270 in accordance with an embodiment of the present disclosure. For example, the IO circuit 270 may include a column plane compression circuit 272, a serializer circuit 274, and a data terminal DQ 276. The semiconductor device 100 of fig. 1 may implement a part of the IO circuit 270.

The column plane compression circuit 272 may be configured to receive column plane data CP0-CPN and ECC bits. In some examples, the CP0-CPN and ECC data may contain multiple bits of data for each column plane. In some instances, the semiconductor device may be implemented without an ECC plane. Thus, while the foregoing description contemplates the inclusion of ECC data in the column plane data CP0-CPN, it should be understood that implementations in which the column plane compression circuit 272 only receives the column plane data CP0-CPN are within the scope of the present disclosure. For example, for column plane 0, CP0 may contain multiple bits (e.g., 4, 8, 16, etc.); for column plane 1, CP1 may contain multiple bits (e.g., 4, 8, 16, etc.), and so on. Thus, in a specific non-limiting example, if each of the column planes and ECC circuits provide a corresponding 8-bit data, and there are 16 column planes in CP0-CPN, the CP0-CPN and ECC data may comprise 136-bit data.

The column plane compression circuit 272 may include a comparison circuit 222 and an encoder circuit 224. The compare circuit 222 may be configured to perform a comparison of the CP0-CPN and the ECC data to detect errors. The compare circuit 222 may determine whether the CP0-CPN and Error Correction Code (ECC) data contain errors by detecting which bits of the CP0-CPN and ECC data differ from expected values, and provide a respective CP0-CPN and ECC pass/fail flag (e.g., bit) for each of the column plane and ECC plane. In some examples, the expected value may be determined based on the logical values of the CP0-CPN and the majority bits of the ECC data. In other examples, the expected value may be provided to the comparison circuit 222 by the tester and/or may be stored or provided internally. The compare circuit 222 may set the CP0-CPN and ECC pass/fail flags for each column plane and ECC based on the detected errors.

The encoder circuit 224 may receive the CP0-CPN and/or ECC pass/fail flag and may encode CP errors (e.g., CP ERR0-CP ERRM) based on the values of the CP0-CPN and ECC pass/fail flag. CP errors with M +1 bits (e.g., CP ERR0-CP ERRM) contain fewer bits than the count of column planes and ECCs (e.g., N + 2). The encoded value of the CP error may indicate a pattern of no column plane failure, a single column plane failure, multiple column plane failures, or any combination thereof. For example, in the event of a single CP or ECC failure, encoder circuit 224 may encode the CP error with a value that identifies a particular column plane or ECC. In instances where more than one column plane fails, encoder circuitry 224 may encode a value indicating multiple column plane failures. In some instances, the failures of multiple column planes may have some logical relationship within the semiconductor device that indicates a failure mode (e.g., sharing a common control signal/line, etc.), and as such, the encoder circuit 224 may encode the CP error code as a value that indicates the failure mode. The encoder circuit 224 may provide the CP error code to the serializer circuit 274.

In some examples, serializer circuit 274 may receive CP error bits (e.g., CP ERR0-CP ERRM) in parallel and may serialize the CP error to provide to data terminal DQ 276. In other examples, the bits of the CP error to be output in parallel may be provided to the plurality of data terminals DQ 276 in parallel. In some examples, the CP error may be stored and/or used internally in addition to or instead of providing the CP error to data terminal DQ 276.

In operation, the column plane compression circuit 272 may be configured to compress CP0-CPN data during test operations. For example, during a test operation, data may be written to the memory cell array and then read out again to verify whether the read data matches the write data. In some examples, a mismatch between read data and write data may be used to indicate a defect in a corresponding cell of the memory cell array (e.g., when the mismatch is an unexpected or unexpected result). In some instances, a mismatch may indicate proper operation of various other functions and logic within the semiconductor device (e.g., when the mismatch is a desired or expected result). The column plane compression circuit 272 may be configured to perform a logical comparison between the CP0-CPN read from the memory cell array and the bits of the ECC data to detect errors and encode the CP error code to provide an indication of the location of the error in the column plane data.

The compare circuit 222 may determine whether the CP0-CPN and ECC data contain errors by determining that the bits of the CP0-CPN and ECC data are different from expected values. When a bit is detected to have a value other than the expected value, the compare circuit 222 may be configured to set one of the respective CP0-CPN and ECC pass/fail flags (e.g., bits) associated with the column plane or ECC plane containing the unexpected data. In some instances, errors may be detected based on logical bit-by-bit comparisons between bits. In some examples, the expected value may be determined based on the logical values of the CP0-CPN and the majority bits of the ECC data. Thus, if the two bits fail a logical bitwise comparison (e.g., an XOR or NAND bitwise comparison), the bit considered to fail may be based on which of the two bits has a logical value common to the selected group or most of all of the bits of CP0-CPN and ECC data. In other examples, the expected value may be provided to the comparison circuit 222 externally (e.g., via a tester), and/or may be set or stored internally.

The encoder circuit 224 may receive the CP0-CPN and the ECC pass/fail flag, and may encode CP errors based on the values of the CP0-CPN and the ECC pass/fail flag. In some examples, encoder circuit 224 includes logic to determine the encoded value of the CP error code. In other examples, based on the CP0-CPN and the ECC pass/fail flag, the encoder circuit 224 may look up the encoded value in a table. The encoded value of the CP error may indicate a pattern of no column plane or ECC failures, a single column plane failure, multiple column plane failures, or any combination thereof. For example, in the event of a single CP or ECC failure, encoder circuit 224 may encode the CP error with a value that identifies a particular column plane or ECC. In instances where more than one column plane fails, encoder circuitry 224 may encode a value indicating multiple column plane failures. In some instances, the failures of multiple column planes may have some logical relationship within the semiconductor device that indicates a failure mode (e.g., sharing a common control signal/line, etc.), and as such, the encoder circuit 224 may encode the CP error code as a value that indicates the failure mode. The encoder circuit 224 may provide the CP error code to the serializer circuit 274.

Fig. 4A-C contain tables 400, 401, and 402 of exemplary encoding of CP bit errors by encoder circuit 224, according to an embodiment of the present disclosure. The examples provided in fig. 4A through 4C are intended to cover one particular implementation. It should be understood that the encoding of CP errors may be applied to different implementations with more or fewer column planes, with or without ECC planes, with more or fewer CP error bits, etc., or any combination thereof, without departing from the scope of the present disclosure. Table 400 in fig. 4A depicts an exemplary CP error code for a semiconductor device containing 8 column planes and one ECC plane. The implementation of table 400 contains four bits for a total of 16 different encoding options. In the example of a semiconductor device containing eight column planes and one ECC plane, ten codes would be used (e.g., no errors, one code for each individual column plane, and one code for ECC), and six codes would remain available to encode other failure modes, such as multi-column plane failures, multi-column plane failure modes, a combination of ECC and column plane failures, and the like, or any combination thereof.

Table 401 in fig. 4B depicts an exemplary CP error code for a semiconductor device containing 16 column planes and one ECC. The implementation of table 401 contains five bits for a total of 32 different encoding options. In the example of a semiconductor device containing 16 column planes and one ECC, 18 codes would be used (e.g., no errors, one code for each individual column plane, and one code for ECC), and 14 codes would remain available to encode other failure modes, such as multi-column plane failures, multi-column plane failure modes, a combination of ECC and column plane failures, and the like, or any combination thereof.

Table 402 in fig. 4C depicts an exemplary multi-column plane CP error code for a semiconductor device containing 8 column planes and one ECC. Assuming that the first ten codes (e.g., b 0000-b 1010) are assigned to error-free, eight column planes and ECC (e.g., as shown in table 400 of fig. 4A), the eleventh code (e.g., b1011) may indicate a failure of both column planes 0 and 1, the twelfth code may indicate a failure of both column planes 2 and 3, and so on.

It should be noted that the coding examples provided in tables 400, 401, and 402 of fig. 4A through 4C are exemplary. Different encoding may be implemented without departing from the scope of the present disclosure. Further, more or fewer bits than described may be included in the CP bit error to allow for more or fewer coding options.

Returning to fig. 2, in some examples, serializer circuit 274 may receive CP error bits (e.g., CP ERR0-CP ERRM) in parallel and may serialize the CP error to provide to data terminal DQ 276. Fig. 3 contains an exemplary timing diagram 300 of serial transmission of CP errors according to an embodiment of the disclosure. At time T0, the semiconductor device receives an active command ACT to prepare the semiconductor device for a read operation. At times T1 and T2, the semiconductor device receives consecutive first read command RD0 and second read command RD1, respectively. At time T3 after the read latency RL delay, IO circuit 270 (e.g., or IO circuit 170 of fig. 1) begins to serially transmit the first CP error associated with the first read command RD0 at serializer circuit 274. The serialized first CP error code may be generated by the serializer circuit 274. Immediately after the last bit of the first CP error is sent at time T4, IO circuit 270 begins to serially send a second CP error associated with second read command RD1 at serializer circuit 274. The serialized second CP error code may be generated by the serializer circuit 274.

In other examples, the CP-error bits may be transmitted in parallel or partially in parallel via multiple data terminals DQ 276. Providing column plane errors that provide information about detected errors may improve the ability to determine the cause of the error as compared to test circuitry that provides a unit pass/fail flag for all column plane error data and involves performing several separate column plane read operations to determine which column plane(s) fail.

Fig. 5 is a flow diagram of an example method 500 of generating column plane errors, according to an embodiment of the present disclosure. Method 500 may be performed by IO circuit 170 of fig. 1 and/or IO circuit 270 of fig. 2.

The method 500 may include receiving a plurality of column plane read data bits during a test operation of a compression circuit of a memory device, each column plane read data bit associated with a respective column plane of a memory cell array of the memory device (at 510). The compression circuit may be included in the column plane compression circuit 172 of fig. 1 and/or the comparison circuit 222 of fig. 2. In some examples, the plurality of column plane read data bits may include the CP0-CPN of fig. 2 and ECC data. In some examples, method 500 may include writing desired data to a memory cell array of a semiconductor device prior to receiving a plurality of column plane read data bits during a test operation.

The method 500 may further include detecting whether a value of a bit of the plurality of column plane read data bits is different from an expected value (at 520). The detection may be performed by the comparison circuit 222 of fig. 2. In some examples, the compare circuitry 222 may provide error data based on a comparison between a bit of a plurality of column planes read data bits received from the memory cell array and an expected value and based on a respective column plane of the memory cell array associated with the bit. The error data may include the CP0-CPN of FIG. 2 and an ECC pass/fail flag. In some examples, method 500 may include receiving expected values of bits from a tester. In some examples, method 500 may include determining an expected value based on a logical bit-by-bit comparison between a plurality of column plane read data bits. In some examples, the logical bitwise comparison may include a bitwise XOR, a comparison, a bitwise NAND comparison, or a combination thereof between at least two of the plurality of column plane read data bits. In some examples, method 500 may include selecting one of the first logical value or the second logical value as the expected value based on whether more than half of the group of the plurality of column plane read data bits have the first logical value or the second logical value.

The method 500 may further include encoding (at 530) a column plane error code based on detecting whether values of bits of the plurality of column plane read data bits have values different from expected values and based on respective column planes associated with the bits. The encoding may be performed by the encoder circuit 224 of fig. 2. The column plane errors may comprise the CP errors of fig. 2 (e.g., CP ERR0-CP ERRM). In some instances, encoding may be performed based on tables 400, 401, and/or 402 of fig. 4A-4C. Other encoding schemes may be implemented without departing from the scope of the present disclosure. In some examples, method 500 may include encoding a column plane error code with a first value in response to a value of a bit of the multiple column plane read data bits being different from an expected value when the bit is associated with a first column plane, and encoding a column plane error code with a second value in response to the value of the bit of the multiple column plane read data bits being different from the expected value when the bit is associated with a second column plane.

In some examples, method 500 may include, in response to a value of a bit of the plurality of column planes of read data bits being different from a desired value: when all other bits of the plurality of column plane read data bits match the expected value, the column plane error code is encoded with a first value based on the respective column plane associated with the bit, and when a second bit is associated with a respective column plane different from the bit, the column plane error code is encoded with a second value in response to the value of the second bit of the plurality of column plane read data bits being different from the expected value.

The method 500 may further include storing the column plane bit errors at the semiconductor device (at 540). In some examples, method 500 may further include providing the column plane bit errors to an output of the semiconductor device and/or internal logic of the semiconductor device (e.g., error correction circuitry, row or column replacement logic, etc.). The output of the semiconductor device may include one or more of the data terminal DQ or the test data terminal TDQ of fig. 1 and/or the data terminal DQ 276 of fig. 2. In some examples, the output of the semiconductor device is a test data terminal or a data terminal. In some embodiments, method 500 may include serializing the bits of the column plane error to provide to an output of the semiconductor device, for internal logic of the semiconductor device, or any combination thereof. In some examples, serialization of the bits of the column plane error may be performed by the serializer circuit 274 of fig. 2.

Although certain preferred embodiments and examples have been described in detail, it will be understood by those skilled in the art that the scope of the disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications within the scope of the disclosure will be apparent to those skilled in the art. It is also contemplated that various combinations or sub-combinations of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Accordingly, the above-described specific disclosed embodiments should not limit the scope of at least some of the present disclosure.