Byte alignment method, device and equipment based on FPGA and storage medium
阅读说明：本技术 基于fpga的字节对齐方法、装置、设备及存储介质 (Byte alignment method, device and equipment based on FPGA and storage medium ) 是由 王文明 崔鲲 黄玮 潘龙 于 2021-01-29 设计创作，主要内容包括：本发明公开了一种基于FPGA的字节对齐方法、装置、设备及存储介质,该方法包括：接收串行数据流,串行数据流包括标志位,串行数据流是通过发送端的FPGA中内置的SERDES收发器将第一并行数据流转换得到,第一并行数据流包括多个并行传输二进制码的第一数据位,标志位为任意一个第一数据位,除标志位外的第一数据位用于传输有效载荷；通过接收端FPGA中内置的SERDES收发器将串行数据流转换为第二并行数据流；查询标志位在第二并行数据流中的位置,作为目标位置；基于目标位置对第二并行数据流进行字节调整,以使第二并行数据流与第一并行数据流对齐。本发明所提出的字节对齐方法占用数据传输的带宽较小,占用FPGA的资源较少,且操作简单,易于实现。(The invention discloses a byte alignment method, a byte alignment device, byte alignment equipment and a storage medium based on an FPGA (field programmable gate array), wherein the method comprises the following steps: receiving a serial data stream, wherein the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through a built-in SERDES transceiver in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload; converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in the receiving end FPGA; querying the position of the marker bit in the second parallel data stream as a target position; byte-justified second parallel data streams are based on the target location to align the second parallel data streams with the first parallel data streams. The byte alignment method provided by the invention occupies smaller bandwidth of data transmission, occupies less resources of the FPGA, and is simple to operate and easy to realize.)
1. An FPGA-based byte alignment method is characterized by comprising the following steps:
receiving a serial data stream, wherein the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through a built-in SERDES transceiver in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload;
converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in an FPGA of a receiving end;
inquiring the position of the zone bit in the second parallel data stream as a target position;
byte-adjusting the second parallel data stream based on the target position to align the second parallel data stream with the first parallel data stream.
2. The method of claim 1, wherein the second parallel data stream comprises a plurality of second data bits of a parallel transmission binary, the binary transmitted in the flag bit being set to 1;
the querying the position of the flag bit in the second parallel data stream as a target position includes:
counting the total number of binary codes continuously transmitted on each second data bit in the second parallel data stream as 1;
determining a position of the marker bit in the second parallel data stream as a target position based on the total number.
3. The method of claim 2, wherein the counting a total number of binary codes transmitted on each second data bit in the second parallel data stream that are consecutively 1 comprises:
configuring a counter for each second data bit in the second parallel data stream respectively;
if the binary code transmitted on the second data bit is 1, adding 1 to a counter corresponding to the second data bit;
if the binary code transmitted on the second data bit is 0, resetting the counter corresponding to the second data bit;
counting results of all the counters;
determining a total number of binary codes transmitted on each second data bit in the second parallel data stream as 1 in succession based on the counting result;
the method further comprises the following steps:
and if the counting results of all the counters are 0, determining that the second parallel data stream has error codes.
4. The method of claim 2, wherein all of the second data bits are ordered in a second parallel data stream;
the determining, as a target location, a location of the marker bit in the second parallel data stream based on the total number comprises:
if the total number reaches a preset threshold value, determining that the second data bits corresponding to the total number are flag bits of a receiving end;
and taking the position of the marker bit of the receiving end in a plurality of second data bits which are orderly arranged in the second parallel data stream as a target position.
5. The method of any of claims 1-4, wherein byte-adjusting the second parallel data stream based on the target location to align the second parallel data stream with the first parallel data stream comprises:
determining the position of the marker bit of the transmitting end in the first parallel data stream as an original position;
byte-adjusting the second parallel data stream based on a displacement difference between the target location and the origin location to align the second parallel data stream with the first parallel data stream;
alternatively, the first and second electrodes may be,
determining a byte range centered at the target position consisting of a plurality of second data bits surrounding the center;
byte-adjusting the second parallel data stream based on the byte range to align the second parallel data stream with the first parallel data stream.
6. The method of claim 5, wherein byte adjusting the second parallel data stream based on the displacement difference between the target location and the original location to align the second parallel data stream with the first parallel data stream comprises:
determining a position of a second data bit in the second parallel data stream corresponding to the original position as a reference position;
calculating the total number of second data bits with the difference between the target position and the reference position as a displacement difference;
performing byte shift adjustment on the second parallel data stream based on the displacement difference to align the second parallel data stream with the first parallel data stream.
7. The method of claim 5, wherein determining the byte range centered at the target position and consisting of a plurality of second data bits surrounding the center comprises:
querying the total number of first data bits in the first parallel data stream before the original position as a first numerical value;
querying the total number of first data bits after the original position in the first parallel data stream as a second numerical value;
screening a plurality of second data bits located before the target position from the second parallel data stream according to a first value to obtain a first packet;
screening a plurality of second data bits behind the target position from the second parallel data stream according to a second numerical value to obtain a second group;
and determining the range of all second data bits consisting of the first packet, the flag bit positioned at the target position and the second packet as a byte range.
8. An FPGA-based byte alignment apparatus, comprising:
the data receiving module is used for receiving a serial data stream, the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through a built-in SERDES transceiver in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of parallel transmission binary codes, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload;
the serial-parallel conversion module is used for converting the serial data stream into a second parallel data stream through an SERDES transceiver built in an FPGA of a receiving end;
the query module is used for querying the position of the marker bit in the second parallel data stream as a target position;
a byte alignment module, configured to perform byte adjustment on the second parallel data stream based on the target position, so as to align the second parallel data stream with the first parallel data stream.
9. A computer device, characterized in that the computer device comprises:
one or more processors;
a memory for storing one or more programs,
when executed by the one or more processors, cause the one or more processors to implement the FPGA-based byte alignment method of any one of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, implements the FPGA-based byte alignment method according to any one of claims 1 to 7.
Technical Field
The embodiment of the invention relates to a digital communication technology, in particular to a byte alignment method, a byte alignment device, byte alignment equipment and a storage medium based on an FPGA (field programmable gate array).
Background
With the rise of big data and the rapid development of information technology, the requirement of data transmission on bus bandwidth is higher and higher, and the development of parallel transmission technology is hindered by a series of problems of difficult time sequence synchronization, serious signal deviation, weak anti-interference capability, high design complexity and the like. Compared with the parallel transmission technology, the serial transmission technology has the advantages of less pins, strong expansion capability, and capability of providing a higher bandwidth than the parallel transmission by adopting a point-to-point connection mode, so the serial transmission technology is widely used in the field of embedded high-speed transmission.
In the data transmission process between the receiving end device with the FPGA and the sending end device with the FPGA, a process of converting parallel data into serial data and then converting serial data into parallel data is usually performed, the FPGA (Field Programmable Gate Array) has one or more SERDES (serial/Deserializer) transceivers built therein, and the SERDES transceivers include high-speed serial-parallel conversion circuits therein, which can provide a physical layer basis for various high-speed serial data transmission protocols. Since the SERDES transceiver can only perform random serial-to-parallel conversion on transmission data, in order to keep the parallel data of the receiving end consistent with the parallel data of the transmitting end, byte alignment needs to be performed on the parallel data of the receiving end and the parallel data of the transmitting end.
The traditional SERDES byte alignment method needs to insert the start bit and the end bit, but the method occupies one eighth of the total bandwidth of data transmission, or 8B/10B coding is adopted, but one quarter of the total bandwidth of data transmission needs to be additionally increased. The existing byte alignment method is to distinguish the boundary of the serial data stream by encoding the data stream and adding a start bit, an end bit and a characteristic character, but the encoding mode can generate larger extra cost and occupy limited bandwidth resources.
Disclosure of Invention
The invention provides a byte alignment method, a byte alignment device, byte alignment equipment and a storage medium based on an FPGA (field programmable gate array), which aim to solve the problem that the existing byte alignment method occupies larger bandwidth resources.
In a first aspect, an embodiment of the present invention provides a byte alignment method based on an FPGA, where the method includes:
receiving a serial data stream, wherein the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through a built-in SERDES transceiver in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload;
converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in an FPGA of a receiving end;
inquiring the position of the zone bit in the second parallel data stream as a target position;
byte-adjusting the second parallel data stream based on the target position to align the second parallel data stream with the first parallel data stream.
In a second aspect, an embodiment of the present invention further provides an FPGA-based byte alignment apparatus, where the apparatus includes:
the data receiving module is used for receiving a serial data stream, the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through a built-in SERDES transceiver in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of parallel transmission binary codes, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload;
the serial-parallel conversion module is used for converting the serial data stream into a second parallel data stream through an SERDES transceiver built in an FPGA of a receiving end;
the query module is used for querying the position of the marker bit in the second parallel data stream as a target position;
a byte alignment module, configured to perform byte adjustment on the second parallel data stream based on the target position, so as to align the second parallel data stream with the first parallel data stream.
In a third aspect, an embodiment of the present invention further provides a computer device, where the computer device includes:
one or more processors;
a memory for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the FPGA-based byte alignment method of the first aspect.
In a fourth aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the FPGA-based byte alignment method according to the first aspect.
The method comprises the steps that a serial data stream is received, the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through an SERDES transceiver arranged in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload; converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in the receiving end FPGA; querying the position of the marker bit in the second parallel data stream as a target position; byte-justified second parallel data streams are based on the target location to align the second parallel data streams with the first parallel data streams. The byte alignment method provided by the invention does not need to carry out additional coding and decoding operations on data transmitted between the sending end and the receiving end, and compared with the mode of realizing the byte alignment of the data of the sending end and the receiving end according to the coding method in the prior art, the method of the invention occupies smaller bandwidth of data transmission, occupies fewer resources of an FPGA, is simple to operate and is easy to realize.
Drawings
Fig. 1 is a flowchart of a byte alignment method based on an FPGA according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a byte alignment method based on an FPGA according to an embodiment of the present invention;
fig. 3 is a schematic diagram of data stream transmission according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a byte alignment apparatus based on an FPGA according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a computer device according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
It should be noted that: in the description of the embodiments of the present invention, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not intended to indicate or imply relative importance.
Example one
Fig. 1 is a flowchart of an FPGA-based byte alignment method according to an embodiment of the present invention, where the embodiment is applicable to a case where an FPGA does not use an additional encoding function and performs boundary differentiation on a serial data stream into a parallel data stream, and the method may be executed by an FPGA-based byte alignment apparatus, and the FPGA-based byte alignment apparatus may be implemented by software and/or hardware and may be configured in a computer device, such as a server, a workstation, a personal computer, and the like, and the method specifically includes the following steps:
s101, receiving a serial data stream.
In this embodiment, the receiving end receives a serial data stream sent by an FPGA interface of the sending end, where the serial data stream includes a flag bit, the serial data stream is obtained by converting a first parallel data stream of the sending end through an SERDES transceiver built in the FPGA of the sending end, the first parallel data stream includes a plurality of first data bits of a parallel transmission binary code, the flag bit may be any one of the first data bits, and the other first data bits except the flag bit are used for transmitting a payload, where the payload refers to a packet having valid data information in a data frame transmitted by the sending end.
In this embodiment, the first data bit is a data bit (bit) and is a minimum unit of data storage inside the computer, the first parallel data stream is a parallel data stream of the transmitting end, the parallel data stream is a multiplexed parallel data stream, and each data stream occupies a fixed data bit.
The method of the invention does not need to carry out coding operation in the process of converting the first parallel data stream into the serial data stream, and only needs to select any one first data bit in the first parallel data stream as a flag bit and fixedly set the binary code transmitted in the flag bit to be 1. For example, the first parallel data stream is a data stream 16 bits wide, and includes 16 data bits, any one of the data bits may be selected to be "1", for example, the bit 15 is selected to be all "1", the bits 0-14 are used to transmit the payload, since the payload may not be a continuous "1", the bits 0-14 and the bit 15 may be distinguished, and the bit 15 is a flag bit.
S102, converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in the FPGA of the receiving end.
In this embodiment, the second parallel data stream comprises a plurality of second data bits of the parallel transmission binary code. The essence of the second data bit is also a data bit (bit) which is the minimum unit of data storage inside the computer, the essence of the second parallel data stream and the first parallel data stream are both parallel data streams, and the "first" and "second" are used only to distinguish the parallel data streams of the transmitting end and the receiving end.
SERDES is an english abbreviation of Serializer and Deserializer, and is suitable for the case of high-speed transmission. The SERDES transceiver is further explained in the function of the embodiment, and the SERDES transceiver consists of two parts, namely a serial sending unit Serializer as a sending end and a high-speed clock for modulating a coded data stream; the connection end is a serial receiving unit Deserializer, and the main function of the serial receiving unit Deserializer is to recover a clock signal from a data stream and demodulate and restore data. In one example, 10 signal lines of 100MHZ in the sending end device are connected to the SERDES device, the SERDES device generates a serial data stream, and a clock signal is also modulated in the serial data stream; at the receiving end, the parallel data stream and clock signal are recovered through a SERDES device. The application of the SERDES technology well solves the bottleneck of data transmission of a high-speed system (particularly the application of backboard transmission), saves the area of a single board, improves the stability of the system and is a powerful support for designing the high-speed system.
S103, inquiring the position of the flag bit in the second parallel data stream as a target position.
In an implementation manner of this embodiment, a total number of binary codes continuously transmitted on each second data bit in the second parallel data stream may be counted as 1; the position of the marker bit in the second parallel data stream is determined as the target position based on the total number.
In an example, a plurality of counters may be configured at the receiving end, and the counters are used to count the number of binary codes continuously 1 transmitted in the second parallel data stream, and the specific steps include:
configuring a counter for each second data bit in the second parallel data stream; if the binary code transmitted on the second data bit is 1, adding 1 to the counter corresponding to the second data bit; if the binary code transmitted on the second data bit is 0, resetting the counter corresponding to the second data bit; counting results of all counters; and determining the total number of the binary codes which are continuously 1 and are transmitted on each second data bit in the second parallel data stream based on the counting result. It should be noted that, on the same second data bit of the second parallel data stream, as long as it is detected that the binary code transmitted at the current time of the second data bit is 0, the counter matched with the second data bit will be cleared.
In an example, if the count results of all the counters are not all zero, the determining, based on the total number, the position of the flag bit sent by the sender in the second parallel data stream may specifically include:
if the total number reaches a preset threshold value, determining a second data bit corresponding to the total number as a marker bit of the receiving end; and taking the position of the marker bit of the receiving end in the second parallel data stream in the plurality of second data bits which are orderly arranged as a target position.
In this example, the preset threshold may be set as an upper limit value of the counter, for example, a 12-bit counter may be set, and when the accumulated value of the counter is "111111111111", the second data bit corresponding to the counter is considered as a flag bit transmitted from the transmitting end to the receiving end.
And S104, adjusting the second parallel data stream based on the target position so as to align the second parallel data stream with the first parallel data stream.
In an implementation manner of this embodiment, a position of a flag bit of a sending end in the first parallel data stream may be determined as an original position; byte-adjusting the second parallel data stream based on a displacement difference between the target location and the origin location to align the second parallel data stream with the first parallel data stream.
The implementation method comprises the following specific steps: determining the position of a marker bit of a sending end in the first parallel data stream as an original position; determining a position of a second data bit in the second parallel data stream corresponding to the original position as a reference position; calculating the total number of second data bits with the difference between the target position and the reference position as a displacement difference; byte shift adjustments are made to the second parallel data stream based on the displacement differences to align the second parallel data stream with the first parallel data stream.
In another implementation manner of this embodiment, the position of the flag bit of the sending end in the first parallel data stream may be determined as an original position; determining a byte range centered at the target position and composed of a plurality of second data bits surrounding the center; byte adjustments are made to the second parallel data stream based on the byte range to align the second parallel data stream with the first parallel data stream.
The implementation method comprises the following specific steps: determining the position of a marker bit of a sending end in the first parallel data stream as an original position; querying the total number of first data bits in the first parallel data stream before the original position as a first numerical value; querying the total number of first data bits after the original position in the first parallel data stream as a second numerical value; screening a plurality of second data bits located before the target position from the second parallel data stream according to the first value to obtain a first packet; screening a plurality of second data bits behind the target position from the second parallel data stream according to the second numerical value to obtain a second group; determining the range of all second data bits consisting of the first packet, the flag bit positioned at the target position and the second packet as a byte range; byte adjustments are made to the second parallel data stream based on the byte range to align the second parallel data stream with the first parallel data stream.
To facilitate understanding by those skilled in the art, the method of the present invention is illustrated below by a specific example.
As shown in fig. 2, a first data bit is arbitrarily selected as a flag bit in a first parallel data stream at the transmitting end, the first parallel data stream in this example is 16-bit parallel data, if a bit 15 is selected as a flag bit, all bits 15 are "1", bits 0 to 14 are used for transmitting the payload, and since the payload cannot be a continuous "1", bits 0 to 14 and bit 15 can be distinguished.
In fig. 2, a first parallel data stream is converted into a serial data stream by an SERDES transceiver in an FPGA of a sending end device, a receiving end device receives the serial data stream, and randomly deserializes the serial data stream by the SERDES transceiver in the FPGA of the receiving end device, and in the process of deserializing, since data bits are randomly shifted (as shown in fig. 3, the first parallel data stream of the sending end is deserialized to obtain the serial data stream, and after the serial data stream is deserialized by the receiving end to obtain a second parallel data stream, the first data bit of the first parallel data stream is randomly shifted in the second parallel data stream after being data converted), the second data bit of the second parallel data stream obtained by the receiving end needs to be readjusted to obtain correct data consistent with the first parallel data stream of the sending end.
The second parallel data stream of the receiving end is a 16-bit data stream, which includes 16 second data bits, and the data bits are sorted from the lower bit to the upper bit into bits 0-15, and 16 12-bit counters are used at the receiving end to monitor the number of consecutive "1" on bits 0-15, if the binary code on bits 0-15 is "1", the corresponding counter accumulates 1, and if the binary code on bits 0-15 is "0", the corresponding counter is cleared. When the accumulated value of the counter is "111111111111", the second digit corresponding to the counter is regarded as the bit 15 (first data bit) of the transmitting end, and the second digit is regarded as the flag bit of the receiving end, so as to determine the target position of the flag bit of the receiving end, where the target position may be any one second data bit in the second parallel data stream, for example, any one of the bits 0 to 15.
An original position (in this example, bit 15) where the flag bit of the sending end is located is determined, byte shift adjustment is performed on the second parallel data stream based on a displacement difference between the target position and the original position, specifically, a reference position where the second data bit corresponding to the original position is located may be queried in the second parallel data stream, the flag bit of the receiving end is moved to the reference position, and corresponding shift is performed on other second data bits, so that the second parallel data stream of the receiving end is aligned with the first parallel data stream of the sending end.
In this example, the second data bit of the second parallel data stream may be adjusted by means of a buffer array, a byte buffer is first performed on the second parallel data stream at the receiving end, a data frame transmitted by the second parallel data stream at the previous time is buffered into the first array buf _ data [15:0], a data frame newly received by the second parallel data stream at the current time is stored into the second array data [15:0], a data frame after byte alignment is stored into the third array adj _ data [15:0], and a byte shift operation is specifically described below.
In this example, if bit 0 at the receiving end is a flag bit, data [0] is provided to adj _ data [15], and buf _ data [15:1] is provided to adj _ data [14:0 ].
In this example, if the receiver bit 1 is a flag bit, data [1:0] to adj _ data [15:14], buf _ data [15:2] is sent to adj _ data [13:0 ].
In this example, if the receiver bit 2 is a flag bit, data [2:0] to adj _ data [15:13], buf _ data [15:3] is sent to adj _ data [12:0 ].
In this example, if the receiver bit 3 is a flag bit, data [3:0] to adj _ data [15:12], buf _ data [15:4] is supplied to adj _ data [11:0 ].
In this example, if the receiver bit 4 is a flag bit, data [4:0] to adj _ data [15:11], buf _ data [15:5] is sent to adj _ data [10:0 ].
In this example, if the receiver bit 5 is a flag bit, data [5:0] to adj _ data [15:10], buf _ data [15:6] is sent to adj _ data [9:0 ].
In this example, if the receiver bit 6 is a flag bit, data [6:0] to adj _ data [15:9] buf _ data [15:7] to adj _ data [8:0 ].
In this example, if the receiver bit 7 is a flag bit, data [7:0] to adj _ data [15:8], buf _ data [15:8] is sent to adj _ data [7:0 ].
In this example, if the receiver bit 8 is a flag bit, data [8:0] to adj _ data [15:7], buf _ data [15:9] is sent to adj _ data [6:0 ].
In this example, if the receiver bit 9 is a flag bit, data [9:0] to adj _ data [15:6] buf _ data [15:10] to adj _ data [5:0 ].
In this example, if the receiver bit 10 is a flag bit, data [10:0] to adj _ data [15:5], buf _ data [15:11] is sent to adj _ data [4:0 ].
In this example, if the receiver bit 11 is a flag bit, data [11:0] to adj _ data [15:4] buf _ data [15:12] to adj _ data [3:0 ].
In this example, if the receiver bit 12 is a flag bit, data [12:0] to adj _ data [15:3] buf _ data [15:13] to adj _ data [2:0 ].
In this example, if the receiver bit 13 is a flag bit, data [13:0] to adj _ data [15:2, buf _ data [15:14] to adj _ data [1:0 ].
In this example, if the receiver bit 14 is a flag bit, data [14:0] to adj _ data [15:1], buf _ data [15] is supplied to adj _ data [0 ].
In this example, if the receiver bit 15 is a flag bit, data [15:0 is provided to adj _ data [15:0 ].
The method comprises the steps that a serial data stream is received, the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through an SERDES transceiver arranged in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload; converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in the receiving end FPGA; querying the position of the marker bit in the second parallel data stream as a target position; byte-justified second parallel data streams are based on the target location to align the second parallel data streams with the first parallel data streams. The byte alignment method provided by the invention does not need to carry out additional coding and decoding operations on data transmitted between the sending end and the receiving end, and compared with the mode of realizing the byte alignment of the data of the sending end and the receiving end according to the coding method in the prior art, the method of the invention occupies smaller bandwidth of data transmission, occupies fewer resources of an FPGA, is simple to operate and is easy to realize.
Example two
Fig. 4 is a schematic structural diagram of a byte alignment apparatus based on an FPGA according to a second embodiment of the present invention, where the apparatus may specifically include the following modules:
a data receiving module 401, configured to receive a serial data stream, where the serial data stream includes a flag bit, the serial data stream is obtained by converting a first parallel data stream through a SERDES transceiver built in an FPGA of a sending end, the first parallel data stream includes a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload;
a serial-to-parallel conversion module 402, configured to convert the serial data stream into a second parallel data stream through a SERDES transceiver built in an FPGA at a receiving end;
a query module 403, configured to query a position of the flag bit in the second parallel data stream as a target position;
a byte alignment module 404, configured to byte adjust the second parallel data stream based on the target position to align the second parallel data stream with the first parallel data stream.
In one embodiment of the invention, the second parallel data stream comprises a plurality of second data bits of the binary code transmitted in parallel, the binary code transmitted in the flag bit is set to 1; the query module 403 includes:
the statistic submodule is used for counting the total number of binary codes continuously transmitted on each second data bit in the second parallel data stream to be 1;
and the position confirming submodule is used for determining the position of the marker bit in the second parallel data stream as a target position based on the total number.
In one embodiment of the invention, the statistics submodule includes:
a counter allocation unit, configured to configure a counter for each second data bit in the second parallel data stream respectively;
a counter accumulation unit, configured to add 1 to a counter corresponding to the second data bit if the binary code transmitted on the second data bit is 1;
the counter resetting unit is used for resetting the counter corresponding to the second data bit if the binary code transmitted on the second data bit is 0;
a counting result counting unit for counting the counting results of all the counters;
and the counting result determining unit is used for determining the total number of the binary codes which are continuously 1 and are transmitted on each second data bit in the second parallel data stream based on the counting result.
In one embodiment of the invention, the apparatus further comprises:
and the abnormity determining module is used for determining that the second parallel data stream has error codes if the counting results of all the counters are 0.
In one embodiment of the invention, all of the second data bits are ordered in the second parallel data stream; the position confirmation submodule includes:
a flag bit determining unit, configured to determine that the second data bits corresponding to the total number are flag bits of a receiving end if the total number reaches a preset threshold;
and the target position determining unit is used for taking the position of the marker bit of the receiving end in a plurality of second data bits which are orderly arranged in the second parallel data stream as a target position.
In one embodiment of the present invention, the byte alignment module 404 includes:
an original position determining submodule, configured to determine a position of a flag bit of the sending end in the first parallel data stream, as an original position;
a first byte alignment submodule configured to perform byte adjustment on the second parallel data stream based on a displacement difference between the target position and the original position, so as to align the second parallel data stream with the first parallel data stream;
alternatively, the first and second electrodes may be,
a byte range determination submodule for determining a byte range made up of a plurality of second data bits around the center, centered on the target position;
a second byte alignment submodule configured to perform byte adjustment on the second parallel data stream based on the byte range, so as to align the second parallel data stream with the first parallel data stream.
In one embodiment of the invention, the first byte alignment submodule comprises:
a reference position determination unit for determining a position of a second data bit corresponding to the original position in the second parallel data stream as a reference position;
a displacement difference calculation unit for calculating the total number of second data bits having a difference between the target position and the reference position as a displacement difference;
a shift adjusting unit, configured to perform byte shift adjustment on the second parallel data stream based on the shift difference, so as to align the second parallel data stream with the first parallel data stream.
In one embodiment of the present invention, the byte range determination submodule includes:
a first value determining unit, configured to query, as a first value, a total number of first data bits in the first parallel data stream before the original position;
a second numerical value determining unit, configured to query, as a second numerical value, a total number of first data bits located after the original position in the first parallel data stream;
a first packet determining unit, configured to screen a plurality of second data bits located before the target position from the second parallel data stream according to a first value, so as to obtain a first packet;
a second grouping determination unit, configured to screen a plurality of second data bits located after the target position from the second parallel data stream according to a second value to obtain a second grouping;
a byte range determination unit, configured to determine, as a byte range, a range of all second data bits that are formed by the first packet, the flag bit located at the target location, and the second packet.
The byte alignment device based on the FPGA provided by the embodiment of the invention can execute the byte alignment method based on the FPGA provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method.
EXAMPLE III
Fig. 5 is a schematic structural diagram of a computer apparatus according to a third embodiment of the present invention, as shown in fig. 5, the computer apparatus includes a processor 500, a memory 501, a communication module 502, an input device 503, and an output device 504; the number of the processors 500 in the computer device may be one or more, and one processor 500 is taken as an example in fig. 5; the processor 500, the memory 501, the communication module 502, the input device 503 and the output device 504 in the computer apparatus may be connected by a bus or other means, and fig. 5 illustrates the connection by a bus as an example.
The memory 501 is a computer-readable storage medium, and can be used for storing software programs, computer-executable programs, and modules, such as modules corresponding to the FPGA-based byte alignment method in the embodiment of the present invention (for example, the data receiving module 401, the serial-to-parallel conversion module 402, the query module 403, and the byte alignment module 404 in the FPGA-based byte alignment apparatus shown in fig. 4). The processor 500 executes various functional applications and data processing of the computer device by running software programs, instructions and modules stored in the memory 501, namely, implementing the above-mentioned FPGA-based byte alignment method.
The memory 501 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the memory 501 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the memory 501 may further include memory located remotely from the processor 500, which may be connected to a computer device through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
And the communication module 502 is used for establishing connection with the display screen and realizing data interaction with the display screen.
The input device 503 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus.
The output device 504 may include a display device such as a display screen.
The specific composition of the input device 503 and the output device 504 can be set according to actual conditions.
The computer device provided by the embodiment of the invention can execute the byte alignment method based on the FPGA provided by any embodiment of the invention, and has corresponding functions and beneficial effects.
Example four
The fourth embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the method for byte alignment based on an FPGA of any one of the embodiments is implemented.
The method comprises the following steps:
receiving a serial data stream, wherein the serial data stream comprises a flag bit, the serial data stream is obtained by converting a first parallel data stream through a built-in SERDES transceiver in an FPGA of a sending end, the first parallel data stream comprises a plurality of first data bits of a parallel transmission binary code, the flag bit is any one of the first data bits, and the first data bits except the flag bit are used for transmitting a payload;
converting the serial data stream into a second parallel data stream through a built-in SERDES transceiver in an FPGA of a receiving end;
inquiring the position of the zone bit in the second parallel data stream as a target position;
byte-adjusting the second parallel data stream based on the target position to align the second parallel data stream with the first parallel data stream.
Of course, the computer program of the computer-readable storage medium provided in the embodiments of the present invention is not limited to the method operations described above, and may also perform related operations in the FPGA-based byte alignment method provided in any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
It should be noted that, in the embodiment of the byte alignment apparatus based on the FPGA, each unit and each module included in the embodiment are only divided according to functional logic, but are not limited to the above division, as long as the corresponding function can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.