阅读说明：本技术 一种抗单粒子翻转的dsp加固电路 (DSP (digital signal processor) reinforcement circuit capable of resisting single event upset ) 是由 薛海卫 于 2020-12-18 设计创作，主要内容包括：本发明公开一种抗单粒子翻转的DSP加固电路,属于数字信号处理器抗辐射领域,包括DSP内核、片内同步存储器、时钟系统、片内数据接口、片内地址接口、外部存储器接口、外设数据总线和外设地址总线；所述片内数据接口连接外设数据总线,片内地址接口连接外设地址总线；DSP内核通过片内数据接口、片内地址接口读写片内同步存储器,存取运行的数据和程序；DSP内核通过外部存储器接口读写片外存储空间的指令或数据,外部存储器接口中的数据通过片内数据接口送入DSP内核中；外部存储器接口中的地址通过片内地址接口由DSP内核送出；DSP内核通过片内数据接口和片内地址接口配置外设寄存器,使DSP加固电路与外界具有串口通信、运动控制、定时及中断的功能。(The invention discloses a single event upset resistant DSP (digital signal processor) reinforcement circuit, which belongs to the field of radiation resistance of a digital signal processor and comprises a DSP core, an on-chip synchronous memory, a clock system, an on-chip data interface, an on-chip address interface, an external memory interface, an external data bus and an external address bus; the on-chip data interface is connected with a peripheral data bus, and the on-chip address interface is connected with a peripheral address bus; the DSP core reads and writes the synchronous memory in the chip through the data interface and the address interface in the chip, and accesses the running data and program; the DSP core reads and writes instructions or data of an off-chip storage space through an external memory interface, and the data in the external memory interface is sent into the DSP core through an on-chip data interface; the address in the external memory interface is sent out by the DSP kernel through the on-chip address interface; the DSP kernel configures a peripheral register through an in-chip data interface and an in-chip address interface, so that the DSP reinforced circuit has the functions of serial port communication, motion control, timing and interruption with the outside.)

1. A DSP (digital signal processor) reinforcement circuit resisting single event upset is characterized by comprising a DSP core, an on-chip synchronous memory, a clock system, an on-chip data interface, an on-chip address interface, an external memory interface, an external data bus and an external address bus;

the on-chip data interface is connected with a peripheral data bus, and the on-chip address interface is connected with a peripheral address bus; the DSP core reads and writes the synchronous memory in the chip through the data interface and the address interface in the chip, and accesses the running data and program;

the DSP core reads and writes instructions or data of an off-chip storage space through an external memory interface, and the data in the external memory interface is sent into the DSP core through an on-chip data interface; the address in the external memory interface is sent out by the DSP kernel through the on-chip address interface;

the DSP kernel configures a peripheral register through an in-chip data interface and an in-chip address interface, so that the DSP reinforced circuit has the functions of serial port communication, motion control, timing and interruption with the outside.

2. The single event upset resistant DSP strengthening circuit of claim 1, wherein the on-chip synchronous memory adopts a 12-pipe DICE unit structure for single event upset resistance strengthening; the on-chip synchronous memory comprises a data input latch, an address row-column decoding circuit, clock logic, a word line driver, a write driver circuit, a DICE bit storage unit, a sensitive amplifier and a data output buffer;

the DICE bit storage unit is reinforced by a 12-pipe DICE structure with separated bit lines; the data input latch adopts a dual-mode redundancy and DICE latch structure, and the address input latch adopts a DICE latch structure.

3. The single event upset resistant DSP ruggedization circuit of claim 2, wherein the clock logic is in a filter circuit configuration and the sense amplifier and the data out buffer are in a DICE ruggedization with filtering to filter out single event generated glitches in the clock and data readout path.

4. The single event upset resistant DSP strengthening circuit of claim 1, wherein the clock system is strengthened using a three-mode PLL; the clock system comprises three PLL circuits, three mode selectors and a filter circuit; the clock outputs of the same three PLL are connected to a three-mode selector, and the output of the three-mode selector is used as the clock of the whole DSP reinforcing circuit; the clock from the three-mode selector is sent to the internal clock network after passing through the filter circuit so as to filter transient pulse interference generated on the clock network by the single event effect.

5. The single event upset resistant DSP strengthening circuit of claim 4, wherein the path lengths of the clock outputs of the three-way PLL to the input terminals of the three mode selectors are consistent, and the difference of the clock delays caused by the path difference between the three-way PLL and the three mode selectors is prevented.

6. The single event upset resistant DSP strengthening circuit of claim 1, wherein the single event upset resistant DSP strengthening circuit further comprises an on-chip bus interface with EDAC, the on-chip bus interface with EDAC comprising the on-chip data interface and an on-chip address interface; the on-chip bus interface with the EDAC comprises a first output data register, a first EDAC coding module, a first input data register, a first EDAC decoding and error correcting module, a selector MUX1/MUX2/MUX3, a peripheral data bus, an output address register, a second EDAC coding module and a peripheral address bus;

when the DSP core writes data to the peripheral, 3 independent data buses DRDB, DWDB and PRDB are multiplexed to the core data bus through a selector MUX1, 32-bit data are written into a first output data register and then enter a first EDAC coding module for coding, and coded output data comprising data bits and check bits are formed; the coded data is transmitted to the peripheral interface through a peripheral data bus;

when the DSP core receives the coded data on the peripheral data bus, the first EDAC decoding and error correcting module decodes the 32-bit received data, regenerates the check bit, and generates a syndrome by performing XOR operation on the newly generated check bit and the original check bit; the first EDAC decoding and error correcting module generates error-corrected data and a data selection signal, if a new check bit is consistent with an original check bit, the received data is not overturned, and the MUX2 is controlled by the data selection signal to select coded data which does not need error correction, and the coded data is directly input into a first input data register and is placed on a kernel data bus; if the new check bit is not consistent with the original check bit, the received data is inverted, the error bit is inverted and then written again, the MUX2 is controlled by the data selection signal to select the data after error correction, the data is sent to the first input data register to be stored, and then the data is input to the kernel data bus.

7. The single event upset resistant DSP reinforcement circuit of claim 6, wherein an address bus interface in the DSP core only sends addresses to an external address bus, 3 independent address buses PAB, DWAB, DRAB are multiplexed to the core address bus through a selector MUX3, the core address bus puts the addresses into a first output address register, the addresses in the first output address register are encoded through a second EDAC encoding module to form encoded addresses, and the encoded addresses are transmitted to an external address interface through an external address bus.

8. The single event upset resistant DSP reinforcement circuit of claim 1, wherein an external memory interface interacting with an off-chip data program is reinforced by EDAC error correction and detection technology; the external memory interface comprises a second input data register, a third EDAC coding module, a second output data register, a second EDAC decoding and error correcting module, a selector MUX4/MUX5, an off-chip data interface, a second output address register, a third EDAC decoding and error correcting module and an off-chip address interface;

when the DSP core reads data or instructions from the off-chip storage space through the external memory interface, the external memory interface stores the data or instructions on the off-chip data interface into a second input data register, the data or instructions in the second input data register are coded through a third EDAC coding module, and the coded data are sent to an external data bus;

when the DSP core sends data to an external memory interface through a peripheral data bus, the data in the second output data register is decoded through a second EDAC decoding and error correcting module to generate a new check bit, and the newly generated check bit and the original check bit are subjected to XOR operation to generate a checker; if the new check bit is consistent with the original check bit, the transmitted data is not turned over, and the data in the second output data register is directly transmitted to an off-chip data interface without error correction; if the new check bit is inconsistent with the original check bit, the sent data is overturned, the data is rewritten after the error-out bit is inverted, the MUX4 is controlled through the data selection signal to select the data after error correction, the data is sent to the second input data register to be stored, and then the data is output to the off-chip data interface, so that the error correction and detection and the sending and receiving of the EDAC of the off-chip data are realized;

when the DSP core sends an address to the external memory interface through the peripheral address bus, the external memory interface receives an EDAC encoded address on the peripheral address bus, the address is stored in the second output address register through the MUX5, the address in the second output address register regenerates a check bit through the third EDAC decoding and error correcting module, and the newly generated check bit and the original check bit are subjected to XOR operation to generate a syndrome; if the new check bit is consistent with the original check bit, the received address is not inverted, and the address in the second output address register is directly sent to the off-chip address bus without error correction; if the new check bit is inconsistent with the original check bit, the sent address is inverted, the error address bit is inverted and then written again, the MUX5 is controlled by the data selection signal to select the address after error correction, the address is stored in the second output address register and then output to the off-chip address bus; and error correction and detection and sending of the EDAC of the off-chip address are realized.

9. The single event upset resistant DSP reinforcement circuit of claim 1, wherein the peripheral registers comprise a field bus ECAN, a multi-channel buffer McBSP, a serial peripheral interface SPI, a serial communication interface SCI, a pulse width modulation PWM, a capture unit CAP, a quadrature code QEP, a timer, and a general purpose GPIO.

Technical Field

The invention relates to the technical field of radiation resistance of digital signal processors, in particular to a DSP (digital signal processor) reinforcement circuit capable of resisting single event upset.

Background

In a space radiation environment, the single event effect of the integrated circuit mainly comprises the phenomena of single event upset, single event transient, single event latch-up and the like. When high-energy particles hit a storage area of a chip, an instantaneous current pulse directly acts on a storage unit, so that the state of the storage unit is changed, and stored data is inverted, which is a Single Event Upset (SEU). A DSP (Digital Signal processor) chip in a spacecraft is a core device for data processing and communication control, and high-energy particles such as plasma, protons, electrons, and heavy ions in an aerospace space bombard a DSP circuit, which easily causes a single-particle upset in the DSP circuit. For DSP circuits, single event upsets occur primarily in SRAM memory regions and various register regions within the circuit. The single event upset occurs in the state machines of key components such as the instruction fetching, instruction decoding and pipeline execution of the DSP, which can cause the error of the DSP instruction execution function, the runaway of the DSP program, the interruption of the single event function, the instability and even the failure of the DSP circuit operation, and the safety and the reliability of the spacecraft are seriously influenced.

The industrial grade DSP circuit can generate a large amount of single event upset phenomena under the space navigation radiation environment. In the prior art, the single event upset resistance reinforcement of a DSP circuit mainly reduces the turnover rate of the whole circuit by adopting an error correction and detection algorithm, and the method has small influence on the performance of the DSP, but has limited effect on the turnover resistance rate.

Disclosure of Invention

The invention aims to provide a DSP (digital signal processor) reinforcement circuit for resisting single event upset, which solves the problem.

In order to solve the technical problem, the invention provides a DSP (digital signal processor) reinforcement circuit resisting single event upset, which comprises a DSP core, an on-chip synchronous memory, a clock system, an on-chip data interface, an on-chip address interface, an external memory interface, an external data bus and an external address bus;

the on-chip data interface is connected with a peripheral data bus, and the on-chip address interface is connected with a peripheral address bus; the DSP core reads and writes the synchronous memory in the chip through the data interface and the address interface in the chip, and accesses the running data and program;

the DSP core reads and writes instructions or data of an off-chip storage space through an external memory interface, and the data in the external memory interface is sent into the DSP core through an on-chip data interface; the address in the external memory interface is sent out by the DSP kernel through the on-chip address interface;

the DSP kernel configures a peripheral register through an in-chip data interface and an in-chip address interface, so that the DSP reinforced circuit has the functions of serial port communication, motion control, timing and interruption with the outside.

Optionally, the on-chip synchronous memory adopts a 12-pipe DICE unit structure to perform single event upset resistance reinforcement; the on-chip synchronous memory comprises a data input latch, an address row-column decoding circuit, clock logic, a word line driver, a write driver circuit, a DICE bit storage unit, a sensitive amplifier and a data output buffer;

the DICE bit storage unit is reinforced by a 12-pipe DICE structure with separated bit lines; the data input latch adopts a dual-mode redundancy and DICE latch structure, and the address input latch adopts a DICE latch structure.

Optionally, the clock logic adopts a filter circuit structure, and the sense amplifier and the data output buffer adopt a filtered DICE reinforced structure to filter transient pulse interference generated by a single particle in the clock and data read-out path.

Optionally, the clock system is reinforced by using a three-mode PLL; the clock system comprises three PLL circuits, three mode selectors and a filter circuit; the clock outputs of the same three PLL are connected to a three-mode selector, and the output of the three-mode selector is used as the clock of the whole DSP reinforcing circuit; the clock from the three-mode selector is sent to the internal clock network after passing through the filter circuit so as to filter transient pulse interference generated on the clock network by the single event effect.

Optionally, the lengths of the paths from the clock output of the three-way PLL to the input terminals of the three mode selectors are kept consistent, so as to prevent the clock delay difference caused by the path difference between the three-way clock and the three mode selectors.

Optionally, the DSP reinforcing circuit for resisting single event upset further includes an on-chip bus interface with EDAC; the on-chip bus interface with the EDAC comprises a first output data register, a first EDAC coding module, a first input data register, a first EDAC decoding and error correcting module, a selector MUX1/MUX2/MUX3, a peripheral data bus, an output address register, a second EDAC coding module and a peripheral address bus;

when the DSP core writes data to the peripheral, 3 independent data buses DRDB, DWDB and PRDB are multiplexed to the core data bus through a selector MUX1, 32-bit data are written into a first output data register and then enter a first EDAC coding module for coding, and coded output data comprising data bits and check bits are formed; the coded data is transmitted to the peripheral interface through a peripheral data bus;

when the DSP core receives the coded data on the peripheral data bus, the first EDAC decoding and error correcting module decodes the received data, regenerates the check bit, and generates a syndrome by performing XOR operation on the newly generated check bit and the original check bit; the first EDAC decoding and error correcting module generates error-corrected data and a data selection signal, if a new check bit is consistent with an original check bit, the received data is not overturned, and the MUX2 is controlled by the data selection signal to select coded data which does not need error correction, and the coded data is directly input into a first input data register and is placed on a kernel data bus; if the new check bit is not consistent with the original check bit, the received data is inverted, the error bit is inverted and then written again, the MUX2 is controlled by the data selection signal to select the data after error correction, the data is sent to the first input data register to be stored, and then the data is input to the kernel data bus.

Optionally, an address bus interface in the DSP core only sends an address to an external address bus, the 3 independent address buses PAB, DWAB, and DRAB are multiplexed onto the core address bus through the selector MUX3, the core address bus puts the address into the first output address register, the address in the first output address register is encoded by the second EDAC encoding module to form an encoded address, and the encoded address is transmitted to the external address interface through the external address bus.

Optionally, an external memory interface interacting with an off-chip data program is reinforced by using an EDAC error detection and correction technology; the external memory interface comprises a second input data register, a third EDAC coding module, a second output data register, a second EDAC decoding and error correcting module, a selector MUX4/MUX5, an off-chip data interface, a second output address register, a third EDAC decoding and error correcting module and an off-chip address interface;

when the DSP core reads data or instructions from the off-chip storage space through the external memory interface, the external memory interface stores the data or instructions on the off-chip data interface into a second input data register, the data or instructions in the second input data register are coded through a third EDAC coding module, and the coded data are sent to an external data bus;

when the DSP core sends data to an external memory interface through a peripheral data bus, the data in the second output data register is decoded through a second EDAC decoding and error correcting module to generate a new check bit, and the newly generated check bit and the original check bit are subjected to XOR operation to generate a checker; if the new check bit is consistent with the original check bit, the transmitted data is not turned over, and the data in the second output data register is directly transmitted to an off-chip data interface without error correction; if the new check bit is inconsistent with the original check bit, the sent data is overturned, the data is rewritten after the error-out bit is inverted, the MUX4 is controlled through the data selection signal to select the data after error correction, the data is sent to the second input data register to be stored, and then the data is output to the off-chip data interface, so that the error correction and detection and the sending and receiving of the EDAC of the off-chip data are realized;

when the DSP core sends an address to the external memory interface through the peripheral address bus, the external memory interface receives an EDAC encoded address on the peripheral address bus, the address is stored in the second output address register through the MUX5, the address in the second output address register regenerates a check bit through the third EDAC decoding and error correcting module, and the newly generated check bit and the original check bit are subjected to XOR operation to generate a syndrome; if the new check bit is consistent with the original check bit, the received address is not inverted, and the address in the second output address register is directly sent to the off-chip address bus without error correction; if the new check bit is inconsistent with the original check bit, the sent address is inverted, the error address bit is inverted and then written again, the MUX5 is controlled by the data selection signal to select the address after error correction, the address is stored in the second output address register and then output to the off-chip address bus; and error correction and detection and sending of the EDAC of the off-chip address are realized.

Optionally, the peripheral register includes a field bus ECAN, a multi-channel buffer McBSP, a serial peripheral interface SPI, a serial communication interface SCI, a pulse width modulation PWM, a capture unit CAP, an orthogonal code QEP, a timer, and a general GPIO.

The invention has the advantages that: the triple-modular redundancy technology is adopted on a clock system of the DSP circuit, the DICE structure is adopted on the on-chip synchronous memory for reinforcing the single event upset resistance, and an EDAC error correction and detection algorithm is adopted on an on-chip bus interface and an external memory interface of the DSP circuit, so that the whole circuit has better single event upset resistance.

Drawings

FIG. 1 is a structure diagram of a DSP reinforcing circuit for preventing single event upset provided by the invention;

FIG. 2 is a block diagram of an on-chip synchronous memory;

FIG. 3 is a block diagram of a clock system;

FIG. 4 is a block diagram of an on-chip bus interface with EDAC;

fig. 5 is a block diagram of an external memory interface with EDAC.

Detailed Description

The following provides a more detailed description of the DSP reinforcing circuit for preventing single event upset according to the present invention with reference to the accompanying drawings and the embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a single event upset resistant DSP (digital signal processor) reinforcement circuit, which is mainly used in the field of aerospace radiation resistance and has the functions of realizing the operation processing of digital signals and simultaneously carrying out serial port communication, data interaction and motion control with external equipment. The invention provides a single event upset resistant DSP (digital signal processor) reinforcement circuit, which has a structure shown in figure 1 and comprises a DSP core 1, an on-chip synchronous memory 2, a clock system 3, an on-chip data interface 4, an on-chip address interface 5, an external memory interface 6, an external data bus 7 and an external address bus 8. The on-chip data interface 4 is connected with a peripheral data bus 7, and the on-chip address interface 5 is connected with a peripheral address bus 8. The DSP core 1 performs arithmetic operations such as multiply-add, shift and accumulation and logic operations such as jump, comparison, addressing and judgment by executing instructions. The DSP core 1 reads and writes the on-chip synchronous memory 2 through the on-chip data interface 4 and the on-chip address interface 5, and accesses the running data and programs; the DSP core 1 reads and writes instructions or data of an off-chip storage space through an external memory interface 6, and the data in the external memory interface 6 is sent into the DSP core 1 through an on-chip data interface 4; the address in the external memory interface 6 is sent out by the DSP core 1 through the on-chip address interface 5; the DSP core 1 is provided with external registers such as a field bus ECAN, a multichannel buffer MCBSP, a serial peripheral interface SPI, a serial communication interface SCI, a pulse width modulation PWM, a capture unit CAP, an orthogonal code QEP, a timer, a general GPIO and the like through an on-chip data interface 4 and an on-chip address interface 5, so that the DSP reinforced circuit has the functions of serial port communication, motion control, timing and interruption with the outside.

The on-chip memory 2 adopts a 12-pipe DICE unit structure to perform single event upset resistance reinforcement; the DSP core 1 and the on-chip synchronous memory 2 carry out data program interactive access operation. As shown in FIG. 2, the circuit includes a data input latch, an address row-column decoding circuit, clock logic, a write driver circuit, a DICE bit storage unit, a sense amplifier and a data output buffer. In FIG. 2, the SRAM port signal A is address bus, D is 32-bit input data bus, CLK is clock, CEN is chip select enable signal, OEN is output enable signal, WEN is read/write enable signal, and Q is 32-bit output data bus. The DICE bit storage unit is reinforced by a 12-pipe DICE structure with separated bit lines; the data input latch logic adopts a dual-mode redundancy and DICE latch structure, and the address input latch logic adopts a DICE latch structure. The clock logic adopts a filter circuit structure, and the sensitive amplifier and the data output buffer adopt a DICE reinforced structure with filtering to filter transient pulse interference generated by single particles in a clock and data read-out path.

The clock system 3 is reinforced by adopting a three-mode PLL; as shown in fig. 3, the clock system includes a three-way PLL (i.e., PLL1, PLL2, and PLL 3), a three-mode selector, and a filter circuit; the clock outputs of the same three PLL are connected to a three-mode selector, and the output of the three-mode selector is used as the clock of the whole DSP reinforcing circuit; the clock from the three-mode selector is sent to the internal clock network after passing through the filter circuit so as to filter transient pulse interference generated on the clock network by the single event effect. The lengths of the paths of the clock output by the three PLL to the input end of the three mode selector are kept consistent, and the clock delay difference caused by the path difference between the three PLL and the three mode selector is prevented. When one of the two PLLs suffers single particle bombardment to cause frequency jitter, the other two PLLs work normally without affecting the clock stability of the whole circuit.

The DSP reinforcing circuit resisting the single event upset comprises an on-chip bus interface with an EDAC (electronic design automation), wherein the on-chip bus interface with the EDAC comprises an on-chip data interface and an on-chip address interface; as shown in fig. 4, the on-chip bus interface with EDAC includes a first output data register, a first EDAC encoding module, a first input data register, a first EDAC decoding and error correcting module, a selector MUX1/MUX2/MUX3, a peripheral data bus 7, an output address register, a second EDAC encoding module, and a peripheral address bus 8; when the DSP core writes data to the peripheral, 3 independent data buses DRDB, DWDB and PRDB are multiplexed to the core data bus through a selector MUX1, 32-bit data are written into a first output data register and then enter a first EDAC coding module for coding, and coded output data comprising data bits and check bits are formed; the coded data is transmitted to the peripheral interface through a peripheral data bus 7; when the DSP core receives the coded data, the first EDAC decoding and error correcting module decodes the 32-bit received data, regenerates the check bit, and generates a syndrome by performing XOR operation on the newly generated check bit and the original check bit; the first EDAC decoding and error correcting module generates error-corrected data and a data selection signal, if a new check bit is consistent with an original check bit, the received data is not overturned, and the MUX2 is controlled by the data selection signal to select coded data which does not need error correction, and the coded data is directly input into a first input data register and is placed on a kernel data bus; if the new check bit is not consistent with the original check bit, the received data is inverted, the error bit is inverted and then written again, the MUX2 is controlled by the data selection signal to select the data after error correction, the data is sent to the first input data register to be stored, and then the data is input to the kernel data bus.

An address bus interface in the DSP core only sends an address to an external address bus, 3 independent address buses PAB, DWAB and DRAB are multiplexed to the core address bus through a selector MUX3, the core address bus puts the address into a first output address register, the address in the first output address register is encoded through a second EDAC encoding module to form an encoded address, and the encoded address is transmitted to an external address interface through the external address bus.

The DSP reinforcing circuit resisting the single event upset also comprises an external memory interface with EDAC; as shown in fig. 5, the external memory interface includes a second input data register, a third EDAC encoding module, a second output data register, a second EDAC decoding and error correcting, a selector MUX4/MUX5, an off-chip data interface, a second output address register, a third EDAC decoding and error correcting module, and an off-chip address interface; when the DSP core reads data or instructions from the off-chip storage space through the external memory interface, the external memory interface stores the data or instructions on the off-chip data interface into a second input data register, the data or instructions in the second input data register are coded through a third EDAC coding module, and the coded data are sent to an external data bus;

when the DSP core sends data to an external memory interface through an on-chip data interface, the peripheral data bus sends the data after EDAC coding into a second output data register, the data in the second output data register is decoded through a second EDAC decoding and error correcting module to generate a new check bit, and the newly generated check bit and the original check bit are subjected to XOR operation to generate a checker; if the new check bit is consistent with the original check bit, the transmitted data is not turned over, and the data in the second output data register is directly transmitted to an off-chip data interface without error correction; if the new check bit is inconsistent with the original check bit, the sent data is overturned, the data is rewritten after the error-out bit is inverted, the MUX4 is controlled through the data selection signal to select the data after error correction, the data is sent to the second input data register to be stored, and then the data is output to the off-chip data interface, so that the error correction and detection and the sending and receiving of the EDAC of the off-chip data are realized;

when the DSP core sends an address to the external memory interface through the peripheral address bus, the external memory interface receives an EDAC encoded address on the peripheral address bus, the address is stored in the second output address register through the MUX5, the address in the second output address register regenerates a check bit through the third EDAC decoding and error correcting module, and the newly generated check bit and the original check bit are subjected to XOR operation to generate a syndrome; if the new check bit is consistent with the original check bit, the received address is not inverted, and the address in the second output address register is directly sent to the off-chip address bus without error correction; if the new check bit is inconsistent with the original check bit, the sent address is inverted, the error address bit is inverted and then written again, the MUX5 is controlled by the data selection signal to select the address after error correction, the address is stored in the second output address register and then output to the off-chip address bus; and error correction and detection and sending of the EDAC of the off-chip address are realized.

Through an EDAC mechanism with an on-chip bus interface of the EDAC and an external memory interface XINTF, the read-write of data or instructions outside the chip by the kernel is protected, and the soft errors of the data and the instructions caused by single event upset of a DSP circuit are reduced.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.