阅读说明：本技术 基于错误率的动态存储器刷新控制方法及装置 (Dynamic memory refresh control method and device based on error rate ) 是由 殷中云 唐越 邓玉良 方晓伟 苏通 朱晓锐 于 2020-12-22 设计创作，主要内容包括：本发明提供了一种基于错误率的动态存储器刷新控制方法,所述方法包括：根据错误率调整刷新周期；根据调整后的所述刷新周期发送刷新指令。根据动态存储器读取时的错误率而调整DRAM动态存储器的刷新周期,从而可以解决由各种因素导致的存储单元数据保持时间缩短的问题。(The invention provides a dynamic memory refresh control method based on an error rate, which comprises the following steps: adjusting a refresh period according to the error rate; and sending a refreshing instruction according to the adjusted refreshing period. The refresh cycle of the DRAM dynamic memory is adjusted according to the error rate when the dynamic memory is read, so that the problem of shortening the data retention time of the memory cell caused by various factors can be solved.)

1. A dynamic memory refresh control method based on error rate is characterized in that: the method comprises the following steps:

adjusting a refresh period according to the error rate;

and sending a refreshing instruction according to the adjusted refreshing period.

2. The error rate based dynamic memory refresh control method of claim 1, wherein: the adjusting the refresh cycle according to the error rate comprises:

coding input data to obtain a first check code;

encoding the read data to obtain a second check code;

and comparing the first check code with the second check code, if the first check code is different from the second check code, the read data has errors, and calculating the error rate of the read data.

3. The error rate based dynamic memory refresh control method of claim 2, wherein: after the encoding of the input data to obtain the first check code, the method includes:

and storing the first check code and the input data into a storage array.

4. The error rate based dynamic memory refresh control method of claim 3, wherein: the adjusting the refresh cycle according to the error rate further comprises: the error rate is derived based on an error detection algorithm.

5. The error rate based dynamic memory refresh control method of claim 4, wherein: the error detection algorithm includes a cyclic redundancy check, CRC.

6. The error rate based dynamic memory refresh control method of claim 5, wherein: the sending of the refresh command according to the adjusted refresh cycle includes: the rate at which refresh commands are sent is dependent on the error rate at the last time data was read.

7. The error rate based dynamic memory refresh control method of claim 6, wherein: said sending a refresh command at a rate that is dependent on said error rate of the last time data was read further comprises:

when the error rate is 0, the highest refreshing period is adopted for refreshing, so that the working efficiency of the memory can be improved, and the power consumption can be saved;

when the error rate increases, the refresh period is reduced to retain data, reducing errors.

8. An error rate based dynamic memory refresh control apparatus, comprising: the device comprises:

a refresh module: for adjusting the refresh period according to the error rate;

a control module: and sending a refresh command according to the adjusted refresh cycle.

9. An error rate based dynamic memory refresh control apparatus comprising a memory, a processor, and a computer program stored in said memory and executable on said processor, wherein said processor implements the steps of the error rate based dynamic memory refresh control method according to any one of claims 1 to 7 when executing said computer program.

10. A storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, performs the steps of the method for error rate based dynamic memory refresh control of any of claims 1 to 7.

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a method and an apparatus for controlling refresh of a dynamic memory based on an error rate.

Background

The structure of the DRAM dynamic memory is 1T1C, that is, one switching transistor plus one capacitor, and data 0 and 1 are stored according to the charging and discharging of the capacitor. Since the charge on the capacitor is lost over time, the memory cell needs to be refreshed periodically to recharge the capacitor to retain the data.

If the capacitance of the memory cell is affected by radiation, temperature, and the like, the data retention time of the memory is affected and reduced, and a data error occurs. At this time, if the refresh rate is increased, errors in the data due to the shortened retention time can be avoided.

Most of the current solutions are to adjust the refresh period according to the operating temperature of the chip. But the temperature is only a factor causing the capacitor to leak more quickly, and the factors such as service life, irradiation environment and the like also cause the capacitor to leak more quickly.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: a problem of shortening a data retention time of a memory cell caused by various factors.

In order to solve the technical problems, the invention adopts the technical scheme that:

in a first aspect, the present invention provides a method for controlling a refresh of a dynamic memory based on an error rate, the method comprising:

adjusting a refresh period according to the error rate;

and sending a refreshing instruction according to the adjusted refreshing period.

Further, the adjusting the refresh cycle according to the error rate comprises:

coding input data to obtain a first check code;

encoding the read data to obtain a second check code;

and comparing the first check code with the second check code, if the first check code is different from the second check code, the read data has errors, and calculating the error rate of the read data.

Further, after the encoding the input data to obtain the first check code, the method includes:

and storing the first check code and the input data into a storage array.

Further, the adjusting the refresh cycle according to the error rate further includes: the error rate is derived based on an error detection algorithm.

Further, the error detection algorithm includes a cyclic redundancy check, CRC.

Further, the sending a refresh command according to the adjusted refresh cycle includes: the rate at which refresh commands are sent is dependent on the error rate at the last time data was read.

Further, the sending the refresh command at a rate that is dependent on the error rate of the last time data was read further comprises:

when the error rate is 0, the highest refreshing period is adopted for refreshing, so that the working efficiency of the memory can be improved, and the power consumption can be saved;

when the error rate increases, the refresh period is reduced to retain data, reducing errors.

In a second aspect, the present invention also provides an apparatus for controlling a refresh of a dynamic memory based on an error rate, the apparatus comprising:

a refresh module: for adjusting the refresh period according to the error rate;

a control module: and sending a refresh command according to the adjusted refresh cycle.

In a third aspect, the present invention further provides an error rate-based dynamic memory refresh control apparatus, including a memory, a processor, and a computer program stored in the memory and capable of being executed on the processor, where the processor implements the steps of the error rate-based dynamic memory refresh control method according to the first aspect when executing the computer program.

In a fourth aspect, the present invention also provides a storage medium having a computer program stored thereon, where the computer program is executed by a processor to implement the steps of the method for controlling the refresh of a dynamic memory based on an error rate according to the first aspect.

The invention has the beneficial effects that: the invention provides a dynamic memory refresh control method based on an error rate, which comprises the following steps: adjusting a refresh period according to the error rate; and sending a refreshing instruction according to the adjusted refreshing period. The refresh cycle of the DRAM dynamic memory is adjusted according to the error rate when the dynamic memory is read, so that the problem of shortening the data retention time of the memory cell caused by various factors can be solved.

Drawings

The detailed structure of the invention is described in detail below with reference to the accompanying drawings

FIG. 1 is a flow chart illustrating a method for controlling refresh of a dynamic memory based on an error rate according to the present invention;

FIG. 2 is a sub-flowchart of the error rate based dynamic memory refresh control method according to the present invention;

FIG. 3 is a schematic view of another sub-flow chart of the error rate-based dynamic memory refresh control method according to the present invention;

FIG. 4 is a flowchart illustrating a method for controlling refresh of a dynamic memory based on an error rate according to an embodiment of the present invention.

Detailed Description

In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for controlling refresh of a dynamic memory based on an error rate according to the present invention;

the invention provides a dynamic memory refresh control method based on an error rate, which comprises the following steps:

step 101, adjusting a refresh period according to an error rate;

and 102, sending a refresh command according to the adjusted refresh cycle.

Assuming that tRFC is used to define the refresh cycle, the prior art is typically 64ms, tREFI is the interval between two refresh signals, and if the memory has 8k rows, tREFI is typically 7.8 μ s, and when the tREFI counter reaches the count value, a refresh command is sent to the DRAM memory. Compared with the prior art, the method and the device have the advantages that the refreshing period of the DRAM dynamic memory is adjusted according to the error rate when the dynamic memory is read, so that the problem that the data retention time of the memory unit is shortened due to various factors can be solved.

Further, referring to fig. 2 to 4, fig. 2 is a sub-flow chart of the error rate based dynamic memory refresh control method according to the present invention; FIG. 3 is a schematic view of another sub-flow chart of the error rate-based dynamic memory refresh control method according to the present invention; FIG. 4 is a flowchart illustrating a method for controlling refresh of a dynamic memory based on an error rate according to an embodiment of the present invention.

The adjusting the refresh cycle according to the error rate comprises:

step 201, encoding input data to obtain a first check code;

step 202, encoding the read data to obtain a second check code;

step 203, comparing the first check code with the second check code, if the first check code is different from the second check code, the read data has an error, and calculating an error rate of the read data.

In the implementation, firstly, the input data is encoded through the data check module to obtain a first check code, when the data is read out, the read data is encoded through the data check module to obtain a second check code, the first check code and the second check code are used for comparison, the number of error data can be obtained, and then the error rate of the read data is calculated.

It should be noted that the data verification module can be placed in both the DRAM controller and the DRAM memory chip. If placed in a DRAM controller, this function can be achieved using different DRAM memories of different manufacturers.

Further, after the encoding the input data to obtain the first check code, the method includes:

and storing the first check code and the input data into a storage array.

Further, the adjusting the refresh cycle according to the error rate further includes: the error rate is derived based on an error detection algorithm.

Further, the error detection algorithm includes a cyclic redundancy check, CRC.

In the embodiment of the present invention, other Error detection algorithms can be used, and the Error detection algorithm uses the principle of division and remainder to detect errors (Error detection).

It should be noted that, the DDR4 chip is provided with a CRC data check module, so that the function of adjusting the refresh period according to the error rate can be more conveniently implemented.

Further, the sending a refresh command according to the adjusted refresh cycle includes: the rate at which refresh commands are sent is dependent on the error rate at the last time data was read.

In this embodiment, after the data check module obtains the error rate of the data, the refresh controller generates a refresh command by using the error rate of the read data obtained by the data check module and the timer, and adjusts the refresh period according to different error rates.

Further, the sending the refresh command at a rate that is dependent on the error rate of the last time data was read further comprises:

when the error rate is 0, the highest refreshing period is adopted for refreshing, so that the working efficiency of the memory can be improved, and the power consumption can be saved;

when the error rate increases, the refresh period is reduced to retain data, reducing errors.

In this embodiment, several refresh cycles may be preset, for example, 5 refresh cycles, which are 128ms, 64ms, 32ms, 16ms, and 8ms, respectively. When the error rate is 0, the highest refreshing period is adopted for refreshing, so that the working efficiency of the memory can be improved, and the power consumption can be saved; when the error rate increases, the refresh period is reduced to retain data, reducing errors.

Further, the present invention also provides an error rate-based dynamic memory refresh control apparatus, comprising:

a refresh module: for adjusting the refresh period according to the error rate;

a control module: and sending a refresh command according to the adjusted refresh cycle.

The error rate-based dynamic memory refresh control device provided by the embodiment of the invention can realize that: adjusting a refresh period according to the error rate; and sending a refresh command according to the adjusted refresh cycle, and adjusting the refresh cycle of the DRAM dynamic memory according to the error rate when the dynamic memory is read, so that the problem of shortening the data retention time of the memory unit caused by various factors can be solved.

Further, the present invention also provides an error rate based dynamic memory refresh control apparatus, which includes a memory, a processor, and a computer program stored in the memory and capable of being stored in the processor for operation, wherein the processor implements the steps of the error rate based dynamic memory refresh control method as described above when executing the computer program.

Further, the present invention also provides a storage medium having stored thereon a computer program which, when being executed by a processor, implements the respective steps of the error rate based dynamic memory refresh control method as described above.

In summary, the error rate-based method and apparatus for controlling refresh of dynamic memory provided by the present invention adjust the refresh cycle of the DRAM dynamic memory according to the error rate when the dynamic memory is read, so as to solve the problem of shortening the data retention time of the memory cell caused by various factors.

Each functional module in the embodiments of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In view of the above description of the error rate-based dynamic memory refresh control method and apparatus provided by the present invention, those skilled in the art will appreciate that there are variations in the embodiments and applications of the method and apparatus according to the concepts of the present application.