阅读说明：本技术 一种基于半导体测试机的数据处理系统及方法 (Data processing system and method based on semiconductor testing machine ) 是由 黄健 于 2020-11-13 设计创作，主要内容包括：本发明公开一种基于半导体测试机的数据处理系统及方法,属于数据处理领域。将各个芯片厂家仿码位流文件转化为测试机的专用测试码,并且在测试完成后,进行对批次芯片测试数据分析,解决了线下烧写的限制,并对批次电路数据进行分析,更好的将其进行分类；解决了主流厂家位流仿码适用于测试机台的问题,减少测试分析程中的人工操作,提高了生产效率。(The invention discloses a data processing system and method based on a semiconductor testing machine, and belongs to the field of data processing. The code-copying bit stream file of each chip manufacturer is converted into a special test code of a testing machine, and after the test is finished, the test data of the batch chips are analyzed, so that the limitation of off-line programming is solved, the batch circuit data are analyzed, and the batch circuit data are better classified; the problem that the bit stream imitation codes of mainstream manufacturers are suitable for a test machine is solved, manual operation in a test analysis process is reduced, and production efficiency is improved.)

1. A data processing system based on a semiconductor tester, comprising:

the transcoding module is used for converting the bit stream file into a test code file formed by the special binary code;

the test machine platform calls the test code file through a test machine platform program to perform online configuration programming on the chip and generate a corresponding function code for testing;

and the data analysis module analyzes the data of the circuit test of the batch so as to judge the circuit problem.

2. The semiconductor tester-based data processing system of claim 1, wherein the semiconductor tester-based data processing system further comprises a test board for hardware connection of the chip to the tester bench to obtain hardware guarantees.

3. The semiconductor tester-based data processing system of claim 1, wherein each row in the test code file is a one-cycle level transition, and the test code consisting of binary numbers 0, 1 complies with IEEE1149.1 design rules.

4. The semiconductor tester-based data processing system of claim 1, wherein the bitstream file is automatically generated by comprehensive simulation of official development software of each FPGA/CPLD manufacturer.

5. A data processing method based on a semiconductor testing machine is characterized by comprising the following steps:

the welding test board is connected with the test board and the test machine platform;

transcoding the ATP, RBT or PCF file to generate a test configuration code;

the test machine station configures the chip function on line by the test configuration code through the JTAG interface or the slave parallel port;

the test machine verifies the signals of the corresponding functions input by the test chip;

and writing or automatically generating a binary function test code by integrating the simulation information generated by the software, and comparing whether the function test code is consistent with the actual output or not so as to perform function verification and performance test on the chip.

6. The semiconductor tester-based data processing method of claim 1, wherein after the functional verification and the performance test of the chip, the semiconductor tester-based data processing method further comprises:

and importing the data into data processing software, performing positive-space distribution analysis on the data, and classifying the batch circuits by using a clustering algorithm so as to analyze the packaging process.

Technical Field

The invention relates to the technical field of data processing, in particular to a data processing system and method based on a semiconductor testing machine.

Background

Semiconductor testers provide the power and precision required by engineers, as well as testing speed and coverage, to provide a wide range of testing requirements for the digital/mixed signal market. Including digital devices, including the most complex and high-value semiconductors, to mixed-signal SoC devices, ten million gate-level FPGA/CPLD devices, in the core of mobile devices and gaming machines.

In conventional semiconductor test data processing, after a semiconductor chip is tested, data corresponding to test items are manually sorted, corresponding table information is generated mainly by using Excel and other software, and then table data analysis is performed, so that whether a batch of chips is good or bad is judged, and a required test item related variation and a positive-phase distribution diagram are generated. However, the conventional test data analysis cannot get rid of the tedious manual operation, a large amount of production time is spent in the data analysis process, and more than one test machine is used, so that the test data analysis is complex, the test cost is high, and the production efficiency is low. Meanwhile, for the FPGA/CPLD chip, code imitation software of each chip manufacturer is different, the generated binary bit stream cannot be suitable for a test machine, an engineer needs to manually translate the binary bit stream into a test code special for the test machine, and the development period is greatly prolonged.

Disclosure of Invention

The invention aims to provide a data processing system and a data processing method based on a semiconductor tester, which aim to solve the problems of long time, high cost and low efficiency of conventional test data analysis.

In order to solve the above technical problem, the present invention provides a data processing system based on a semiconductor tester, comprising:

the transcoding module is used for converting the bit stream file into a test code file formed by the special binary code;

the test machine platform calls the test code file through a test machine platform program to perform online configuration programming on the chip and generate a corresponding function code for testing;

and the data analysis module analyzes the data of the circuit test of the batch so as to judge the circuit problem.

Optionally, the data processing system based on the semiconductor tester further includes a test board for connecting the chip to the test machine through hardware, so as to obtain hardware guarantee.

Optionally, in the test code file, each row is a period of level conversion, and the test code composed of binary numbers 0 and 1 conforms to the IEEE1149.1 design rule.

Optionally, the bit stream file is automatically generated by the comprehensive simulation of official development software of each FPGA/CPLD manufacturer.

The invention also provides a data processing method based on the semiconductor tester, which comprises the following steps:

the welding test board is connected with the test board and the test machine platform;

transcoding the ATP, RBT or PCF file to generate a test configuration code;

the test machine station configures the chip function on line by the test configuration code through the JTAG interface or the slave parallel port;

the test machine verifies the signals of the corresponding functions input by the test chip;

and writing or automatically generating a binary function test code by integrating the simulation information generated by the software, and comparing whether the function test code is consistent with the actual output or not so as to perform function verification and performance test on the chip.

Optionally, after performing the function verification and the performance test on the chip, the data processing method based on the semiconductor tester further includes:

and importing the data into data processing software, performing positive-space distribution analysis on the data, and classifying the batch circuits by using a clustering algorithm so as to analyze the packaging process.

In the data processing system and method based on the semiconductor tester, the code-imitating bit stream file of each chip manufacturer is converted into the special test code of the tester, and after the test is finished, the test data of the chips in batches is analyzed, so that the limitation of off-line programming is solved, the circuit data in batches is analyzed, and the circuits are better classified; the problem that the bit stream imitation codes of mainstream manufacturers are suitable for a test machine is solved, manual operation in a test analysis process is reduced, and production efficiency is improved.

Drawings

FIG. 1 is a schematic block diagram of a data processing system architecture based on a semiconductor tester;

FIG. 2 is a schematic flow chart of the transcoding module converting the bit stream of the FPGA/CPLD chip into the test code;

FIG. 3 is a schematic workflow diagram of a data analysis module;

fig. 4 is a flow chart of a data processing method based on a semiconductor tester.

Detailed Description

The data processing system and method based on semiconductor tester according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a data processing system based on a semiconductor tester, which is used for performing function/performance test on an FPGA/CPLD chip and comprises a transcoding module, a data analysis module, a test machine, a test board, a test machine program and a test code file, wherein the transcoding module is used for performing function/performance test on the FPGA/CPLD chip, as shown in figure 1, the data processing system comprises a transcoding module, a data analysis module, a test machine, a test board:

the test code file is a special binary code converted from a bit stream code provided by an FPGA/CPLD manufacturer into a test machine, and each line in the test code file is a periodic level conversion test code consisting of binary numbers 0 and 1. The bit stream code is automatically generated by the comprehensive simulation of official development software of each FPGA/CPLD manufacturer.

As shown in fig. 2, the transcoding module converts the bit stream of the FPGA/CPLD chip into the test code, which can conform to the design rule of IEEE1149.1, convert the bit stream RBT file or the bit stream PCF file into the AVC file, and deal with the compatibility problem of the tester, and mainly convert the test code ATP file (vector format) into the AVC file for the ULTRA FLEX platform to V93000 platform. As shown in fig. 3, the data analysis module is mainly responsible for analyzing the test data of the batch circuit, so as to determine the problem of the batch circuit.

The testing machine calls the AVC file through the testing machine program to perform online configuration programming on the FPGA/CPLD chip, and generates a corresponding function code through the configuration file to perform testing.

The test board and the tester are hardware components of the method, and the test board is used for connecting the chip and the tester table through hardware, so that hardware guarantee is obtained.

Example two

The invention also provides a data processing method based on the semiconductor tester, which can realize the function verification, the performance test and the data analysis of the FPGA/CPLD chip, and the flow is shown as figure 4, and comprises the following steps:

the welding test board is connected with the test board and the test machine platform;

transcoding the ATP, RBT or PCF file to generate a test configuration code;

the test machine station configures the chip function on line by the test configuration code through the JTAG interface or the slave parallel port;

the test machine verifies the signals of the corresponding functions input by the test chip;

writing or automatically generating a binary function test code through simulation information generated by the integrated software, comparing whether the function test code is consistent with actual output or not, and further performing function verification and performance test on the chip; if only one of the function verification and the performance test is inconsistent, the chip is indicated to be invalid;

otherwise, the chip test is passed, the data is led into the data analysis module, the positive distribution analysis is carried out on the data, and the clustering algorithm is used for classifying the batch circuits so as to analyze the packaging process.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.