阅读说明：本技术 一种电路装置及电子设备 (Circuit device and electronic equipment ) 是由 李志� 贾学强 满宏涛 于 2020-12-28 设计创作，主要内容包括：本发明提供了一种电路装置及电子设备,属于网络设备的技术领域,解决了现有技术在SD控制器配置新的相关寄存器时存在控制器命令响应接收错误或数据传输错误的技术问题。一种电路装置,包括状态判断电路、写入电路和硬件逻辑电路；状态判断电路包括数据状态判断电路和命令状态判断电路；写入电路包括数据写入电路和命令写入电路；数据状态判断电路的第一输入端与硬件逻辑电路的数据线使能端相连,数据状态判断电路的第二输入端与总线使能端相连；命令状态判断电路的第一输入端与硬件逻辑电路的命令线使能端相连,命令状态判断电路的第二输入端与总线使能端相连；数据状态判断电路的输出端与数据写入电路的使能端相连。(The invention provides a circuit device and electronic equipment, belongs to the technical field of network equipment, and solves the technical problem that in the prior art, when an SD controller is configured with a new related register, a controller command response receiving error or a data transmission error exists. A circuit device comprises a state judgment circuit, a write-in circuit and a hardware logic circuit; the state judgment circuit comprises a data state judgment circuit and a command state judgment circuit; the write circuit comprises a data write circuit and a command write circuit; the first input end of the data state judging circuit is connected with the data line enabling end of the hardware logic circuit, and the second input end of the data state judging circuit is connected with the bus enabling end; the first input end of the command state judging circuit is connected with the command line enabling end of the hardware logic circuit, and the second input end of the command state judging circuit is connected with the bus enabling end; the output end of the data state judging circuit is connected with the enabling end of the data writing circuit.)

1. A circuit device is characterized by comprising a state judgment circuit, a write-in circuit and a hardware logic circuit;

the state judgment circuit comprises a data state judgment circuit and a command state judgment circuit;

the write circuit comprises a data write circuit and a command write circuit;

the first input end of the data state judging circuit is connected with the data line enabling end of the hardware logic circuit, and the second input end of the data state judging circuit is connected with the bus enabling end;

the first input end of the command state judging circuit is connected with the command line enabling end of the hardware logic circuit, and the second input end of the command state judging circuit is connected with the bus enabling end;

the output end of the data state judging circuit is connected with the enabling end of the data writing circuit;

and the output end of the command state judgment circuit is connected with the enabling end of the command writing circuit.

2. The circuit arrangement of claim 1, wherein the data state decision circuit comprises a primary and gate, a secondary and gate, and a data address matching circuit;

the first input end of the first-level AND gate is connected with the data line enabling end, and the second input end of the first-level AND gate is connected with the bus enabling end;

the output end of the first-stage AND gate is connected with the first input end of the second-stage AND gate, and the output end of the data address matching circuit is connected with the second input end of the second-stage AND gate;

and the output end of the secondary AND gate is connected with the enabling end of the data writing circuit.

3. The circuit arrangement of claim 2, wherein the data address matching circuit has a first input for inputting a data set register address signal and a second input for inputting a bus address signal.

4. The circuit arrangement of claim 2, wherein the data address matching circuit comprises an ADMA system register address matching circuit, a data block length register address matching circuit, a data block number register address matching circuit, and a transfer mode register address matching circuit;

the output ends of the ADMA system register address matching circuit, the data block length register address matching circuit, the data block number register address matching circuit and the transmission mode register address matching circuit are respectively connected with the second input end of a two-stage AND gate.

5. The circuit arrangement of claim 1, wherein the command state decision circuit comprises a primary and gate, a secondary and gate, and a command address matching circuit;

the first input end of the first-level AND gate is connected with the command line enabling end, and the second input end of the first-level AND gate is connected with the bus enabling end;

the output end of the first-stage AND gate is connected with the first input end of the second-stage AND gate, and the output end of the command address matching circuit is connected with the second input end of the second-stage AND gate;

and the output end of the secondary AND gate is connected with the enabling end of the command writing circuit.

6. The circuit arrangement of claim 5, wherein the command address matching circuit has a first input for a command group register address signal and a second input for a bus address signal.

7. The circuit arrangement of claim 5, wherein the command address matching circuit comprises a command content register address matching circuit and a command number register address matching circuit;

the command content register address matching circuit and the command number register address matching circuit are respectively connected with the second input end of the second-stage AND gate.

8. The circuit arrangement of claim 1, wherein the data write circuit and the command write circuit further comprise a data receiving terminal;

the data receiving ends of the data writing circuit and the command writing circuit are connected with the data end of the bus;

the output end of the data writing circuit is connected with the input end of the data group register;

the output end of the command writing circuit is connected with the input end of the command group register.

9. The circuit arrangement of claim 8, wherein the data group registers include an ADMA system address register, a data block length register, a data block number register, and a transfer mode register;

the command group register includes a command content register and a command number register.

10. An electronic device, characterized in that it comprises a circuit arrangement according to any one of claims 1 to 9.

Technical Field

The present invention relates to the field of network device technologies, and in particular, to a circuit device and an electronic device.

Background

The sd (secure digital) card is a new generation of memory devices based on semiconductor flash memory. The mobile phone has the characteristics of small volume, high memory capacity, high data transmission rate, low cost, flexible movement and high safety, and is widely applied to products such as a PC (personal computer), a digital camera, a digital video camera, a mobile phone and the like at present.

The SD protocol is divided into a host controller protocol and a physical layer protocol, where the host controller protocol defines a standard register set and various transaction flows, and the physical layer protocol defines various commands, responses, frame formats, timing sequences, electrical characteristics, and the like. A typical SD controller is responsible for configuring registers and controlling transaction flow, and hardware is responsible for receiving and transmitting commands, responses and data according to physical layer format.

For the command transaction flow, according to the protocol specification, before configuring a new command related register, the driver needs to read the controller status register and judge whether the controller related line is occupied, because the driver reads the controller related register through the system bus, if the data transmission error or the driver execution program judgment error occurs on the bus, the driver may update the command related register when the related line is occupied, which may cause the controller command response receiving error or the data transmission error.

Therefore, the prior art has a problem that a controller command response reception error or a data transmission error occurs when the SD controller configures a new relevant register.

Disclosure of Invention

The invention provides a circuit device and an electronic device, which solve the technical problem of the prior art that a command response receiving error or a data transmission error of a controller exists when an SD controller configures a new relevant register.

In a first aspect, the present invention provides a circuit apparatus, including a state determining circuit, a writing circuit, and a hardware logic circuit;

the state judgment circuit comprises a data state judgment circuit and a command state judgment circuit;

the write circuit comprises a data write circuit and a command write circuit;

the first input end of the data state judging circuit is connected with the data line enabling end of the hardware logic circuit, and the second input end of the data state judging circuit is connected with the bus enabling end;

the first input end of the command state judging circuit is connected with the command line enabling end of the hardware logic circuit, and the second input end of the command state judging circuit is connected with the bus enabling end;

the output end of the data state judging circuit is connected with the enabling end of the data writing circuit;

and the output end of the command state judgment circuit is connected with the enabling end of the command writing circuit.

Furthermore, the data state judging circuit comprises a primary AND gate, a secondary AND gate and a data address matching circuit;

the first input end of the first-level AND gate is connected with the data line enabling end, and the second input end of the first-level AND gate is connected with the bus enabling end;

the output end of the first-stage AND gate is connected with the first input end of the second-stage AND gate, and the output end of the data address matching circuit is connected with the second input end of the second-stage AND gate;

and the output end of the secondary AND gate is connected with the enabling end of the data writing circuit.

Furthermore, a first input end of the data address matching circuit inputs a data group register address signal, and a second input end of the data address matching circuit inputs a bus address signal.

Further, the data address matching circuit comprises an ADMA system register address matching circuit, a data block length register address matching circuit, a data block number register address matching circuit and a transmission mode register address matching circuit;

the output ends of the ADMA system register address matching circuit, the data block length register address matching circuit, the data block number register address matching circuit and the transmission mode register address matching circuit are respectively connected with the second input end of a two-stage AND gate.

Furthermore, the command state judging circuit comprises a first-level AND gate, a second-level AND gate and a command address matching circuit;

the first input end of the first-level AND gate is connected with the command line enabling end, and the second input end of the first-level AND gate is connected with the bus enabling end;

the output end of the first-stage AND gate is connected with the first input end of the second-stage AND gate, and the output end of the command address matching circuit is connected with the second input end of the second-stage AND gate;

and the output end of the secondary AND gate is connected with the enabling end of the command writing circuit.

Furthermore, a first input end of the command address matching circuit inputs a command group register address signal, and a second input end of the command address matching circuit inputs a bus address signal.

Further, the command address matching circuit comprises a command content register address matching circuit and a command number register address matching circuit;

the command content register address matching circuit and the command number register address matching circuit are respectively connected with the second input end of the second-stage AND gate.

Furthermore, the data writing circuit and the command writing circuit also comprise a data receiving end;

the data receiving ends of the data writing circuit and the command writing circuit are connected with the data end of the bus;

the output end of the data writing circuit is connected with the input end of the data group register;

the output end of the command writing circuit is connected with the input end of the command group register.

Further, the data group register comprises an ADMA system address register, a data block length register, a data block number register and a transmission mode register;

the command group register includes a command content register and a command number register.

In a second aspect, the present invention further provides an electronic device, including the circuit apparatus in the first aspect.

The circuit device provided by the invention comprises a state judgment circuit, a write-in circuit and a hardware logic circuit, wherein the state judgment circuit comprises a data state judgment circuit and an instruction state judgment circuit, and the write-in circuit comprises a data write-in circuit and an instruction write-in circuit.

The first input end of the data state judging circuit is connected with the data line enabling end of the hardware logic circuit, the second input end of the data state judging circuit is connected with the bus enabling end, and the output end of the data state judging circuit is connected with the enabling end of the data writing circuit.

When the data line is idle, the data line enable end of the hardware logic circuit outputs a high level enable signal, when the bus enable signal is at a high level, the output end of the data state judging circuit is the high level enable signal, the data state judging circuit outputs the high level enable signal to the data writing circuit, and the data writing circuit starts to write data; when the bus enable signal is at a low level, the output end of the data state judging circuit is the low level enable signal, the data state judging circuit outputs the low level enable signal to the data writing circuit, and the data writing circuit cannot write data.

When the data line is occupied, the data line enable end of the hardware logic circuit outputs a low level enable signal, no matter the bus enable signal is at a high level or a low level, the output end of the data state judging circuit is at a low level enable signal, the data state judging circuit outputs the low level enable signal to the data writing circuit, and the data writing circuit cannot write data. The first input end of the command state judging circuit is connected with the enabling end of the command line of the hardware logic circuit, the second input end of the command state judging circuit is connected with the enabling end of the bus, and the output end of the command state judging circuit is connected with the enabling end of the command writing circuit.

When the command line is idle, the enabling end of the command line of the hardware logic circuit outputs a high-level enabling signal, when the bus enabling signal is high level, the output end of the command state judging circuit is the high-level enabling signal, the command state judging circuit outputs the high-level enabling signal to the command writing circuit, and the command writing circuit starts to write commands; when the bus enable signal is at low level, the output end of the command state judgment circuit is the low level enable signal, the command state judgment circuit outputs the low level enable signal to the command write-in circuit, and the command write-in circuit can not write in the command. When the command line is occupied, the command line enable end of the hardware logic circuit outputs a low level enable signal, no matter the bus enable signal is at a high level or at a low level, the output end of the command state judging circuit is at a low level enable signal, the command state judging circuit outputs a low level enable signal to the command writing circuit, and the command writing circuit cannot write commands.

By adopting the circuit device provided by the invention, the setting state judging circuit, the writing circuit and the hardware logic circuit are utilized, whether the data line and the command line are occupied is judged, and the enabling signal is output to the writing circuit to control the writing circuit to write data and command, so that the drive can not update the related register when the command line or the data line is occupied, the problem of command response receiving error or data transmission error of the SD controller is further avoided, and the purpose of smoothly configuring the related register is achieved.

Accordingly, the electronic equipment provided by the invention also has the technical effects.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a circuit arrangement according to an embodiment of the present invention;

FIG. 2 is a flow chart of command and data transmission of the SD controller according to the embodiment of the invention;

fig. 3 is a circuit diagram of a circuit device according to an embodiment of the invention.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terms "comprising" and "having," and any variations thereof, as referred to in embodiments of the present invention, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

For the command transaction flow, according to the protocol specification, before configuring a new command related register, the driver needs to read the controller status register and judge whether the controller related line is occupied, because the driver reads the controller related register through the system bus, if the data transmission error or the driver execution program judgment error occurs on the bus, the driver may update the command related register when the related line is occupied, which may cause the controller command response receiving error or the data transmission error.

Therefore, the prior art has a problem that a controller command response reception error or a data transmission error occurs when the SD controller configures a new relevant register.

To solve the above problems, embodiments of the present invention provide a circuit device and an electronic apparatus.

Example 1:

as shown in fig. 1, a circuit device according to an embodiment of the present invention includes a state determining circuit, a writing circuit and a hardware logic circuit, where the state determining circuit includes a data state determining circuit and a command state determining circuit, and the writing circuit includes a data writing circuit and a command writing circuit.

The first input end of the data state judging circuit is connected with the data line enabling end of the hardware logic circuit, the second input end of the data state judging circuit is connected with the bus enabling end, and the output end of the data state judging circuit is connected with the enabling end of the data writing circuit.

When the data line is idle, the data line enable end of the hardware logic circuit outputs a high level enable signal, when the bus enable signal is at a high level, the output end of the data state judging circuit is the high level enable signal, the data state judging circuit outputs the high level enable signal to the data writing circuit, and the data writing circuit starts to write data; when the bus enable signal is at a low level, the output end of the data state judging circuit is the low level enable signal, the data state judging circuit outputs the low level enable signal to the data writing circuit, and the data writing circuit cannot write data.

When the data line is occupied, the data line enable end of the hardware logic circuit outputs a low level enable signal, no matter the bus enable signal is at a high level or a low level, the output end of the data state judging circuit is at a low level enable signal, the data state judging circuit outputs the low level enable signal to the data writing circuit, and the data writing circuit cannot write data. The first input end of the command state judging circuit is connected with the enabling end of the command line of the hardware logic circuit, the second input end of the command state judging circuit is connected with the enabling end of the bus, and the output end of the command state judging circuit is connected with the enabling end of the command writing circuit.

When the command line is idle, the enabling end of the command line of the hardware logic circuit outputs a high-level enabling signal, when the bus enabling signal is high level, the output end of the command state judging circuit is the high-level enabling signal, the command state judging circuit outputs the high-level enabling signal to the command writing circuit, and the command writing circuit starts to write commands; when the bus enable signal is at low level, the output end of the command state judgment circuit is the low level enable signal, the command state judgment circuit outputs the low level enable signal to the command write-in circuit, and the command write-in circuit can not write in the command. When the command line is occupied, the command line enable end of the hardware logic circuit outputs a low level enable signal, no matter the bus enable signal is at a high level or at a low level, the output end of the command state judging circuit is at a low level enable signal, the command state judging circuit outputs a low level enable signal to the command writing circuit, and the command writing circuit cannot write commands.

By adopting the circuit device provided by the embodiment of the invention, the setting state judgment circuit, the write-in circuit and the hardware logic circuit are utilized, whether the data line and the command line are occupied is judged, and the enable signal is output to the write-in circuit to control the write-in circuit to write in the data and the command, so that the drive cannot update the related register when the command line or the data line is occupied, further the problem of command response receiving error or data transmission error of the SD controller is avoided, and the purpose of smoothly configuring the related register is achieved.

According to the SD controller protocol, the transmission of commands and data is completed by the cooperation of a driver and hardware logic, the work of the driver completion in the command transaction flow is shown in figure 2, for the commands without data transmission, the state register of the read controller is driven, and the command content register and the command number register are configured after the command line is idle; for a command with data transmission, the driver also needs to wait for the data line to be free and configure a data block length register, a data block number register, a transmission mode register, and the like.

In one possible embodiment, as shown in fig. 3, the data state determining circuit includes a first and gate, a second and gate, and a data address matching circuit, wherein a first input terminal of the first and gate is connected to the data line enable terminal, a second input terminal of the first and gate is connected to the bus enable terminal, an output terminal of the first and gate is connected to a first input terminal of the second and gate, an output terminal of the data address matching circuit is connected to a second input terminal of the second and gate, and an output terminal of the second and gate is connected to the enable terminal of the data writing circuit. The data state judging circuit is provided with a first-level AND gate and a second-level gate, so that when the data line enabling end and the bus enabling end both output high-level enabling signals and the data address matching circuit is successfully matched with the address and then is also a high-level signal, the output end of the second AND gate can output the high-level enabling signals, the data writing circuit is controlled to write data, and otherwise, the data writing circuit cannot write data.

In one possible embodiment, the data address matching circuit has a first input for the data set register address signal and a second input for the bus address signal. The register address signals of the data group machine comprise ADMA (address Memory Access, linked list type direct Memory Access) address signals, data block length register address signals, data block number register address signals and transmission mode register address signals, and after address matching is successful, the data address matching circuit sends high-level enabling signals to the second input end of the second-stage AND gate.

In one possible implementation, the data address matching circuitry includes ADMA system register address matching circuitry, data block length register address matching circuitry, data block number register address matching circuitry, and transfer mode register address matching circuitry. The output ends of the ADMA system register address matching circuit, the data block length register address matching circuit, the data block number register address matching circuit and the transmission mode register address matching circuit are respectively connected with the second input end of a two-stage AND gate. The first input end of the second-level AND gate is connected with the output end of the first-level AND gate, and the second input end of the second-level AND gate is respectively connected with a plurality of data address matching circuits.

In one possible implementation, the command state judging circuit includes a first and gate, a second and gate, and a command address matching circuit, a first input terminal of the first and gate is connected to a command line enable terminal, a second input terminal of the first and gate is connected to a bus enable terminal, an output terminal of the first and gate is connected to a first input terminal of the second and gate, an output terminal of the command address matching circuit is connected to a second input terminal of the second and gate, and an output terminal of the second and gate is connected to an enable terminal of the command writing circuit. The command state judging circuit is provided with a first-level AND gate and a second-level AND gate, so that when the command line enabling end and the bus enabling end both output high-level enabling signals and the command address matching circuit is successfully matched with the address and then is a high-level signal, the output end of the second AND gate can output the high-level enabling signals, the command writing circuit is controlled to write commands, and otherwise, the command writing circuit cannot write commands.

In one possible implementation, the first input terminal of the command address matching circuit inputs a command group register address signal, the second input terminal inputs a bus address signal, the command group register address signal includes a command content register address signal and a command number register address signal, and after the address matching is successful, the command address matching circuit sends a high-level enable signal to the second input terminal of the second-stage and gate.

In a possible implementation manner, the command address matching circuit includes a command content register address matching circuit and a command number register address matching circuit, and the command content register address matching circuit and the command number register address matching circuit are respectively connected to the second input end of one of the two-stage and gates. The first input end of the second-level AND gate is connected with the output end of the first-level AND gate, and the second input end of the second-level AND gate is respectively connected with a plurality of command address matching circuits.

In a possible implementation manner, the data write circuit and the command write circuit further include a data receiving end, the data receiving ends of the data write circuit and the command write circuit are connected to the data end of the bus, the output end of the data write circuit is connected to the input end of the data group register, the output end of the command write circuit is connected to the input end of the command group register, and the data receiving end is responsible for receiving the bus data to be written by the data group register and the command group register.

In one possible implementation, the data group register includes an ADMA system address register, a data block length register, a data block number register, and a transfer mode register, the command group register includes a command content register and a command number register, and the data write circuit and the command write circuit write the bus data into the corresponding registers when receiving the high-level enable signal.

Example 2:

an embodiment of the present invention provides an electronic device including the circuit apparatus as provided in embodiment 1. The electronic equipment adopting the circuit device has the advantage of high operation stability.

The electronic device provided by the embodiment of the invention has the same technical characteristics as the circuit device provided by the embodiment of the invention, so that the same technical problems can be solved, and the same technical effects can be achieved.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings or the orientations or positional relationships that the products of the present invention are conventionally placed in use, and are only used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; and the modifications, changes or substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention. Are intended to be covered by the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.