阅读说明：本技术 一种相控阵雷达驱动控制电路内嵌eeprom存储器自动化测试装置 (Automatic testing device for embedded EEPROM (electrically erasable programmable read-Only memory) of phased array radar drive control circuit ) 是由 张鹏伟 邬君 王恪良 邵昕 赵康 姚永昶 于 2020-12-09 设计创作，主要内容包括：本发明提供了一种相控阵雷达驱动控制电路内嵌EEPROM存储器自动化测试装置,包括：主控处理器、按键启动模块、EEPROM存储器写读模块、数据比较模块、结果显示模块、供电模块等。所述主控处理器通过按键启动模块执行电路EEPROM存储器测试命令,所述EEPROM存储器写读模块按照写读时序要求实现EEPROM存储器写读操作,所述数据比较显示模块实现存储器写读结果比较,所述显示模块实现测试结果的显示功能,所述供电模块为整板元器件提供各种的电源电压。该方案可用于实现相控阵雷达驱动控制电路内嵌存储器自动化一键测试功能。(The invention provides an automatic testing device for an EEPROM (electrically erasable programmable read-Only memory) memory embedded in a phased array radar drive control circuit, which comprises: the device comprises a main control processor, a key starting module, an EEPROM memory writing and reading module, a data comparison module, a result display module, a power supply module and the like. The main control processor executes a circuit EEPROM memory test command through the key starting module, the EEPROM memory writing and reading module realizes writing and reading operations of the EEPROM memory according to writing and reading time sequence requirements, the data comparison and display module realizes writing and reading result comparison of the memory, the display module realizes a test result display function, and the power supply module provides various power supply voltages for the whole panel component. The scheme can be used for realizing the automatic one-key test function of the embedded memory of the phased array radar drive control circuit.)

1. The utility model provides an embedded EEPROM memory automatic testing arrangement of phased array radar drive control circuit which characterized in that: the device comprises a main control processor, a key starting module, an EEPROM memory writing and reading module, a data comparison module, a result display module and a power supply module;

the main control processor starts initialization after being powered on, is in a waiting starting state, receives a starting signal of a key starting module after a circuit to be tested is powered on, and performs power-on connectivity detection on the circuit to be tested to ensure that the circuit to be tested is correctly placed in a test socket; the circuit to be tested enters a normal working mode, the main control processor performs multiple test writing read-back operations on the embedded EEPROM, automatic data comparison is performed through the data comparison module, and the result is displayed through the result display module;

the key starting module is used as a mark for starting the main control processor to start working and is realized by a key switch and a corresponding signal driving device;

the EEPROM memory writing and reading module generates writing and reading parallel signals for the EEPROM embedded in the phased array radar drive control circuit according to specific time sequence requirements, and writes and reads data back;

the data comparison module is used for comparing the test writing data with the read-back data and verifying whether the EEPROM function of the circuit is normal or not to obtain a test result;

the result display module carries out interface-free display on the test result, and the display is realized through LED indicator lamps with three different colors of red, yellow and green and a signal driving and current protection device, wherein the red indicates that the test is unqualified, and the yellow indicates that the test is qualified;

the power supply module provides power supply voltages with various different amplitudes for the whole board element, and meanwhile, the device is provided with a circuit module for converting 5V into 4.5V and 5.5V, and can test a circuit to be tested working at the voltages of 4.5V, 5V and 5.5V, so that the compatibility of the testing device is improved.

2. The automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit as claimed in claim 1, characterized in that: the main control processor receives the starting signal through the key starting module, executes the test command, and sequentially completes connectivity test, circuit initialization configuration, EEPROM write-in and read-back data comparison according to the corresponding command to obtain a test result and sends a signal of the test result to the result display module.

3. The automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit as claimed in claim 1, characterized in that: the key starting module consists of a key switch and a corresponding driving device, a low pulse signal is generated through the key switch, the main control processor starts a test working mode after receiving the signal, and after a test process is completed, the main control processor enters a state of waiting for starting a signal and waits for a signal sent by the next key starting module.

4. The automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit as claimed in claim 1, characterized in that: the EEPROM test writing and read-back module generates parallel writing and reading timing sequence signals, firstly test writing is carried out on the full addresses of the EEPROM of the circuit to be tested one by one, read-back operation is carried out after the test writing of the full addresses is completed, read-back data is sent to the data comparison module for subsequent operation processing, the data comparison module obtains a test result through data comparison processing, and test writing or read-back function testing of the circuit EEPROM is completed.

5. The automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit as claimed in claim 1, characterized in that: the data comparison module compares the read-back data of each address with the test writing data one by one, if the data are consistent, the data comparison of the next address is carried out, if the data are inconsistent, a test error signal is generated, and the current test flow is interrupted; and generating a test pass signal after all the address tests pass, and finishing the data comparison function.

6. The automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit as claimed in claim 1, characterized in that: the result display module consists of an LED, a driving device and a current protection device, and realizes real-time and accurate display of the test result without a display interface.

7. The automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit as claimed in claim 1, characterized in that: the power supply module provides power supply voltages with different amplitudes for the main control processor and the whole board element and is provided with 5V and 12V power supply circuits; the power supply module provides power supplies with amplitudes of 4.5V, 5V, 5.5V and the like for the circuit to be tested, the power supply of the circuit to be tested is controlled by the key switch, and the power supply module has the functions of overheat protection and undervoltage protection.

8. An automatic test method for an embedded memory of a phased array radar drive control circuit is characterized by comprising the following steps:

(1) the main control processor enters a waiting state after being powered on, and starts a test mode after waiting for a key starting module to send a starting test signal;

(2) the main control processor carries out power-on connectivity detection on a circuit to be detected, carries out initialization configuration and enters a working state;

(3) the main control processor starts an EEPROM test writing mode, sends a display signal in test work and starts a yellow LED lamp of the display module;

(4) starting test operation, firstly carrying out an EEPROM (electrically erasable programmable read-only memory) trial writing time sequence, wherein the trial writing data is 0x155, and starting a read-back EEPROM time sequence after all address trial writing is finished;

(5) in the process of readback EERPOM data, starting data comparison, carrying out data comparison once when address data are read back, interrupting the current EEPROM readback time sequence if the data comparison is inconsistent, sending a test non-passing signal to the main control processor, and generating a test passing signal to the main control processor if the data comparison is completely consistent in the whole test process;

(6) the replacement trial writing data is 0x0 AA; repeating the testing processes of the steps (3), (4) and (5);

(7) the main control processor receives the result signals sent by the result comparison module, sends different result signals to the result display module according to different information, and the test passes the turn-on of the green LED lamp and does not pass the turn-on of the red LED lamp;

(8) and after the test is finished, the power supply of the circuit to be tested is turned off, the circuit to be tested is replaced, and the main control processor enters a waiting working state to wait for starting a test signal next time.

Technical Field

The invention relates to an automatic test device for an EEPROM (electrically erasable programmable read-only memory) memory embedded in a phased array radar drive control circuit, which is used for carrying out automatic read-write function test on the EEPROM embedded in the circuit in the production process of the phased array radar drive control circuit, can be operated in a multi-station parallel mode and independently, and greatly improves the production test efficiency of the circuit.

Background

Generally, a general test machine is adopted for the write-read test of the EEPROM embedded in the phased array radar drive control circuit, complex test programs and vectors need to be developed, the resources of a test hardware board card are limited, only a single circuit test can be carried out, the test time is fixed due to the write-read time sequence requirement, the test time reaches 120 seconds, 1 person is needed for operation, and the test efficiency is low.

Disclosure of Invention

The technical problem solved by the invention is as follows: the automatic test device for the embedded EEPROM of the phased array radar drive control circuit is capable of automatically testing the test writing and reading functions of the embedded EEPROM of the phased array radar drive control circuit, 1 person can simultaneously operate a plurality of test devices, the test efficiency is improved, and the general test machine and the labor cost are saved.

The technical solution of the invention is as follows: an automatic test device for an EEPROM (electrically erasable programmable read-only memory) memory embedded in a phased array radar drive control circuit comprises a main control processor, a key starting module, an EEPROM memory writing and reading module, a data comparison module, a result display module and a power supply module;

the main control processor starts initialization after being powered on, is in a waiting starting state, receives a starting signal of a key starting module after a circuit to be tested is powered on, and performs power-on connectivity detection on the circuit to be tested to ensure that the circuit to be tested is correctly placed in a test socket; the circuit to be tested enters a normal working mode, the main control processor performs multiple test writing read-back operations on the embedded EEPROM, automatic data comparison is performed through the data comparison module, and the result is displayed through the result display module;

the key starting module is used as a mark for starting the main control processor to start working and is realized by a key switch and a corresponding signal driving device;

the EEPROM memory writing and reading module generates writing and reading parallel signals for the EEPROM embedded in the phased array radar drive control circuit according to specific time sequence requirements, and writes and reads data back;

the data comparison module is used for comparing the test writing data with the read-back data and verifying whether the EEPROM function of the circuit is normal or not to obtain a test result;

the result display module carries out interface-free display on the test result, and the display is realized through LED indicator lamps with three different colors of red, yellow and green and a signal driving and current protection device, wherein the red indicates that the test is unqualified, and the yellow indicates that the test is qualified;

the power supply module provides power supply voltages with various different amplitudes for the whole board element, and meanwhile, the device is provided with a circuit module for converting 5V into 4.5V and 5.5V, and can test a circuit to be tested working at the voltages of 4.5V, 5V and 5.5V, so that the compatibility of the testing device is improved.

The main control processor receives the starting signal through the key starting module, executes the test command, and sequentially completes connectivity test, circuit initialization configuration, EEPROM write-in and read-back data comparison according to the corresponding command to obtain a test result and sends a signal of the test result to the result display module.

The key starting module consists of a key switch and a corresponding driving device, a low pulse signal is generated through the key switch, the main control processor starts a test working mode after receiving the signal, and after a test process is completed, the main control processor enters a state of waiting for starting a signal and waits for a signal sent by the next key starting module.

The EEPROM test writing and read-back module generates parallel writing and reading timing sequence signals, firstly test writing is carried out on the full addresses of the EEPROM of the circuit to be tested one by one, read-back operation is carried out after the test writing of the full addresses is completed, read-back data is sent to the data comparison module for subsequent operation processing, the data comparison module obtains a test result through data comparison processing, and test writing or read-back function testing of the circuit EEPROM is completed.

The data comparison module compares the read-back data of each address with the test writing data one by one, if the data are consistent, the data comparison of the next address is carried out, if the data are inconsistent, a test error signal is generated, and the current test flow is interrupted; and generating a test pass signal after all the address tests pass, and finishing the data comparison function.

The result display module consists of an LED, a driving device and a current protection device, and realizes real-time and accurate display of the test result without a display interface.

The power supply module provides power supply voltages with different amplitudes for the main control processor and the whole board element and is provided with 5V and 12V power supply circuits; the power supply module provides power supplies with amplitudes of 4.5V, 5V, 5.5V and the like for the circuit to be tested, the power supply of the circuit to be tested is controlled by the key switch, and the power supply module has the functions of overheat protection and undervoltage protection.

An automatic test method for an embedded memory of a phased array radar drive control circuit comprises the following steps:

(1) the main control processor enters a waiting state after being powered on, and starts a test mode after waiting for a key starting module to send a starting test signal;

(2) the main control processor carries out power-on connectivity detection on a circuit to be detected, carries out initialization configuration and enters a working state;

(3) the main control processor starts an EEPROM test writing mode, sends a display signal in test work and starts a yellow LED lamp of the display module;

(4) starting test operation, firstly carrying out an EEPROM (electrically erasable programmable read-only memory) trial writing time sequence, wherein the trial writing data is 0x155, and starting a read-back EEPROM time sequence after all address trial writing is finished;

(5) in the process of readback EERPOM data, starting data comparison, carrying out data comparison once when address data are read back, interrupting the current EEPROM readback time sequence if the data comparison is inconsistent, sending a test non-passing signal to the main control processor, and generating a test passing signal to the main control processor if the data comparison is completely consistent in the whole test process;

(6) the replacement trial writing data is 0x0 AA; repeating the testing processes of the steps (3), (4) and (5);

(7) the main control processor receives the result signals sent by the result comparison module, sends different result signals to the result display module according to different information, and the test passes the turn-on of the green LED lamp and does not pass the turn-on of the red LED lamp;

(8) and after the test is finished, the power supply of the circuit to be tested is turned off, the circuit to be tested is replaced, and the main control processor enters a waiting working state to wait for starting a test signal next time.

Compared with the prior art, the invention has the beneficial effects that:

the automatic test device for the embedded EEPROM memory of the phased array radar drive control circuit can realize one-key automatic test of the write-read function of the embedded EEPROM memory of the circuit, has small volume and low cost, can simultaneously test a plurality of circuits to be tested, greatly reduces manpower and material resources required by the test, and greatly improves the production test efficiency of the phased array radar drive control circuit.

Drawings

FIG. 1 is a diagram of the hardware design of the present invention;

FIG. 2 is a flow chart of the test of the present invention.

Detailed Description

As shown in fig. 1, the main control processor is controlled by the key start module, when a start signal is received and a test mode is started, the main control processor firstly performs power-on connectivity detection on a circuit to be tested, initializes the circuit to be tested after normal communication, and enables the circuit to be tested to enter a normal working mode (i.e. under a read-write EEPROM mode); starting a writing and reading EEPROM module function, generating a parallel trial writing EEPROM timing signal of 4 Kx 9bit, wherein the trial writing data is 0x155, reading back the EEPROM timing after trial writing, if the data is not 0x155, interrupting the test to generate a test fail signal, continuing the next test if the data comparison is consistent, performing the trial writing operation again, wherein the trial writing data is 0x0AA, then reading back to perform the data comparison to obtain a test result, and performing the EEPROM test twice to ensure that each bit of data of the embedded EEPROM of the circuit to be tested has jump (namely 0-1, 1-0) and ensure the test coverage rate requirement; the test result generated by the test is displayed by a result display module through corresponding signals generated by a main control processor, wherein the green LED lamp in the display module is on to represent that the test is passed, the red LED lamp is on to represent that the test is not passed, and the yellow LED lamp is on to represent that the test is in progress.

FIG. 2 is a flow chart of the test of the present invention, which is implemented as follows:

(1) the main control processor enters a waiting state after being powered on, and starts a test mode after waiting for a key starting module to send a starting test signal;

(2) the main control processor carries out power-on connectivity detection on a circuit to be detected, carries out initialization configuration and enters a working state;

(3) the main control processor starts an EEPROM test writing mode, sends a display signal in test work and starts a yellow LED lamp of the display module;

(4) starting test operation, firstly carrying out an EEPROM (electrically erasable programmable read-only memory) trial writing time sequence, wherein the trial writing data is 0x155, and starting a read-back EEPROM time sequence after all address trial writing is finished;

(5) in the process of readback EERPOM data, starting data comparison, carrying out data comparison once when address data are read back, interrupting the current EEPROM readback time sequence if the data comparison is inconsistent, sending a test non-passing signal to the main control processor, and generating a test passing signal to the main control processor if the data comparison is completely consistent in the whole test process;

(6) the replacement trial writing data is 0x0 AA; repeating the test processes (3), (4) and (5);

(7) the main control processor receives the result signals sent by the result comparison module, sends different result signals to the result display module according to different information, and the test passes the turn-on of the green LED lamp and does not pass the turn-on of the red LED lamp;

(8) and after the test is finished, the power supply of the circuit to be tested is turned off, the circuit to be tested is replaced, and the main control processor enters a waiting working state to wait for starting a test signal next time.

Example (b):

the main controller adopts a high-performance and low-power-consumption AVR microprocessor, an SRAM, a programmable FLASH, 32 8-bit general working registers and 32 programmable I/0 ports are integrated in the main controller, and the working speed reaches 16 MHz.

The key starting module selects a key switch with high sensitivity, low resistance value and high reliability; the test writing read-back EEPROM module generates 9 paths of parallel data, and the driving capability of each path reaches 20 mA. The test writing read-back signal adopts 0x155 and 0x0AA as test writing data, and respectively writes and reads time sequences for the whole address of the EEPROM twice, thereby ensuring that each storage bit is subjected to the jump of '0' and '1', ensuring the reliability and coverage rate of the test, and the mutual influence possibly existing on special address bits.

The result display module is composed of a high-durability and high-reliability LED lamp, a corresponding driving circuit and a current-limiting protection resistor; the power supply module adopts an LDO power supply module, the 12V voltage is adjusted to be 5V working voltage, the testing device and the circuit to be tested are independently powered, and the power supply end of the circuit to be tested is controlled by the key switch to supply power. Meanwhile, the device is provided with a 5V-to-4.5V and 5.5V circuit module, and can test a circuit to be tested working under 4.5V, 5V and 5.5V voltages, so that the compatibility of the testing device is improved.

After the test device is powered on and started, a main program runs on an internal SRAM (static random access memory), firstly, the test device enters a waiting starting state, a starting signal triggers a test working module, the working state of an I/O (input/output) interface of other modules and a circuit to be tested starts to be initialized and butted, and then the test device enters a test working mode. In the working mode, a yellow LED lamp of a display module is started, at the moment, a processor shields starting information sent by a key starting module, a readback time sequence runs and a data comparison module is started in the process of writing and reading EEPROM test, the comparison module obtains a test FALSE result, the current writing and reading module is interrupted to work, the FLASE result is sent to a result display module, and the display module starts a red LED lamp to indicate that the test is not passed; if the read module does not have a FALSE result in the running process, after the read module runs completely, the comparison module obtains a final PASS result, the processor orders the result display module to display a test passing result according to a test result PASS signal, and the green LED lamp is started to indicate that the test is passed, namely, the automatic test task of the EEPROM memory embedded in the phased array radar drive control circuit is completed once. And after the result display module displays the test result, the main processor enters the waiting starting mode again. The specific implementation process is as follows:

(1) the main control processor enters a waiting state after being powered on, and starts a test mode after waiting for a key starting module to send a starting test signal;

(2) the main control processor carries out power-on connectivity detection on a circuit to be detected, carries out initialization configuration and enters a working state;

(3) the main control processor starts an EEPROM test writing mode, sends a display signal in test work and starts a yellow LED lamp of the display module;

(4) starting test operation, firstly carrying out an EEPROM (electrically erasable programmable read-only memory) trial writing time sequence, wherein the trial writing data is 0x155, and starting a read-back EEPROM time sequence after all address trial writing is finished;

(5) in the process of readback EERPOM data, starting data comparison, carrying out data comparison once when address data are read back, interrupting the current EEPROM readback time sequence if the data comparison is inconsistent, sending a test non-passing signal to the main control processor, and generating a test passing signal to the main control processor if the data comparison is completely consistent in the whole test process;

(6) the replacement trial writing data is 0x0 AA; repeating the testing processes of the steps (3), (4) and (5);

(7) the main control processor receives the result signals sent by the result comparison module, sends different result signals to the result display module according to different information, and the test passes the turn-on of the green LED lamp and does not pass the turn-on of the red LED lamp;

(8) and after the test is finished, the power supply of the circuit to be tested is turned off, the circuit to be tested is replaced, and the main control processor enters a waiting working state to wait for starting a test signal next time.