阅读说明：本技术 一种主板及其信号转接系统 (Mainboard and signal switching system thereof ) 是由 张世强 于 2020-12-03 设计创作，主要内容包括：本发明公开了一种信号转接系统,硬盘接口本身能够给出指示自身所连接硬盘类型的信号,而本申请中的信号通道切换器能够根据硬盘接口所接硬盘的类型而适应性地选择将自身第一端与第二端或第三端连通,也即在所接硬盘为NVMe硬盘时,可以直接连通硬盘接口与CPU,在所接硬盘为SATA硬盘时,可以在CPU以及硬盘接口之间连接协议转换器进行协议转换,因此用户可任意选择SATA硬盘或者NVMe硬盘进行连接使用,提高了硬盘选择的灵活性,提升了用户体验。本发明还公开了一种主板,具有如上信号转接系统相同的有益效果。(The invention discloses a signal switching system, wherein a hard disk interface can give a signal indicating the type of a hard disk connected with the hard disk interface, a signal channel switcher in the application can adaptively select to communicate a first end with a second end or a third end according to the type of the hard disk connected with the hard disk interface, namely, when the connected hard disk is an NVMe hard disk, the hard disk interface can be directly communicated with a CPU, and when the connected hard disk is an SATA hard disk, a protocol converter can be connected between the CPU and the hard disk interface for protocol conversion, so that a user can randomly select the SATA hard disk or the NVMe hard disk for connection and use, the flexibility of hard disk selection is improved, and the user experience is improved. The invention also discloses a mainboard which has the same beneficial effects as the signal switching system.)

1. A signal relay system, comprising:

the signal channel switcher is used for communicating the first end and the third end of the signal channel switcher with the CPU when the hard disk interface is detected to be connected with a nonvolatile memory standard NVMe hard disk, and communicating the first end and the second end of the signal channel switcher with the hard disk interface when the hard disk interface is detected to be connected with a serial advanced technology attachment SATA hard disk;

and the protocol converter is connected with the CPU and is used for converting the protocol type of the received data into the other one of NVMe and SATA.

2. The signal transfer system of claim 1, further comprising:

the communication device is respectively connected with the baseboard management controller BMC and the hard disk interface and is used for reading the pre-stored basic information of the hard disk connected with the hard disk interface by the BMC;

the BMC.

3. The signal transfer system of claim 2, wherein the communication device is a level shifting chip connected to the BMC and a bus interface of the hard disk interface, respectively.

4. The signal transfer system of claim 2, further comprising:

the complex programmable logic device CPLD is respectively connected with the hard disk interface, the BMC and the CPU and is used for sending the state information of the hard disk interface to the BMC and the CPU;

the state information comprises the type of the connected hard disk and the in-place state of the hard disk.

5. The signal relay system of claim 4, wherein the CPLD is further configured to:

and the CPU controls the hard disk interface to reset through the CPU.

6. The signal transfer system of claim 5, wherein the CPLD is further connected to the protocol converter;

the CPLD is also used by the CPU to control the protocol converter to reset through it.

7. The signal transfer system of claim 2, wherein the hard disk interface is an m.2 connector interface.

8. The signal forwarding system of claim 2 wherein the CPU is an Ampere processor.

9. The signal transfer system of any one of claims 2 to 8, further comprising a reminder;

the BMC is also used for controlling a prompter to prompt the pre-stored basic information.

10. A motherboard comprising a signal transfer system as claimed in any one of claims 1 to 9.

Technical Field

The invention relates to the field of computers, in particular to a signal switching system and a mainboard.

Background

In the computer device, some CPUs can process signals of SATA (Serial Advanced Technology Attachment) protocol and signals of NVMe (Non-Volatile Memory standard) protocol, so that the CPUs can be arbitrarily connected with NVMe hard disks (hard disks based on NVMe protocol communication) or SATA (hard disks based on SATA protocol communication) through a physical interface for use, however, some CPUs can only process signals of NVMe protocol, so that a user can only select an NVMe hard disk when using the computer device with the CPUs, and the flexibility of hard disk selection is poor, which affects user experience.

Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a signal switching system, which can be used for connecting and using an SATA hard disk or an NVMe hard disk arbitrarily selected by a user, thereby improving the flexibility of hard disk selection and improving the user experience; another object of the present invention is to provide a motherboard including the above signal switching system, wherein a user can arbitrarily select a SATA hard disk or an NVMe hard disk for connection, so as to improve flexibility of hard disk selection and enhance user experience.

In order to solve the above technical problem, the present invention provides a signal transfer system, including:

the signal channel switcher is used for communicating the first end and the third end of the signal channel switcher with the CPU when the hard disk interface is detected to be connected with a nonvolatile memory standard NVMe hard disk, and communicating the first end and the second end of the signal channel switcher with the hard disk interface when the hard disk interface is detected to be connected with a serial advanced technology attachment SATA hard disk;

and the protocol converter is connected with the CPU and is used for converting the protocol type of the received data into the other one of NVMe and SATA.

Preferably, the signal transfer system further comprises:

the communication device is respectively connected with the baseboard management controller BMC and the hard disk interface and is used for reading the pre-stored basic information of the hard disk connected with the hard disk interface by the BMC;

the BMC.

Preferably, the communication device is a level conversion chip connected to the BMC and a bus interface of the hard disk interface, respectively.

Preferably, the signal transfer system further comprises:

the complex programmable logic device CPLD is respectively connected with the hard disk interface, the BMC and the CPU and is used for sending the state information of the hard disk interface to the BMC and the CPU;

the state information comprises the type of the connected hard disk and the in-place state of the hard disk.

Preferably, the CPLD is further configured to:

and the CPU controls the hard disk interface to reset through the CPU.

Preferably, the CPLD is further connected with the protocol converter;

the CPLD is also used by the CPU to control the protocol converter to reset through it.

Preferably, the hard disk interface is an m.2 connector interface.

Preferably, the CPU is an Ampere processor.

Preferably, the signal transfer system further comprises a prompter;

the BMC is also used for controlling a prompter to prompt the pre-stored basic information.

In order to solve the above technical problem, the present invention further provides a motherboard including the signal switching system described above.

The invention provides a signal switching system, a hard disk interface can give a signal indicating the type of a hard disk connected with the hard disk interface, a signal channel switcher in the signal switching system can adaptively select to connect a first end of the signal channel switcher with a second end or a third end according to the type of the hard disk connected with the hard disk interface, namely, when the connected hard disk is an NVMe hard disk, the signal channel switcher can directly connect the hard disk interface with a CPU, and when the connected hard disk is an SATA hard disk, a protocol converter can be connected between the CPU and the hard disk interface for protocol conversion, so that a user can randomly select the SATA hard disk or the NVMe hard disk for connection and use, the flexibility of hard disk selection is improved, and the user experience is improved.

The invention also provides a mainboard which has the same beneficial effects as the signal switching system.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a signal transfer system according to the present invention;

fig. 2 is a schematic structural diagram of another signal forwarding system provided by the present invention.

Detailed Description

The core of the invention is to provide a signal switching system, a user can randomly select an SATA hard disk or an NVMe hard disk for connection use, the flexibility of hard disk selection is improved, and the user experience is improved; the main board comprises the signal switching system, and a user can randomly select a SATA hard disk or an NVMe hard disk for connection and use, so that the flexibility of hard disk selection is improved, and the user experience is improved.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a signal forwarding system provided by the present invention, the signal forwarding system includes:

the signal channel switcher 1 is used for communicating the first end and the third end of the signal channel switcher with the CPU when the hard disk interface is detected to be connected with a nonvolatile memory standard NVMe hard disk, and communicating the first end and the second end of the signal channel switcher with the hard disk interface when the signal channel switcher detects that the hard disk interface is connected with a serial advanced technology attachment SATA hard disk;

and the protocol converter 2 is connected with the CPU and is used for converting the protocol type of the received data into the other one of NVMe and SATA.

Specifically, in view of the technical problems in the above background art, in order to be compatible with the SATA hard disk, hardware may be added to convert the SATA protocol into the NVMe protocol for processing by the CPU, but if the NVMe hard disk is connected, data does not need to pass through the protocol converter 2, so that the signal channel switch 1 may be used to switch the signal channel, so that the CPU can normally operate when the hard disks of different protocols are connected, and in view of that the hard disk interface itself can give a signal indicating the type of the hard disk connected to itself, the detection end of the signal channel switch 1 may be connected to the hard disk interface, so that the signal provided by the hard disk interface can distinguish the protocol type of the hard disk connected to the hard disk interface and correspondingly communicate the signal channel, so that the computer device where the CPU is located can be compatible with the NVMe protocol and the hard disk of the SATA protocol, the user can select and use flexibly, and the user experience is improved.

Specifically, the protocol converter 2 may be of various types, for example, the protocol converter 2ASM1062R may be adopted, the ASM1062R may support a hard RAID (Redundant Arrays of Independent Disks), and support RAID0 and RAID1 to meet RAID requirements of a server group, and may convert 2-way 6Gbps SATA signals.

The signal channel switch 1 may be of various types, for example, a high-speed signal switch PI3DBS16212 zbex may be adopted, the PI3DBS16212 zbex supports high-speed signals up to 20Gbps, the 2-way differential signal a may perform B/C channel switching, the Ampere platform server m.2 requires to support PCIe GEN4 and SATA3.2, and needs to meet the requirements of PCIe GEN4 for communication rates of 16Gbps and sat 3.26gbps, and the PI3DBS16212 zbex may meet the requirements of design and use.

The invention provides a signal switching system, a hard disk interface can give a signal indicating the type of a hard disk connected with the hard disk interface, a signal channel switcher in the signal switching system can adaptively select to connect a first end of the signal channel switcher with a second end or a third end according to the type of the hard disk connected with the hard disk interface, namely, when the connected hard disk is an NVMe hard disk, the signal channel switcher can directly connect the hard disk interface with a CPU, and when the connected hard disk is an SATA hard disk, a protocol converter can be connected between the CPU and the hard disk interface for protocol conversion, so that a user can randomly select the SATA hard disk or the NVMe hard disk for connection and use, the flexibility of hard disk selection is improved, and the user experience is improved.

For better explaining the embodiment of the present invention, please refer to fig. 2, fig. 2 is a schematic structural diagram of another signal forwarding system provided by the present invention, and on the basis of the above embodiment:

as a preferred embodiment, the signal transfer system further comprises:

the communication device 3 is respectively connected with the baseboard management controller BMC 4 and the hard disk interface and is used for reading the pre-stored basic information of the hard disk connected with the hard disk interface by the BMC 4;

BMC 4。

specifically, in consideration of the fact that the computer device needs to manage the basic information of the hardware connected to the computer device, in the embodiment of the present invention, the BMC 4 may read the pre-stored basic information of the connected hard disk through the communication device 3 and the hard disk interface, so as to conveniently acquire and manage the basic information of the connected hard disk.

The pre-stored basic information may be of various types, such as the capacity size and brand of the even hard disk, and the pre-stored basic information may be stored in an FRU (Field replaceable Unit) of the hard disk.

The BMC 4 may be of various types, for example, a General BMC 4 chip AST2500 may be selected, and has 14 paths of I2C buses and multiple paths of GPIOs (General-purpose input/output interfaces), and the BMC 4 in the embodiment of the present invention may have 1 path of I2C and 2 paths of GPIO interfaces, where the I2C interface is used to communicate with an I2C interface of an m.2 connector interface, so as to implement reading of information of a hard disk FRU of an SATA/NVMe m.2 interface.

Specifically, the channel a of the signal channel switch 1 in fig. 2 is the first end, the channel B is the second end, and the channel C is the third end.

In a preferred embodiment, the communication device 3 is a level conversion chip connected to the BMC 4 and a bus interface of the hard disk interface.

Specifically, in practical applications, the I2C level of the BMC 4 may be +3.3V, and the I2C level of the m.2 connector interface may be +1.8V, so that the I2C communication level conversion function between the BMC 4 and the m.2 connector interface may be implemented by the level conversion chip.

Specifically, the level shifting chip may be of various types, for example, the I2C repeater chip PCA9617A may be selected for level shifting of the I2C interface, and the I2C driving capability may be improved, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, the signal transfer system further comprises:

the complex programmable logic device CPLD5 is respectively connected with the hard disk interface, the BMC 4 and the CPU and is used for sending the state information of the hard disk interface to the BMC 4 and the CPU;

the state information comprises the type of the connected hard disk and the on-site state of the hard disk.

Specifically, in order to facilitate the BMC 4 and the CPU to manage the state information of the hard disk interface respectively, the CPLD5 with a plurality of interfaces may be used in the embodiment of the present invention to obtain the state information of the hard disk interface and send the state information to the BMC 4 and the CPU.

The state information may be of other types besides the type of the connected hard disk and the on-site state of the hard disk, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, CPLD5 is also configured to:

the CPU controls the hard disk interface to reset through the CPU.

Specifically, in some cases, a reset operation needs to be performed on the hard disk interface, for example, a repair is attempted by resetting the hard disk interface when the hard disk data interaction is abnormal, so the CPU can also reset the hard disk interface through the CPLD5, and the CPLD5 can receive an instruction issued by the CPU and perform reset control on the hard disk interface.

As a preferred embodiment, the CPLD5 is also connected to the protocol converter 2;

the CPLD5 is also used for CPU reset by its control protocol converter 2.

Specifically, it is considered that a reset operation of the protocol converter 2 is required in some cases, for example, in the case where the protocol converter 2 is abnormally operated, the protocol converter 2 may be controlled to be reset under the control of the CPU for failure recovery.

Specifically, CPLD5 may be of various types, for example, CPLD5 chip lcmcxo 2-7000HC-4FG484C may be selected, CPLD5 is used in the PRESENT invention to design m.2 connector interface reset signal and protocol converter 2 reset signal, and PEDET, PRESENT, PEWAKE _ n signals of m.2 connector interface are transmitted to GPIO [2:0] of BMC 4 and GPIO [2:0] of Ampere processor, respectively, BIOS (Basic Input Output System) of Ampere platform server of the PRESENT invention may design CPLD5 to design m.2 connector interface reset signal and protocol converter 2 reset signal by using CPU0_ GPIO [19:16] to encode, CPLD5 may perform reset control according to preset reset setting truth table, CPLD5 outputs the m.2 connector interface reset signal at normal time as high level and outputs the protocol converter 2 reset signal as high level, when CPLD5 detects that CPLD 0_ GPIO [19: 0011 ] is in CPLD state, the M.2 connector interface and the protocol converter 2 can be triggered to reset simultaneously, a 150ms low pulse signal can be output to control the reset, the M.2 connector interface can be reset separately when the CPLD5 detects that the state of the CPU0_ GPIO [19:16] is 0111, and the protocol converter 2 can be reset separately when the CPLD5 detects that the state of the CPU0_ GPIO [19:16] is 1000.

In addition, the CPLD5 can transmit PEDET, PRESENT _ n and PEWAKE _ n signals of the M.2 connector interface to GPIO [2:0] of the BMC 4, the two interfaces can be directly connected if the voltage characteristics of the two interfaces are consistent, and due to the fact that the voltage characteristics of the GPIO [2:0] transmitted to the Ampere processor are inconsistent, an anti-leakage design is needed, and therefore anti-leakage diodes are connected in series on signal paths of the PEDET, PRESENT _ n and PEWAKE _ n.

The level of PEDET may indicate the type of the connected hard disk, for example, when PEDET is low, it may indicate that the type of the connected hard disk is a SATA hard disk, and when PEDET is high, it may indicate that the type of the connected hard disk is an NVMe hard disk, and the level of detect _ n signal may indicate whether the hard disk is in place, for example, it may indicate that the hard disk is in place by low, it may indicate that the hard disk is not in place by high, PEWAKE _ n may be in a high impedance state by default, and when it is low, it may trigger PCIe (Peripheral Component Interconnect express) wakeup, and PERST _ n is an input signal of the m.2 connector interface, and the signal is used for resetting the SATA/NVMe m.2 hard disk, which is not limited herein.

As a preferred embodiment, the hard disk interface is an m.2 connector interface.

Specifically, the m.2 connector interface has the advantages of small volume, low price, long service life, and the like.

Of course, the hard disk interface may be of other types besides the m.2 connector interface, and the embodiment of the present invention is not limited herein.

In a preferred embodiment, the CPU is an Ampere processor.

Specifically, the Ampere processor has the advantages of strong performance, multiple functions and the like.

The Ampere processor adopts an Altra/Altra Max processor, the processor is based on an ARM Neoverse N1 enterprise-level kernel architecture, four-emission superscalar out-of-order execution is realized, an ARM v8.2 Instruction set is supported, partial characteristics of ARM v8.3 and ARM v8.5 are used for reference, the Ampere processor is provided with two SIMD (Single Instruction Multiple Data) 128 bit units and supports FP16 floating point and INT integer arithmetic, Altra and Altra Max Pin to are compatible and replaceable, and Altra Max is an enhancement type Altra Max. All cores are connected in series through a Mesh network, each core is provided with a 64KB first-level instruction cache, a 64KB first-level data cache and a 1MB second-level cache, all cores share a 32MB third-level cache, and all levels of caches support ECC (Error correction Code). The memory supports eight-channel DDR4-3200 ECC with at most two channels, at most 16 single channels in total and 4TB maximum capacity. It supports single or dual lane parallelism, each providing 128 PCIe 4.0 buses, 32 of which are used for interconnect with each other, 96 out, and 192 PCIe 4.0 buses can be provided for dual lane. The Ampere processor is the core of the platform, and the related hardware resources of the invention comprise GPIO [4:0], GPIO [21:16] and CPU0_ RCB0A _ D [5:0 ]. GPIO [2:0] is used for reading M.2 connector interface signals PEDET, PRESENT _ n and PEWAKE _ n, and the Ampere processor can respectively identify the SATA/NVMe M.2 hard disk type, whether the hard disk type is in place or not and whether the hard disk type is awakened by triggering PEWAKE _ n through the GPIO [2:0 ]. GPIO [4:3] is connected to the MODE control pin GPIO [1:0] of the protocol converter 2, and can control the working MODE of the protocol converter 2 according to the following table 1. CPU0_ RCB0A _ D [5:4] of Ampere processor is connected with protocol converter 2, and SATA _ A and SATA _ B signals can be expanded. The CPU0_ RCB0A _ D [3:0] of the Ampere processor is connected with the signal channel switch 1, and PCIe x4 required by NVMe can be introduced into the signal channel switch 1 for the M.2 connector 4 to use.

TABLE 1

Specifically, in the embodiment of the present invention, the SEL of the signal path switch 1 is connected to the PEDET signal of the m.2 connector interface, and the PD pin of the signal path switch 1 is grounded. As shown in table 2 below, when the PEDET is at a low level, An to Bn transmits the SATA signal of the protocol converter 2 to the channel a; when PEDET is high, An to Cn transmits PCIe signals corresponding to the Ampere processor into the A channel.

TABLE 2

The Clock CLK gen uses an 8-channel PCIe Clock generator 9FGL0851CKILFT for generating a multi-channel PCIe Clock. The CLK gen can be respectively interfaced with the Ampere processor, the protocol converter 2 and the M.2 connector to provide 100MHz PCIe clocks, and the design of the invention adopts the PCIe clock homologous and in-phase design and meets the design requirement of the Ampere platform.

Specifically, in the using process, the Ampere platform server is powered on and started, the BMC 4 can access the hard disk inserted into the M.2 connector interface through the I2C bus, and the FRU information such as the capacity and the brand of the hard disk can be read; in addition, both BMC 4 and Ampere processors may communicate with each other via respective GPIOs [2:0] is connected to the CPLD5, and indirectly can read the PEDET, PRESENT _ n, and PEWAKE _ n states of the M.2 connector. By reading the PEDET state of the m.2 connector, the type of the hard disk inserted into the m.2 connector interface can be known, and by reading the PRESENT _ n state of the m.2 connector, whether the hard disk is inserted into the m.2 connector interface can be known. By reading the m.2 connector PEWAKE _ n signal to a low level signal, the BMC 4 and the Ampere processor may trigger an interrupt, which may be used to perform a server wake-up function. PCIe resources of the Ampere processor are rich, GPIO [19:16] is designed and coded for PCIe peripheral reset, the GPIO [19:16] is output as 0000 during initial power-on to trigger global reset of all PCIe peripheral, when the GPIO [19:16] is set to output as 0011 during use, the M.2 connector interface and the protocol converter 2 are triggered to reset simultaneously, and 150ms low pulse signals are output after reset. CPLD5 individually resets the M.2 connector interface when detecting that CPU0_ GPIO [19:16] state is "0111", and individually resets protocol converter 2 when detecting that CPU0_ GPIO [19:16] state is "1000", at which time the registers of protocol converter 2 will resume the default power-on state. The Ampere processor CPU0_ RCB 0_ 0A _ D [5:4] is converted into SATA signal through the protocol converter 2 and connected to the B channel of the signal channel switch 1, and the Ampere processor CPU0_ RCB0A _ D [3:0] is directly connected to the C channel of the signal channel switch 1. The a-channel of the signal channel switch 1 is connected to the m.2 connector interface, and the a-channel switch control signal SEL of the signal channel switch 1 is controlled by the m.2 connector interface signal PEDET. When the m.2 connector interface is connected to the satam.2 hard disk, the m.2 connector interface signal PEDET is at a low level, and at this time, the signal channel switcher 1A channel is connected to the B channel, and when the m.2 connector interface is connected to the NVMe m.2 hard disk, the m.2 connector interface signal PEDET is at a high level, and at this time, the a channel of the signal channel switcher 1 is connected to the C channel.

Of course, the CPU may be of various types other than the amp processor, and the embodiment of the present invention is not limited herein.

As a preferred embodiment, the signal transfer system further comprises a prompter;

the BMC 4 is also used for controlling the prompter to prompt the pre-stored basic information.

Specifically, considering that a user has a need to check the basic information of the connected hard disk under certain conditions, the BMC 4 in the embodiment of the present invention may further control the prompter to prompt the obtained pre-stored basic information, so that the user can know the related information of the connected hard disk through the prompter, and the user need is met.

The prompting device may be of various types, for example, a display, and the like, and the embodiment of the present invention is not limited herein.

The invention also provides a mainboard comprising the signal switching system.

For the introduction of the main board provided by the embodiment of the present invention, please refer to the embodiment of the signal forwarding system described above, and the embodiment of the present invention is not described herein again.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.