阅读说明：本技术 一种基于fpga的lio总线扩展uart外设系统及方法 (FPGA-based LIO bus extension UART peripheral system and method ) 是由 杨炳伟 程骥思 孙冲 樊涛 于 2020-12-21 设计创作，主要内容包括：本发明提供了一种基于FPGA的LIO总线扩展UART外设系统及方法,该系统包括龙芯2k1000模块,龙芯2k1000的LIO端口连接FPGA模块；FPGA模块包括总线协议解析单元,用于解析龙芯2K1000处理器的LIO总线协议,实现FPGA与龙芯2K1000处理器的LIO通讯功能；控制单元,用于实现FIFO的读写操作,包括读控制逻辑、写控制逻辑、读FIFO Read-FIFO、写FIFO Write-FIFO；UART单元,用于完成UART协议的发送和接收。本发明可以满足龙芯2k1000需要更多UART外设资源的场合,利用该方法可以很容易进行通用的外设扩展,具有结构简单、通用性高、实用性强等优点。(The invention provides a system and a method for extending UART peripheral equipment by LIO bus based on FPGA, the system comprises a Loongson 2k1000 module, the LIO port of the Loongson 2k1000 is connected with the FPGA module; the FPGA module comprises a bus protocol analysis unit for analyzing the LIO bus protocol of the Loongson 2K1000 processor and realizing the LIO communication function between the FPGA and the Loongson 2K1000 processor; the control unit is used for realizing the Read-Write operation of the FIFO and comprises Read control logic, Write control logic, Read FIFO Read _ FIFO and Write FIFO Write _ FIFO; and the UART unit is used for finishing the sending and receiving of the UART protocol. The method can meet the situation that the Loongson 2k1000 needs more UART peripheral resources, can easily carry out universal peripheral extension by utilizing the method, and has the advantages of simple structure, high universality, strong practicability and the like.)

1. An LIO bus extension UART peripheral system based on FPGA is characterized by comprising a Loongson 2k1000 processor, wherein an LIO port of the Loongson 2k1000 processor is connected with an FPGA module; the FPGA module comprises a bus protocol analysis unit, a control unit and a UART unit;

the bus protocol analysis unit is used for analyzing an LIO bus protocol of the Loongson 2K1000 processor and realizing an LIO communication function between the FPGA and the Loongson 2K1000 processor;

the control unit is used for realizing the Read-Write operation of the FIFO and comprises a Read control logic, a Write control logic, a Read FIFO Read _ FIFO and a Write FIFO Write _ FIFO;

the UART unit is used for completing the transmission and the reception of a UART protocol.

2. The FPGA-based LIO bus extension UART peripheral system of claim 1, wherein the bus protocol parsing unit comprises:

the address decoding module is used for realizing the analysis of the LIO bus;

the synchronous trigger unit is used for improving the time sequence of the parallel bus data;

the first multiplexer selects the data of the corresponding register to output to a data bus LIO _ D through a selection signal given by the address decoding module;

the second multiplexer sends the input data to the corresponding register through the selection signal given by the address decoding module;

a receive data register for reading and storing data from the receive FIFO;

the state register is used for storing the state of the UART module;

a Transmit data register for storing and holding data to be sent to the Transmit FIFO;

and the control register is used for configuring and saving the configuration information of the UART.

3. The FPGA-based LIO bus extended UART peripheral system of claim 1, wherein the LIO bus timing comprises an address bus LIO _ A, a data LIO _ D, a read control bus LIO _ RDn and a write control bus LIO _ WRn; and, the LIO bus works in a 16-bit read-write data state.

4. The FPGA-based LIO bus extended UART peripheral system of claim 1, wherein the data interface of the LIO bus uses a tri-state gate bus, and the control signal of the tri-state gate bus adopts the read control signal of the LIO bus.

5. The FPGA-based LIO bus extension UART peripheral system of claim 1, wherein the data bits of the receiving data register, the transmitting data register and the control register are all 16 bits and are all readable and writable.

6. The FPGA-based LIO bus extended UART peripheral system of claim 1, wherein the status register has 16 bits of data bits and is read-only.

7. The FPGA-based LIO bus extension UART peripheral system as recited in claim 1, wherein the UART unit comprises a UART module, the UART module generates interrupt information during sending or receiving, the interrupt information is transmitted to the Loongson 2k1000 processor through a status register, in addition, an interrupt trigger is generated to the Loongson 2k1000 processor through a GPIO pin intr, and the Loongson 2k1000 processor can read a corresponding register to complete data access after receiving the interrupt information.

8. A method for extending UART peripheral by LIO bus based on FPGA is characterized in that it comprises data transmitting process and data receiving process;

the data transmission process comprises the following steps:

(1) the Loongson 2k1000 configures a configuration register;

(2) the Loongson 2k1000 inquires a state register, and if the FIFO is not empty, the Loongson 2k1000 outputs data to the LIO bus;

(3) the LIO _ WR bus is pulled low, and the writing logic state is triggered to be converted into a delay state;

(4) after the delay is finished, the writing logic state jumps to the writing state, the lower 8 bits are written firstly, and then the upper 8 bits are written;

(5) when the uart tx module inquires that the FIFO is not empty, reading the data of the FIFO, serially transmitting the data to the outside, continuously reading the FIFO data if the FIFO is not empty after the data is transmitted, and waiting if the FIFO is empty;

the data receiving process comprises the following steps:

(1) the Loongson 2k1000 configures a configuration register;

(2) if the data starts to be transmitted to the Uart _ rx, the Uart writes the data of one byte into the FIFO after receiving the data;

(3) if the FIFO is not empty, an interrupt signal is sent to the Loongson 2k1000, and the Loongson 2k1000 is triggered to generate interrupt;

(4) when the Loongson 2k1000 receives the interrupt, the number of the receiving FIFO in the status register starts to be read, if the number is not 0, the data of the LIO interface is read, and if the number is 0, the data of the LIO interface is not read;

(5) when the Loongson 2k1000 reads the data of the LIO interface, the state of Sw1 is triggered to turn to the state of Sw 2;

(6) the data reading logic reads the data in the FIFO, the data is read to the lower 8 bits of the data receiving register, and then the FIFO data is read to the upper 8 bits of the data receiving register;

(7) the Loongson 2k1000 reads the received data register into the internal RAM, and the reading operation of uart data is completed.

Technical Field

The disclosure relates to the technical field of bus extension and storage control, in particular to an LIO bus extension UART peripheral system and method based on an FPGA.

Background

The LocalIO bus is called LIO bus for short, is a peripheral access interface provided by loongson 2k1000 series CPUs, and is generally used for connecting an external ROM for starting a system. The Loongson 2k1000 series CPU is taken as a domestic independently developed CPU and is generally applied to products with domestic requirements. The CPU processor has limited peripheral resources, if some special application scenes are met, more peripheral interfaces are needed, and the 2k1000 processor cannot provide more peripheral interfaces, so that peripheral interface expansion needs to be carried out on the CPU. In the prior art, only an extended DMA controller is used for the 2k1000 LIO peripheral extension, and peripheral devices such as UART, IIC, HDLC and the like are not extended.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a system and a method for extending a UART peripheral through an LIO bus based on an FPGA, where the system and the method can meet the requirement of a loongson 2k1000 on more UART peripheral resources, and the method can be used to easily perform universal peripheral extension, and has the advantages of simple structure, high versatility, strong practicability, and the like.

In order to achieve the above purpose, the invention provides the following technical scheme:

an LIO bus extension UART peripheral system based on FPGA comprises a Loongson 2k1000 processor, wherein an LIO port of the Loongson 2k1000 processor is connected with an FPGA module; the FPGA module comprises a bus protocol analysis unit, a control unit and a UART unit;

the bus protocol analysis unit is used for analyzing an LIO bus protocol of the Loongson 2K1000 processor and realizing an LIO communication function between the FPGA and the Loongson 2K1000 processor;

the control unit is used for realizing the Read-Write operation of the FIFO and comprises a Read control logic, a Write control logic, a Read FIFO Read _ FIFO and a Write FIFO Write _ FIFO;

the UART unit is used for completing the transmission and the reception of a UART protocol.

Further, the bus protocol parsing unit includes:

the address decoding module is used for realizing the analysis of the LIO bus;

the synchronous trigger unit is used for improving the time sequence of the parallel bus data;

the first multiplexer selects the data of the corresponding register to output to a data bus LIO _ D through a selection signal given by the address decoding module;

the second multiplexer sends the input data to the corresponding register through the selection signal given by the address decoding module;

a receive data register for reading and storing data from the receive FIFO;

the state register is used for storing the state of the UART module;

a Transmit data register for storing and holding data to be sent to the Transmit FIFO;

and the control register is used for configuring and saving the configuration information of the UART.

Further, the timing sequence of the LIO bus includes an address bus LIO _ a, data LIO _ D, a read control bus LIO _ RDn, and a write control bus LIO _ WRn; and, the LIO bus works in a 16-bit read-write data state.

Furthermore, the data interface of the LIO bus uses a tri-state gate bus, and the control signal of the tri-state gate bus adopts the read control signal of the LIO bus.

Furthermore, the data bit numbers of the receiving data register, the transmitting data register and the control register are all 16 bits and are all readable and writable.

Further, the number of data bits of the status register is 16 bits, and the register is read-only.

Further, the UART unit includes a UART module, the UART module generates interrupt information when transmitting or receiving, the interrupt information is transmitted to the loongson 2k1000 processor through the status register, and an interrupt trigger is generated to the loongson 2k1000 processor through a GPIO pin intr, and the loongson 2k1000 processor can read a corresponding register to complete data access by receiving the interrupt information.

The invention also provides a method for extending the UART peripheral by the LIO bus based on the FPGA, which comprises a data sending process and a data receiving process;

the data transmission process comprises the following steps:

(1) the Loongson 2k1000 configures a configuration register;

(2) the Loongson 2k1000 inquires a state register, and if the FIFO is not empty, the Loongson 2k1000 outputs data to the LIO bus;

(3) the LIO _ WR bus is pulled low, and the writing logic state is triggered to be converted into a delay state;

(4) after the delay is finished, the writing logic state jumps to the writing state, the lower 8 bits are written firstly, and then the upper 8 bits are written;

(5) when the uart tx module inquires that the FIFO is not empty, reading the data of the FIFO, serially transmitting the data to the outside, continuously reading the FIFO data if the FIFO is not empty after the data is transmitted, and waiting if the FIFO is empty;

the data receiving process comprises the following steps:

(1) the Loongson 2k1000 configures a configuration register;

(2) if the data starts to be transmitted to the Uart _ rx, the Uart writes the data of one byte into the FIFO after receiving the data;

(3) if the FIFO is not empty, an interrupt signal is sent to the Loongson 2k1000, and the Loongson 2k1000 is triggered to generate interrupt;

(4) when the Loongson 2k1000 receives the interrupt, the number of the receiving FIFO in the status register starts to be read, if the number is not 0, the data of the LIO interface is read, and if the number is 0, the data of the LIO interface is not read;

(5) when the Loongson 2k1000 reads the data of the LIO interface, the state of Sw1 is triggered to turn to the state of Sw 2;

(6) the data reading logic reads the data in the FIFO, the data is read to the lower 8 bits of the data receiving register, and then the FIFO data is read to the upper 8 bits of the data receiving register;

(7) the Loongson 2k1000 reads the received data register into the internal RAM, and the reading operation of uart data is completed.

The invention discloses a system and a method for extending UART peripheral by LIO bus based on FPGA, which has the following beneficial effects:

(1) the invention has the characteristics of clear framework, relatively simple structure and strong transportability, and is suitable for different FPGA devices;

(2) the method has strong practicability, and the uart peripheral equipment can be expanded when the number of the uart peripheral equipment of the Loongson 2k1000 cannot meet the requirement;

(3) the invention has strong stability and high safety, adopts a tri-state gate bus interface and adopts the LIO _ RD signal as a control signal of the tri-state gate, can avoid the interface level conflict of the Loongson and the FPGA, and ensures that the circuit has the characteristics of strong stability and high safety.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic block diagram of an LIO bus extended UART according to an embodiment of the present invention;

FIG. 2 is a timing diagram of LIO according to an embodiment of the present invention;

FIG. 3 is a state transition diagram of read control logic in an embodiment of the present invention;

FIG. 4 is a state transition diagram of write control logic in an embodiment of the present invention.

Detailed Description

The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

The embodiments of the present disclosure are described below with specific examples, and other advantages and effects of the present disclosure will be readily apparent to those skilled in the art from the disclosure in the specification. It is to be understood that the described embodiments are merely illustrative of some, and not restrictive, of the embodiments of the disclosure. The disclosure may be embodied or carried out in various other specific embodiments, and various modifications and changes may be made in the details within the description without departing from the spirit of the disclosure. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It is noted that various aspects of the embodiments are described below within the scope of the appended claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the disclosure, one skilled in the art should appreciate that one aspect described herein may be implemented independently of any other aspects and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. Additionally, such an apparatus may be implemented and/or such a method may be practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.

It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present disclosure, and the drawings only show the components related to the present disclosure rather than the number, shape and size of the components in actual implementation, and the type, amount and ratio of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.

The embodiment of the disclosure provides a system and a method for extending UART peripheral by an LIO bus based on an FPGA.

The system is shown in a schematic block diagram in fig. 1 and comprises a Loongson 2K1000 and an FPGA module. The LIO bus is originally a bus interface of the loongson 2k1000 expansion external memory, and is here extended to be a universal peripheral interface UART, so that a user-defined peripheral UART can be operated by operating a space corresponding to the LIO peripheral. The functional block diagram module of the designed FPGA is shown in a dotted line frame of fig. 1, and includes a bus protocol parsing unit, a control unit, and a UART unit.

(1) Bus protocol analysis unit

The bus protocol analysis unit is used for analyzing the LIO bus protocol of the Loongson 2K1000 and realizing the LIO communication function of the FPGA and the Loongson 2K 1000. As shown in fig. 1, it includes an address decoding module, a tri-state gate bus, a synchronous trigger unit, a first multiplexer, a second multiplexer, a receiving data register, a status register, a transmitting data register and a control register. The timing sequence of the LIO bus is shown in fig. 2, and mainly includes an address bus LIO _ a, data LIO _ D, a read control bus LIO _ RDn, and a write control bus LIO _ WRn.

The LIO bus works in a 16-bit read-write data state;

the address decoding module realizes the analysis of the LIO bus, and the data bus of the address decoding module needs to be set as a bidirectional interface because the data bus needs to meet the switching of input and output, and in addition, a tri-state gate needs to be used at the data bus interface in order to prevent the 2k1000 from colliding with the FPGA.

The control signal of the tri-state gate adopts a read control signal of an LIO bus, so that the read-write signal of the LIO is effective at a low level, and when the Loongson 2k1000 performs write-in operation on the FPGA, a data bus interface of the FPGA is externally high-resistance, so that the read control signal bus is designed to meet the requirement. The address decoder translates the address on the LIO _ a into a corresponding selection signal, the selection signal is used for selecting a corresponding register, and the LIO _ a data bit width is 16 bits.

The data bit width of the LIO _ A is 7 bits, the Loongson carries out data on 32-bit address space when the LIO is operated, and the 32-bit address has a certain corresponding relation with an address obtained on the LIO _ A;

the synchronous trigger module is used for improving the time sequence of the parallel bus data, and is generally triggered by 2 beats;

the first multiplexer selects the data of the corresponding register to output to the data bus LIO _ D through the selection signal given by the address decoding module;

the second multiplexer sends the input data to the corresponding register through the selection signal given by the address decoding module;

the receiving data register is used for reading and storing data in the receiving FIFO, the number of data bits is 16, and the register is readable and writable;

the state register is used for storing the state of the UART module, the data bit number of the state register is 16 bits, and the register is read-only;

the transmission data register is used for storing and saving data to be sent to the transmission FIFO, the number of data bits is 16, and the register is readable and writable;

the control register is used for configuring and storing configuration information of the UART, wherein the configuration information comprises baud rate, parity check and the like, the number of data bits is 16, and the register is readable and writable.

(2) Control unit

Since the LIO bus is an asynchronous bus, if the LIO bus is to be converted into a bus inside the FPGA, the timing is optimized by the previously used flip-flop synchronization unit, and data needs to be converted into a local clock domain of the FPGA through the FIFO. The control unit mainly realizes the reading and writing operation of the FIFO and comprises reading control logic, writing control logic, reading FIFO Read _ FIFO and writing FIFO Write _ FIFO.

The read-write FIFO is 8bit wide and 512 depth;

the state flow diagram of the read control logic is shown in fig. 3, which is described as follows;

sr 1: the idle state is a default state of the system, if the falling edge of the read signal is effective, the state jumps to Sr2, otherwise, the state is kept in the current state;

sr 2: in the delayed state, the godson generates a plurality of clocks after the read state is valid when data is fetched, so that delay is needed, and the godson enters the Sr3 state after the delay;

sr 3: reading low 8-bit data and entering the Sr4 state;

sr 4: reading high 8-bit data and entering the Sr5 state;

sr 5: the end state jumps to Sr 1.

The state flow diagram of the write control logic is shown in fig. 4, which is described as follows:

sw 1: the idle state is the default state of the system, if the falling edge of the writing signal is effective, the state jumps to Sr2, otherwise, the state is kept in the current state;

sw 2: in the delayed state, the Loongson generates a plurality of clocks after the read state is effective when writing data, so that delay is needed, and the Loongson enters the Sr3 state after the delay;

sw 3: writing lower 8 bits of data and entering the Sr4 state;

sw 4: writing high 8 bits of data, and entering the Sr5 state;

sw 5: the end state jumps to Sr 1.

(3) UART unit

The UART unit is used for finishing the sending and receiving of a UART protocol, and the control register configures the UART _ tx module and the UART _ rx module and configures the UART _ tx module and the UART _ rx module to work in a specific baud rate and parity check state; the UART module generates interrupt information during sending or receiving, the information is transmitted to the Loongson 2k1000 through the state register, in addition, interrupt triggering is generated to the Loongson 2k1000 through one GPIO pin intr, and the Loongson can read the corresponding register to finish data access by receiving the interrupt signal. The status register also includes information such as the depth size of the FIFO.

Next, the method of the present invention will be described by way of specific examples.

Since the LIO port of the loongson 2k1000 is in a multiplexing state, corresponding pins are required to be configured on the loongson 2k1000 to work in the LIO state, and the LIO peripheral is configured as a 16-bit data bus.

The method comprises a data sending process and a data receiving process;

the data transmission process comprises the following steps:

(1) the Loongson 2k1000 configures a configuration register;

(2) the Loongson 2k1000 inquires a state register, and if the FIFO is not empty, the Loongson 2k1000 outputs data to the LIO bus;

(3) the LIO _ WR bus is pulled low, and the writing logic state is triggered to be converted into a delay state;

(4) after the delay is finished, the writing logic state jumps to the writing state, the lower 8 bits are written firstly, and then the upper 8 bits are written;

(5) when the uart tx module inquires that the FIFO is not empty, reading the data of the FIFO, serially transmitting the data to the outside, continuously reading the FIFO data if the FIFO is not empty after the data is transmitted, and waiting if the FIFO is empty;

the data receiving process comprises the following steps:

(1) the Loongson 2k1000 configures a configuration register;

(2) if the data starts to be transmitted to the Uart _ rx, the Uart writes the data of one byte into the FIFO after receiving the data;

(3) if the FIFO is not empty, an interrupt signal is sent to the Loongson 2k1000, and the Loongson 2k1000 is triggered to generate interrupt;

(4) when the Loongson 2k1000 receives the interrupt, the number of the receiving FIFO in the status register starts to be read, if the number is not 0, the data of the LIO interface is read, and if the number is 0, the data of the LIO interface is not read;

(5) when the Loongson 2k1000 reads the data of the LIO interface, the state of Sw1 is triggered to turn to the state of Sw 2;

(6) the data reading logic reads the data in the FIFO, the data is read to the lower 8 bits of the data receiving register, and then the FIFO data is read to the upper 8 bits of the data receiving register;

(7) the Loongson 2k1000 reads the received data register into the internal RAM, and the reading operation of uart data is completed.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present disclosure should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.