阅读说明：本技术 一种高频双极晶体管制备方法 (Preparation method of high-frequency bipolar transistor ) 是由 张新欣 于 2020-12-11 设计创作，主要内容包括：本发明的一种高频双极晶体管制备方法涉及一种带有外置基区结构的双极晶体管制造方法,目的是为了克服在现有的双极晶体管结构基础上降低器件Vcesat时,影响器件BVCBO的问题,方法如下：制成重掺杂N型阱区,该重掺杂N型阱区贯穿N型外延层,且底部插入N型埋层；使用光刻胶将表面浅槽处的重掺杂N型阱区覆盖,再通过光刻胶和氧化硅阻挡,在重掺杂N阱的两侧做P+外基区的倾斜注入,且使重掺杂N阱与P+外基区达到电荷平衡；对基区进行快速热退火,使得多晶硅-1内的P型杂质进入到N型外延层,形成P型的基区接触区,基区接触区与P+外基区连接；并且,基区接触区的浓度要大于P+外基区的浓度。(The invention discloses a preparation method of a high-frequency bipolar transistor, relates to a manufacturing method of a bipolar transistor with an external base region structure, and aims to solve the problem that when a device Vcesat is reduced on the basis of the existing bipolar transistor structure, the BVCBO of the device is influenced, wherein the method comprises the following steps: manufacturing a heavily doped N-type well region, wherein the heavily doped N-type well region penetrates through the N-type epitaxial layer, and the bottom of the heavily doped N-type well region is inserted into the N-type buried layer; covering a heavily doped N-type well region at the shallow groove on the surface by using photoresist, and performing inclined injection of a P + outer base region on two sides of the heavily doped N-type well through the photoresist and silicon oxide barrier, so that the heavily doped N-type well and the P + outer base region reach charge balance; carrying out rapid thermal annealing on the base region to enable P-type impurities in the polycrystalline silicon-1 to enter the N-type epitaxial layer to form a P-type base region contact region, wherein the base region contact region is connected with the P + outer base region; and the concentration of the base contact region is greater than that of the P + outer base region.)

1. A preparation method of a high-frequency bipolar transistor is characterized by comprising the following specific steps:

manufacturing an isolation groove, an N-type buried layer, an N-type epitaxial layer and a deep N well on a P substrate;

secondly, manufacturing a heavily doped N-type well region, wherein the heavily doped N-type well region penetrates through the N-type epitaxial layer, and the bottom of the heavily doped N-type well region is inserted into the N-type buried layer;

step three, manufacturing an active region on the upper surface of the N-type epitaxial layer;

step four, depositing polycrystalline silicon-1 and surface silicon oxide on the upper surfaces of the N-type epitaxial layer and the active region from bottom to top in sequence;

step five, photoetching and etching the surface silicon oxide and the polycrystalline silicon-1, removing part of the surface silicon oxide and the polycrystalline silicon-1, and exposing the part of the upper surface of the active region and the part of the upper surface of the N-type epitaxial layer; and the upper surface of the heavily doped N-type well region is positioned in the partial upper surface of the N-type epitaxial layer;

sixthly, performing self-aligned groove etching on the N-type epitaxial layer through silicon oxide barrier to form a surface shallow groove, wherein the depth of the surface shallow groove is the same as that of the transistor base region;

step seven, covering the heavily doped N-type well region at the shallow groove on the surface by using photoresist, and performing inclined injection of a P + outer base region on two sides of the heavily doped N-type well by using the photoresist and silicon oxide barrier, so that the heavily doped N-type well and the P + outer base region reach charge balance;

step eight, performing rapid thermal annealing on the base region to enable P-type impurities in the polycrystalline silicon-1 to enter the N-type epitaxial layer to form a P-type base region contact region, wherein the base region contact region is connected with the P + outer base region; moreover, the concentration of the base region contact region is greater than that of the P + outer base region;

filling the surface shallow groove with the P-type lightly doped epitaxy, and performing epitaxial layer back etching on the P-type lightly doped epitaxy to form a P-base region;

and step ten, manufacturing the isolation side wall, the polycrystalline silicon emitter, the metal electrode and the like to finish the preparation of the transistor.

2. The method as claimed in claim 1, wherein the heavily doped N-type well region has a doping concentration of 1E15/cm³～3E15/cm³。

3. The method according to claim 2, wherein the implanted ions of the polysilicon-1 are B, the implantation energy is 30-80KeV, and the implantation dose is 2E15/cm³～4E15/cm³A thickness of

4. A method for forming a high frequency bipolar transistor according to claim 3, wherein the surface silicon oxide has a thickness of

5. The method as claimed in claim 4, wherein the shallow grooves have a depth of

6. A method for forming a high-frequency bipolar transistor according to claim 5, wherein the implanted ions of the P + extrinsic base region are BF₂The implantation energy is 20-40KeV, and the implantation dosage of the P + outer base region is half of that of the heavily doped N well.

7. A method for manufacturing a high-frequency bipolar transistor according to claim 5, wherein the base region is subjected to rapid thermal annealing at 950 to 1050 ℃ for 20 to 30 min.

Technical Field

The invention relates to a manufacturing method of a transistor, in particular to a manufacturing method of a bipolar transistor with an external base region structure.

Background

Since the point contact transistor invented in 1948, the transistor was originally developed in the 50 s into a junction transistor, now called a bipolar transistor. Bipolar transistors have two basic structures: PNP type and NPN type. In the 3-layer semiconductor, the middle layer is called a base region, and the outer two layers are called an emitter region and a collector region respectively. When a small amount of current is injected into the base region, a large current flows between the emitter region and the collector region, which is an amplification effect of the transistor.

And in bipolar transistors, both electrons and holes participate in conduction. Compared with a field effect transistor, the bipolar transistor has the advantages of low switching speed, low input impedance and high power consumption. The single-double pole transistor has small volume, light weight, low power consumption, long service life and high reliability, is widely used in the fields of broadcasting, television, communication, radar, computer, automatic control device, electronic instrument, household appliance and the like, and plays roles of amplification, oscillation, switching and the like.

However, as shown in fig. 1 to 8, in the conventional bipolar transistor structure, electrons must pass through the entire N-type epitaxial layer in the vertical direction after diffusing through the base region, and then are collected by the N-type buried layer and then by the collector through the N-well.

In practice, to maintain a high device BVCBO (collector junction breakdown voltage), the N-type epitaxial layer concentration must be made relatively thin, which results in a high resistance in the electron motion path of the N-type epitaxial layer and a high device Vcesat (base-emitter voltage drop at saturation). However, if the device's Vcesat is to be reduced, the resistivity of the N-type epitaxial layer must be reduced, which in turn affects the BVCBO of the device.

Disclosure of Invention

The invention aims to solve the problem that when the Vcesat of a device is reduced on the basis of the structure of the existing bipolar transistor, the BVCBO of the device is influenced, and provides a preparation method of a high-frequency bipolar transistor.

The invention relates to a preparation method of a high-frequency bipolar transistor, which comprises the following specific steps:

manufacturing an isolation groove, an N-type buried layer, an N-type epitaxial layer and a deep N well on a P substrate;

secondly, manufacturing a heavily doped N-type well region, wherein the heavily doped N-type well region penetrates through the N-type epitaxial layer, and the bottom of the heavily doped N-type well region is inserted into the N-type buried layer;

step three, manufacturing an active region on the upper surface of the N-type epitaxial layer;

step four, depositing polycrystalline silicon-1 and surface silicon oxide on the upper surfaces of the N-type epitaxial layer and the active region from bottom to top in sequence;

step five, photoetching and etching the surface silicon oxide and the polycrystalline silicon-1, removing part of the surface silicon oxide and the polycrystalline silicon-1, and exposing the part of the upper surface of the active region and the part of the upper surface of the N-type epitaxial layer; and the upper surface of the heavily doped N-type well region is positioned in the partial upper surface of the N-type epitaxial layer;

step six, self-aligned groove etching is carried out on the N-type epitaxial layer through silicon oxide blocking to form a surface shallow groove, and the depth of the surface shallow groove is the same as that of the transistor base region;

step seven, covering the heavily doped N-type well region at the shallow groove on the surface by using photoresist, blocking by using the photoresist and silicon oxide, and performing inclined injection of a P + outer base region on two sides of the heavily doped N-type well so as to balance the charges of the heavily doped N-type well and the P + outer base region;

step eight, performing rapid thermal annealing on the base region to enable P-type impurities in the polycrystalline silicon-1 to enter the N-type epitaxial layer to form a P-type base region contact region, wherein the base region contact region is connected with the P + outer base region; moreover, the concentration of the base region contact region is greater than that of the P + outer base region;

filling the surface shallow groove with the P-type lightly doped epitaxy, and performing epitaxial layer back etching on the P-type lightly doped epitaxy to form a P-base region;

and step ten, manufacturing the isolation side wall, the polycrystalline silicon emitter, the metal electrode and the like to finish the preparation of the transistor.

Further, the doping concentration of the heavily doped N-type well region is 1E15/cm³～3E15/cm³。

Furthermore, the implanted ions of the polysilicon-1 are B, the implantation energy is 30-80KeV, and the implantation dosage is 2E15/cm³～4E15/cm³A thickness of

Further, the surface silica has a thickness of

Further, the depth of the shallow surface grooveIs composed of

Further, the implanted ions of the P + outer base region are BF₂The implantation energy is 20-40KeV, and the implantation dosage of the P + outer base region is half of that of the heavily doped N well.

Further, the temperature for carrying out rapid thermal annealing on the base region is 950-1050 ℃, and the time is 20-30 min.

The invention has the beneficial effects that:

the preparation method of the high-frequency bipolar transistor has the advantages of simple process flow, compatibility with the existing process and easiness in implementation;

after electrons penetrate through the base region through diffusion, the electrons are immediately collected by the heavily doped N-well, and the resistivity of the heavily doped N-well is very low, so that the resistance of an electron motion path is greatly reduced, and the Vcesat of a device is greatly reduced;

meanwhile, P + outer base regions are arranged on two sides of the heavily doped N well, when the collector-base electrode is reversely biased, the outer base regions can be completely depleted with the heavily doped N well, the P-base regions are protected through the formed depleted high-resistance layer, reverse bias voltage of the collector is borne, and therefore voltage resistance between the collector and the base electrode is improved.

Namely, Vcesat of the device is reduced on the premise of ensuring the BVCBO of the device.

Drawings

Fig. 1 is a schematic diagram of step 1 of a conventional bipolar transistor main formation process;

fig. 2 is a schematic diagram of step 2 of a conventional bipolar transistor main formation process;

fig. 3 is a schematic diagram of step 3 of a conventional bipolar transistor main formation process;

fig. 4 is a schematic diagram of step 4 of a conventional bipolar transistor main formation process;

fig. 5 is a schematic diagram of step 5 of a conventional bipolar transistor main formation process;

fig. 6 is a schematic diagram of step 6 of a conventional bipolar transistor main formation process;

fig. 7 is a schematic diagram of step 7 of a conventional bipolar transistor main formation process;

fig. 8 is a schematic diagram of step 8 of a conventional bipolar transistor main formation process;

wherein, the reference numbers in fig. 1 to 8 are: 1-silicon oxide, 2-photoresist, 3-polysilicon-1, 4-base junction and 5-emitter polycrystal; c-collector, b-base, e-emitter;

fig. 9 is a schematic diagram of a first step in a method for manufacturing a high-frequency bipolar transistor according to a first embodiment;

fig. 10 is a schematic diagram illustrating a second step in the method for manufacturing a high-frequency bipolar transistor according to the first embodiment;

fig. 11 is a schematic view of a third step in the manufacturing method of the high-frequency bipolar transistor according to the first embodiment;

fig. 12 is a schematic diagram illustrating a fourth step in the method for manufacturing a high-frequency bipolar transistor according to the first embodiment;

fig. 13 is a schematic view of a fifth step in the manufacturing method of the high-frequency bipolar transistor according to the first embodiment;

fig. 14 is a schematic view of a sixth step in the manufacturing method of the high-frequency bipolar transistor according to the first embodiment;

fig. 15 is a schematic diagram illustrating a seventh step in the manufacturing method of the high-frequency bipolar transistor according to the first embodiment;

fig. 16 is a schematic diagram illustrating a step eight in the method for manufacturing a high-frequency bipolar transistor according to the first embodiment;

fig. 17 is a schematic diagram illustrating a ninth step in the method for manufacturing a high-frequency bipolar transistor according to the first embodiment;

fig. 18 is a schematic view of a tenth step in the manufacturing method of the high-frequency bipolar transistor according to the first embodiment;

fig. 19 is a schematic diagram of step eleven in a manufacturing method of a high-frequency bipolar transistor according to the first embodiment.

Detailed Description

In a first embodiment, a conventional bipolar transistor is mainly formed as follows:

step 1, as shown in fig. 1, the N-type buried layer, the N-type epitaxy and the trench isolation are completed according to the conventional process. Wherein the trench may be filled with oxide, oxide + polysilicon, etc. Is not particularly limited;

step 2, as shown in fig. 2, completing the manufacture of the N well and the active region according to the traditional process;

step 3, as shown in FIG. 3, performing polysilicon-1 deposition and polysilicon P-type implantation;

step 4, as shown in fig. 4, a layer of silicon dioxide is redeposited. And completing the multi-crystal layer photoetching;

step 5, as shown in fig. 5, respectively completing the etching of the silicon oxide and the polysilicon, and completing the photoresist removal;

and 6, as shown in FIG. 6, base region injection and high-temperature diffusion are carried out. Forming a shallow base region junction;

step 7, as shown in fig. 7, completing side wall isolation and forming emitter polycrystal;

and 8, finishing the device medium isolation and the metal lead as shown in fig. 8, and finishing the preparation of the conventional bipolar transistor.

In the method for manufacturing a high-frequency bipolar transistor in this embodiment, the problems of the conventional bipolar transistor are solved. The device BVCBO is ensured, meanwhile, Vcesat of the device is effectively reduced, and the performance of the device is greatly improved.

Step one, as shown in fig. 9, the trench isolation, the N-type buried layer, the N-type epitaxial layer and the deep N well of the device are completed according to the conventional process;

step two, as shown in fig. 10, a heavily doped N-type well region is formed in the N-type epitaxial layer by post-lithography implantation and post-implantation drive-in. Besides the injection mode after photoetching, the heavily doped N-type well region can also be formed by filling the N-type epitaxy after groove etching. And is not particularly limited. The doping concentration of the heavily doped N-type well region is usually 1E15/cm³-3E15/cm³To (c) to (d);

step three, as shown in fig. 11, forming an active region of the device by processes such as photolithography, etching, oxidation, and the like according to a conventional process, and defining the position of the device without any special limitation;

step four, as shown in FIG. 12, a layer of polysilicon-1 is deposited with a thickness of usually 2000-3000 angstroms, and the P-type implantation of the polysilicon-1 is completed under the same implantation conditions as those of the background art, usually the implanted ions are B, the implantation energy is 30-80KeV, and the implantation dose is usually 2E15/cm³-4E15/cm³To (c) to (d); and depositing a layer of silicon oxide on the surface of the polysilicon-1 after the implantation. The silicon oxide thickness is typically between 2500-;

and step five, as shown in FIG. 13, performing photolithography and etching on the polysilicon-1. Part of the silicon oxide and the polysilicon-1 are removed.

And step six, as shown in fig. 14, performing self-aligned trench etching on the N-type epitaxial layer under the surface silicon oxide barrier. Forming a shallow groove on the surface, wherein the depth of the groove is the same as that of the base region of the device, and is usually between 7000-;

and seventhly, as shown in FIG. 15, photoetching is carried out on the P + outer base region. Protecting the heavily doped N well;

and step eight, as shown in fig. 16, performing inclined implantation of the P + outer base region under the barrier of the photoresist and the surface silicon oxide. Implanting ions to BF₂The implantation energy is 20-40 KeV. The injection dosage refers to the dosage of the heavily doped N well, and finally the heavily doped N well and the P + outer base regions on the two sides can reach charge balance. The typical injection dosage of the P + outer base region is half of that of the heavily doped N well;

and step nine, as shown in fig. 17, performing rapid thermal annealing on the base region. The annealing temperature is typically 950-. Through rapid thermal annealing, P-type impurities in the polysilicon-1 can enter the N-type epitaxial layer to form a P-type base region contact region and are connected with the outer base region;

because the concentration of the base region contact region is greater than that of the P + outer base region, the P + outer base region injected from the side face can be covered after P-type impurities enter the epitaxial layer from the polycrystalline silicon-1. Forming P + outer base regions only on two sides of the heavily doped N well;

step ten, as shown in fig. 18, filling the P-type lightly doped epitaxy in the trench, and completing the back etching of the epitaxy. Realizing surface planarization; forming a P-base region;

step eleven, as shown in fig. 19, according to the conventional process, the manufacturing of the side wall isolation, the polysilicon emitter, the metal electrode and the like is formed.

By adopting the scheme, electrons penetrate through the base region through diffusion and are immediately collected by the heavily doped N-well, and the resistivity of the heavily doped N-well is very low, so that the resistance of an electron motion path is greatly reduced, and the Vcesat of a device is greatly reduced. Meanwhile, P + outer base regions are arranged on two sides of the heavily doped N well, when the collector-base electrode is reversely biased, the outer base regions can be completely depleted with the heavily doped N well, the P-base regions are protected through the formed depleted high-resistance layer, reverse bias voltage of a collector is borne, and therefore voltage resistance between the collector and the base electrode is improved. Namely, on the premise of ensuring the BVCBO of the device, Vcesat of the device is reduced. Meanwhile, the process flow is simple, and the method is compatible with the existing process and easy to implement.