阅读说明：本技术 基于分子级网表的三模冗余方法 (Triple modular redundancy method based on molecular-level netlist ) 是由 杨海钢 于 2020-12-28 设计创作，主要内容包括：本公开提供一种基于分子级网表的三模冗余方法,包括：操作S1：将FPGA中的冗余的分子级模块进行复制得到三份该分子级模块；操作S2：将所述三份分子级模块连接至多数表决器形成表决单元,输出第一表决结果；操作S3：将所述第一表决结果输入至后接的非冗余单元后,再连接至后续的表决单元继续进行表决,进而以汇聚的方式处理路径上不需要冗余的模块,完成基于分子级网表的三模冗余。(The invention provides a triple modular redundancy method based on a molecular netlist, which comprises the following steps: operation S1: copying redundant molecular modules in the FPGA to obtain three parts of the molecular modules; operation S2: connecting the three molecular modules to a majority voter to form a voting unit and outputting a first voting result; operation S3: and inputting the first voting result to a subsequent non-redundant unit, then connecting to a subsequent voting unit for continuous voting, and further processing modules which do not need redundancy on the path in a convergence manner to complete the triple modular redundancy based on the molecular netlist.)

1. A triple modular redundancy method based on a molecular-level netlist comprises the following steps:

operation S1: copying redundant molecular modules in the FPGA to obtain three parts of the molecular modules;

operation S2: connecting the three molecular modules to a majority voter to form a voting unit and outputting a first voting result;

operation S3: and inputting the first voting result to a subsequent non-redundant unit, then connecting to a subsequent voting unit for continuous voting, and further processing modules which do not need redundancy on the path in a convergence manner to complete the triple modular redundancy based on the molecular netlist.

2. The method for triple modular redundancy based on molecular-level netlist as claimed in claim 1, wherein the three inputs of the molecular-level module are homologous.

3. The method of claim 1 for triple modular redundancy based on a molecular level netlist, said netlist having a format of vqm.

4. The molecular-level netlist-based triple modular redundancy method of claim 1, the molecular-level module comprising: a lcell module or a slice module.

5. The method of triple modular redundancy based on molecular level netlist as claimed in claim 1, the operation S2 further comprising: and judging whether the molecular level module is a cascade module.

6. The molecular level netlist based triple modular redundancy method of claim 1, wherein the non-redundant cells are sequential devices.

7. The method of triple modular redundancy based on molecular-level netlist as claimed in claim 6, said fee redundancy cells comprising dff cells.

8. The method of claim 3, wherein the netlist of the majority voter is of the form:

Technical Field

The present disclosure relates to the Field of FPGA (Field Programmable Gate Array), and in particular, to a triple modular redundancy method based on a molecular level netlist.

Background

With the continuous improvement of the degree of informatization, the application of a Field Programmable Gate Array (FPGA) is more and more extensive, and particularly, the FPGA is widely applied in the Field of aviation. The FPGA has the advantages of large integration scale, low power consumption and high concurrency. The FPGA is mainly divided into three types, namely SRAM type, FLASH type and antifuse type according to different processes. The SRAM has the advantages of simple process, low cost, low power consumption, erasability and the like, and is most widely applied.

When an SRAM (Static Random-Access Memory) type FPGA (field programmable gate array) is applied to an aerospace device as a core device, high-energy particle rays in the space easily interfere with the SRAM, and a Single Event Effect (SEE) is generated, so that no content stored in the SRAM fails. In recent years, with the continuous improvement of the process technology of the FPGA, the FPGA strides over 28nm and advances to 10 nm; the performance is improved, and meanwhile, the reliability problem caused by the single event effect in the space is more obvious.

Therefore, how to solve the reliability problem caused by the single event effect is an urgent issue to be solved.

Disclosure of Invention

Technical problem to be solved

Based on the problems, the invention provides a triple modular redundancy method based on a molecular netlist, so as to relieve the technical problems that reliability of an FPGA in a space is reduced due to a single event effect in the prior art.

(II) technical scheme

The invention provides a triple modular redundancy method based on a molecular netlist, which comprises the following steps:

operation S1: copying redundant molecular modules in the FPGA to obtain three parts of the molecular modules;

operation S2: connecting the three molecular modules to a majority voter to form a voting unit and outputting a first voting result;

operation S3: and inputting the first voting result to a subsequent non-redundant unit, then connecting to a subsequent voting unit for continuous voting, and further processing modules which do not need redundancy on the path in a convergence manner to complete the triple modular redundancy based on the molecular netlist.

In the disclosed embodiment, the three inputs of the molecular-scale module are homologous.

In the disclosed embodiment, the format of the netlist is vqm format.

In an embodiment of the present disclosure, the molecular-scale module includes: a lcell module or a slice module.

In an embodiment of the present disclosure, the operation S2 further includes: and judging whether the molecular level module is a cascade module.

In an embodiment of the present disclosure, the non-redundant cell is a sequential device.

In an embodiment of the present disclosure, the fee redundancy unit includes a dff unit.

In an embodiment of the present disclosure, the netlist of the majority voter is of the form:

(III) advantageous effects

According to the technical scheme, the triple modular redundancy method based on the molecular-level netlist has at least one or part of the following beneficial effects:

(1) the user does not need to carry out redundancy design on the design, the original design is synthesized, and the synthesized netlist file is processed by the tool disclosed by the invention to realize redundancy processing.

(2) The redundancy scheme disclosed by the invention is software redundancy, and compared with hardware redundancy, the redundancy scheme is low in cost and easy to implement.

(3) The redundancy scheme of the present disclosure is to carry out redundancy design on part of molecular level units in the FPGA; the redundant netlist file has certain advantages in area and power consumption compared with a gate-level redundancy scheme.

(4) After redundancy processing is carried out on the basis of the molecular netlist, the equivalence verification of the netlist can be carried out by performing gate-level simulation by using simulation tools such as modelSim and the like, and the verification is convenient.

Drawings

Fig. 1 is a schematic diagram of a triple modular redundancy structure in the prior art.

FIG. 2 is a truth table and implementation of a majority voter in a triple modular redundancy scheme.

Fig. 3 is a schematic diagram of the structure of the FPGA.

Fig. 4 is a TMR flow based on vqm in the triple modular redundancy method based on a molecular level netlist according to an embodiment of the present disclosure.

Fig. 5 is a schematic diagram of a TMR flow for an icell in a triple modular redundancy method based on a molecular-level netlist according to an embodiment of the present disclosure.

Fig. 6 is a schematic flow chart of TMR aggregation in the triple modular redundancy method based on a molecular level netlist according to an embodiment of the present disclosure.

FIG. 7 is a schematic structural diagram of a voter in the triple modular redundancy method based on a molecular-level netlist according to an embodiment of the present disclosure.

Detailed Description

The invention provides a Triple modular Redundancy method based on a molecular-level netlist, which takes a netlist file after user design synthesis as output to carry out the Triple Modular Redundancy (TMR), effectively controls the resource consumption and ensures the reliability of a device.

In the process of realizing the present disclosure, the inventor finds that the single event upset protection technology of the FPGA can be divided into hardware protection and software protection.

Hardware protection refers to increasing fault tolerance of a system through hardware design, and main technologies include cyclic power-up, static refresh, dynamic refresh (configuration management) and device redundancy. The hardware protection has high reliability, but high cost, and is suitable for the working condition with high probability of SEU (Single Event Upset). The circular power-on is a simple refreshing measure, the FPGA is powered on at regular time, and the whole content in the device is refreshed, and the method can be considered in a low-radiation environment. The method for correcting the overturn of the configuration area by means of reloading is called refreshing. The refresh is divided into static refresh and dynamic refresh. Static refresh means to reload all contents of the configuration area under the condition that the device is not powered down, so as to correct errors. The static refreshing can cause the interruption of the device work and the loss of the pre-point working parameters; the dynamic refreshing is also called configuration management, which means that the content of the device configuration area is subjected to targeted analysis, analysis and blocking operation, and is combined with the design, so that the work of the device is not influenced in the refreshing process. Configuration management may be done by radiation-resistant FPGAs, CPUs, ASICs (Application Specific Integrated circuits), or the FPGA design itself. The method that is completed by adopting the radiation-resistant FPGA, the CPU and the ASIC is also called External refresh (External Scrub). The method for realizing refreshing by the device designed by the FPGA is called Self-refreshing (Self Scrub). According to the experimental condition of NASA, the effect of external refresh is obviously superior to that of self refresh. Device redundancy is the implementation of configuration management and design across multiple FPGAs, and the final output is determined by comparing the outputs. There are many implementation schemes for redundant devices, and it is common to use two FPGAs to implement two-modulus redundancy or three FPGAs to implement three-modulus redundancy. For the implementation scheme of two FPGAs, each FPGA has two backups of the same design, and an additional radiation-resistant device is used for output judgment. If one of the outputs is different from the other three, then the arbiter ignores all of the outputs of the FPGA until its outputs are again consistent with the other FPGAs. And if the output data of any one of the other three FPGAs is inconsistent, ignoring the result and resetting the FPGA. For the implementation scheme of the three FPGAs, the design of each FPGA is the same, and output judgment is carried out through one anti-radiation FPGA. In order to solve the problem of single event upset, device redundancy is the best scheme at present, but the defects of high cost, difficulty in synchronizing a plurality of FPGAs and the like exist.

Software protection mainly refers to triple modular redundancy, three sensitive circuits to be protected are copied in an FPGA device according to the principle shown in figure 1, and a majority voter is added to an output part to take the majority output in the three same circuits as the output of a final circuit, so that the protection of circuit logic is realized. The majority voter is used for taking two or more than two identical signals in the output of the three replica modules as the final output of the circuit. Here we mark the output signals of the three replica modules as A, B, C, respectively, and the final output of the circuit as OUT, then OUT is AB + BC + AC. Wherein the voter and truth table are shown in fig. 2.

If soft errors occur in different configuration bits, the TMR can correct n soft errors in each n-bit word, the TMR circuit only has the influence on delay due to the addition of a majority voter which is not influenced by the number of protection bits, so the circuit performance is basically not influenced, but 3 times of storage units are required, additional logic is required for the majority voter, and therefore more than 3 times of area overhead is often caused. Research shows that the area overhead of TMR is more than 350% of the original circuit, and at the same time, more than 200% of power consumption is generated, and the wiring speed is reduced by about 30% due to the extra increased wiring resources such as a voter. The huge overhead limits the application of TMR technology in large-scale FPGA design.

Triple modular redundancy is performed on the design, and the influence of SEU can be obviously reduced. The triple modular redundancy has low cost and flexible implementation mode, but the design power consumption after redundancy is increased, and the performance has certain influence. When the triple modular redundancy design is carried out, the problems of feasibility of layout and wiring, signal integrity, asynchronous design and the like need to be considered, and if the performance after the triple modular redundancy does not reach the standard, the original design needs to be optimized.

Hardware protection and software protection have advantages and disadvantages respectively, and a user needs to select proper protection measures according to different application scenes, so that the optimal effect and cost control can be achieved. For example, in the prior art, a selection table of protective measures under different working conditions has been given as follows:

TABLE 1

The FPGA internal unit can be divided into different levels according to different granularities, and the granularities are sequentially from small to large: atom (Atom) level, Molecule (Molecule) level, Cluster (Cluster) level.

As shown in fig. 3, the atomic level is mainly basic units such as LUT, DFF, etc.; the molecular scale consists of the atomic scale such as alm; the cluster level is then composed of the molecular level such as clb. TMR for different levels is different in performance, power consumption, reliability. When the granularity is smaller, more resources are consumed, the power consumption is larger, and the difficulty of layout and wiring is larger. TMR resource consumption at the atomic level is the largest.

In order to solve the problems, the method based on the molecular level is provided, the netlist file after user design synthesis is used as output, the molecular level TMR is carried out, resource consumption is effectively controlled, and meanwhile the reliability of the device is guaranteed.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

In an embodiment of the present disclosure, a triple modular redundancy method based on a molecular-level netlist is provided, which is shown in fig. 1 to 7, and includes:

operation S1: copying redundant molecular modules in the FPGA to obtain three parts of the molecular modules;

operation S2: connecting the three molecular modules to a majority voter to form a voting unit and outputting a first voting result;

operation S3: and inputting the first voting result to a subsequent non-redundant unit, then connecting to a subsequent voting unit for continuous voting, and further processing modules which do not need redundancy on the path in a convergence manner to complete the triple modular redundancy based on the molecular netlist.

Wherein, the three parts of the molecular-level modules are input with the same source; as input to the majority voter;

taking the FPGA in the prior art as an example, the netlist file after user synthesis is in vqm format.

In the embodiment of the present disclosure, as shown in fig. 4, a triple modular redundancy process is performed based on vqm, a module in vqm that needs redundancy, such as an lcell, is duplicated in triplicate, a voter is added, and the output of the voter is used as the input of the next-stage unit. The final redundant result is still a netlist file in vqm format. And after the redundancy processing, gate-level simulation, layout and wiring and code stream generation are continuously carried out.

In the embodiment of the present disclosure, as shown in fig. 5 and 6, the target icell 1 is first copied into two copies of icell 2 and icell 3; then adding a majority voter at the next stage of the lcell; three redundant lcell inputs are homologous; as the input of majority voter; finally, the modules which do not need redundancy on the path are processed in a convergence mode.

The pseudo code of the redundancy algorithm is as follows:

l is all molecular level units;

c is a unit set needing redundancy processing;

the design of the voter is as follows:

the vqm form of the netlist derived by logically synthesizing in Quartus for the voter design described above is as follows:

so far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

From the above description, those skilled in the art should clearly recognize that the present disclosure is based on the triple modular redundancy method of the molecular-level netlist.

In summary, the present disclosure provides a triple modular redundancy method based on a molecular netlist, where redundant objects are molecular-level units such as lcell and slice in an FPGA; the redundant area can be reduced, and the complexity of subsequent layout and wiring can also be reduced. The convergence concept in redundancy does not make redundancy for the dff and other time-sequence devices, and further inhibits the area increase caused by redundancy. Specifically vqm implementations of a majority voter. The user does not need to carry out redundancy design on the design, the original design is synthesized, and the synthesized netlist file is processed by the tool disclosed by the invention to realize redundancy processing. The redundancy scheme disclosed by the invention is soft redundancy, and compared with hardware redundancy, the redundancy scheme is low in cost and easy to implement. The redundancy scheme is that a part of molecular level units in the FPGA are subjected to redundancy design; the redundant netlist file has certain advantages in area and power consumption compared with a gate-level redundancy scheme. After redundancy processing is carried out on the basis of the molecular netlist, the equivalence verification of the netlist can be carried out by performing gate-level simulation by using simulation tools such as modelSim and the like, and the verification is convenient.

It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.

And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.