阅读说明：本技术 半导体元件及其形成方法 (Semiconductor device and method for forming the same ) 是由 邓雅骏 郑允玮 宋健铭 于 2020-08-19 设计创作，主要内容包括：一种半导体元件及其形成方法,半导体元件包括像素阵列,像素阵列包括第一像素及第二像素。半导体元件包括金属结构,金属结构上覆基板的在第一像素与第二像素之间的一部分。半导体元件包括邻近金属结构的侧壁的第一阻障层。半导体元件包括邻近第一阻障层的侧壁的钝化层。第一阻障层位于钝化层与金属结构之间。(A semiconductor device and a method for forming the same are provided, the semiconductor device includes a pixel array including a first pixel and a second pixel. The semiconductor element includes a metal structure overlying a portion of the substrate between the first pixel and the second pixel. The semiconductor device includes a first barrier layer adjacent to a sidewall of a metal structure. The semiconductor device includes a passivation layer adjacent to sidewalls of the first barrier layer. The first barrier layer is located between the passivation layer and the metal structure.)

1. A semiconductor device, comprising:

a pixel array including a first pixel and a second pixel;

a metal structure overlying a portion of a substrate between the first pixel and the second pixel;

a first barrier layer adjacent to a sidewall of the metal structure; and

a passivation layer adjacent a sidewall of the first barrier layer, wherein the first barrier layer is between the passivation layer and the metal structure.

2. The semiconductor device of claim 1, wherein the first barrier layer covers the metal structure.

3. The semiconductor element according to claim 1, wherein:

the first barrier layer is in contact with the sidewall of the metal structure; and is

The passivation layer contacts the sidewalls of the first barrier layer.

4. The semiconductor element according to claim 1, wherein:

the first barrier layer is in contact with the sidewall of the metal structure; and is

The passivation layer is in contact with a top surface of the metal structure.

5. The semiconductor device according to claim 1, comprising:

a filter material covering the first pixel and adjacent to a sidewall of the passivation layer.

6. A semiconductor device, comprising:

a pixel array including a first pixel and a second pixel;

a first barrier layer overlying a portion of a substrate between the first pixel and the second pixel;

a metal structure overlying the first barrier layer and overlying a portion of a substrate between the first pixel and the second pixel; and

a second barrier layer adjacent to a sidewall of the metal structure and contacting a sidewall of the first barrier layer.

7. The semiconductor device of claim 6, wherein the first barrier layer and the second barrier layer comprise a same material composition.

8. The semiconductor device according to claim 6, comprising:

a passivation layer, wherein the second barrier layer is between the metal structure and the passivation layer.

9. A method of forming a semiconductor device, comprising:

forming a metal structure on a first dielectric layer and overlying a portion of a substrate between a first pixel and a second pixel;

forming a first barrier layer on the metal structure and the first dielectric layer;

removing a portion of the first barrier layer over the first dielectric layer to expose a top surface of the first dielectric layer; and

forming a filter on the top surface of the first dielectric layer after removing the portion of the first barrier layer.

10. The method of claim 9, comprising:

a passivation layer is formed on the top surface of the first dielectric layer after removing the portion of the first barrier layer and before forming the filter.

Technical Field

The present application relates to a semiconductor device and a method of forming the same.

Background

A semiconductor device, such as a complementary metal-oxide-semiconductor (CMOS) image sensor, includes a pixel array for detecting radiation, such as light, impinging on pixels of the pixel array. The CMOS image sensor includes a grid array defining optical paths through which radiation is directed toward each pixel. A filter material is disposed within the optical path between the grid structures of the grid array to filter the radiation such that only certain wavelengths of radiation reach each pixel.

Disclosure of Invention

Embodiments of the present disclosure include a semiconductor device including a pixel array, a metal structure, a first barrier layer, and a passivation layer. The pixel array comprises a first pixel and a second pixel. The metal structure overlies a portion of the substrate between the first pixel and the second pixel. The first barrier layer is adjacent to the side wall of the metal structure. The passivation layer is adjacent to a sidewall of the first barrier layer, wherein the first barrier layer is between the passivation layer and the metal structure.

Embodiments of the present disclosure also include a semiconductor device including a pixel array, a first barrier layer, a metal structure, and a second barrier layer. The pixel array comprises a first pixel and a second pixel. The first barrier layer overlies a portion of the substrate between the first pixel and the second pixel. The metal structure overlies the first barrier layer and a portion of the substrate between the first pixel and the second pixel. The second barrier layer is adjacent to the sidewalls of the metal structure and contacts the sidewalls of the first barrier layer.

Embodiments of the present disclosure further include a method of forming a semiconductor device, the method comprising forming a metal structure on a first dielectric layer and overlying a portion of a substrate between a first pixel and a second pixel. The method also includes forming a first barrier layer over the metal structure and the first dielectric layer. The method further includes removing a portion of the first barrier layer over the first dielectric layer to expose a top surface of the first dielectric layer. The method also includes forming a filter on a top surface of the first dielectric layer after removing a portion of the first barrier layer.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that the various features are not drawn to scale in accordance with standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A-1J are perspective views of semiconductor structures according to some embodiments;

fig. 2A-2I are diagrams of cross-sectional views of a semiconductor device at various stages of fabrication according to some embodiments;

fig. 3 is an illustration of a cross-sectional view of a semiconductor component according to some embodiments;

fig. 4 is an illustration of a cross-sectional view of a semiconductor component according to some embodiments;

fig. 5 is an illustration of a cross-sectional view of a semiconductor component according to some embodiments;

fig. 6 is an illustration of a cross-sectional view of a semiconductor element according to some embodiments;

fig. 7 is an illustration of a cross-sectional view of a semiconductor element according to some embodiments.

[ notation ] to show

100 semiconductor element

101 base plate

102 back side

103 isolation region

104 first dielectric layer

104' a first dielectric structure

105 pixel array

106 the first barrier layer

106' first barrier structure

107 pixels

108 metal layer

108' metal structure

109 front side

110 second dielectric layer

110' a second dielectric structure

111 third dielectric layer

111' a third dielectric structure

112 grid structure

113 interconnect structure

114 direction of radiation travel

115 conducting wire

116 conductive via/contact

117 optical path

118 the second barrier layer

119 part of a substrate

122 passivation layer

130 first filter material

132 second Filter Material

200 semiconductor element

202 grid structure

208 second barrier layer

208' part of the second barrier layer

216 passivation layer

230 first filter material

232 second filter material

300 semiconductor element

302 portion of the second barrier layer

400 semiconductor element

500 semiconductor device

502 width (width)

504 width (b)

600 semiconductor element

700 semiconductor device

701 average width of first dielectric structure

Average width of first barrier structure 702

703 average width of metal structure

704 average width of second dielectric structure

705 average width of third dielectric structure

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, in various examples, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "below … … (beneath)", "below … … (below)", "lower (lower)", "above … … (above)" and "upper" and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures for ease of description. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In some embodiments, a semiconductor element including a pixel array is provided. In some embodiments, the semiconductor device includes a grid array formed over the pixel array. In some embodiments, the grid array includes a grid structure formed over and between pixels of the pixel array. The grid structure also includes a metal structure to reflect radiation to create an optical path for directing radiation to the pixels. In some embodiments, a first barrier layer is formed adjacent to one or more sidewalls of each metal structure. In some embodiments, a first barrier layer is further disposed on each of the metal structures. In some embodiments, the semiconductor element includes a second barrier layer under each of the metal structures. In some embodiments, the semiconductor device includes a passivation layer adjacent to sidewalls of the first barrier layer such that the first barrier layer is between the passivation layer and the metal structure. In some embodiments, the semiconductor device comprises a cmos image sensor, such as a backside illuminated cmos image sensor.

In some embodiments, the first barrier layer reduces diffusion of metal within the metal structure into the optical path between the grid structures. In some embodiments, the first barrier layer provides enhanced adhesion between the metal structure and surrounding non-metal materials (such as a passivation layer).

Fig. 1A-1J are cross-sectional views of a semiconductor device 100 with a second barrier layer 118 formed, according to some embodiments. In some embodiments, the semiconductor device 100 includes a complementary metal-oxide-semiconductor (CMOS) image sensor, such as a backside illuminated CMOS image sensor.

Referring to fig. 1A, according to some embodiments, a substrate 101 including a pixel array 105 is provided. The substrate 101 has a front side 109 and a back side 102. In some embodiments, the substrate 101 is a monocrystalline silicon substrate, a doped substrate comprising monocrystalline silicon (having a <100> crystallographic orientation), or other suitable material. The pixel array 105 includes a plurality of pixels 107, such as photodiodes, phototransistors, etc., formed within the substrate 101 or on a front side 109 of the substrate. In some embodiments, the pixels 107 are configured to sense radiation, such as incident light, projected from the backside 102 toward the substrate 101. Radiation entering the substrate 101 through the backside 102 is detected by one or more of the pixels 107. In some embodiments, the pixels 107 include pinned layer photodiodes (pinned layer photodiodes), photogates (photomasks), reset transistors (reset transistors), source follower transistors (source follower transistors), transfer transistors (transfer transistors), and the like. The pixels 107 may vary from one another to have different junction depths, thicknesses, widths, etc. Even though 2 pixels are depicted, any number of pixels may be formed within the substrate 101. In some embodiments, isolation regions 103, such as backside isolation regions, are disposed between pixels 107 such that the isolation regions 103 are offset from the pixels 107 in a direction perpendicular to a direction 114 of radiation travel that enters the substrate 101 and is detected by the pixels 107. In some embodiments, the isolation region 103 is a Shallow Trench Isolation (STI) structure.

According to some embodiments, the interconnect structure 113 is formed on the front side 109 of the substrate 101. In some embodiments, the interconnect structure 113 includes a plurality of patterned dielectric and conductive layers that provide interconnections, such as routing, between various doped features, circuitry, and input/output terminals of the semiconductor element 100. In some embodiments, the interconnect structure 113 includes interlayer dielectrics and multilayer interconnect structures, such as contacts, vias, metal lines, and the like. For illustrative purposes, the interconnect structure 113 includes the conductive lines 115 and vias/contacts 116 illustrated in fig. 1A, which are merely exemplary, and the actual positioning and configuration may vary depending on design requirements.

In some embodiments, additional layers are formed between the interconnect structure 113 and the front side 109 of the substrate 101. For example, interlayer dielectrics, thermal dielectrics, metal blocks, redistribution layers, and the like may be present between the interconnect structure 113 and the front side 109 of the substrate 101. In some embodiments, additional layers are formed on a surface of the interconnect structure 113 opposite the substrate 101, such as interlayer dielectrics, thermal dielectrics, redistribution layers, application specific integrated circuits, and the like. In some embodiments, the carrier substrate is bonded with the substrate 101 via the interconnect structure 113 and any additional layers present on the front side 109 of the substrate 101 such that processing of the back side 102 of the substrate 101 may be performed as described below.

In some embodiments, the semiconductor device 100 may include other regions not shown in fig. 1A or in the previous figures. For example, in the case where the semiconductor device 100 is a backside illuminated Complementary Metal Oxide Semiconductor (CMOS) image sensor, the backside illuminated Complementary Metal Oxide Semiconductor (CMOS) image sensor may include a pixel region (at least a portion of which is shown), a peripheral region (not shown), a contact pad region (not shown), a black level calibration region (not shown), a backside scribe line region (not shown), and the like.

Fig. 1B to 1J are cross-sectional views of a grid array formed on the substrate 101. Referring to fig. 1B, a first dielectric layer 104 is formed on the substrate 101 according to some embodiments. In some embodiments, the first dielectric layer 104 comprises a material that is substantially optically transparent to the wavelengths of radiation intended to be received by the pixels 107. In some embodiments, the first dielectric layer 104 comprises SiO₂Or a low-k material. Low-k dielectric materials have k values (dielectric constants) below about 3.9. Some low-k dielectric materials have k values below about 3.5, and may have k values below about 2.5.

Referring to fig. 1C, according to some embodiments, a first barrierLayer 106 is formed on first dielectric layer 104. In some embodiments, the first barrier layer 106 includes a metallic material. Examples of the metallic material include, but are not limited to, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), alloys thereof, or other suitable metallic materials. In some embodiments, the first barrier layer 106 includes a dielectric material. Examples of dielectric materials include, but are not limited to, silicon oxide (SiO)_x) Silicon nitride (SiN)_x) Silicon carbide (SiC)_x) Titanium nitride (TiN)_x) Tantalum nitride (TaN)_x) Hafnium oxide (HfO)_x) Tantalum oxide (TaO)_x) Aluminum oxide (AlO)_x) Or other suitable dielectric material, wherein x is a value greater than or equal to 1. In some embodiments, the first barrier layer 106 comprises a single material layer. In some embodiments, the first barrier layer 106 includes multiple material layers. For example, the first barrier layer 106 may comprise a silicon nitride (SiN)_x) Layer, silicon oxide (SiO)_x) Layer and another silicon nitride (SiN)_x) And (3) a layer.

Referring to fig. 1D, a metal layer 108 is formed on the first barrier layer 106, according to some embodiments. In some embodiments, the metal layer 108 comprises tungsten or other suitable metallic material. Referring to fig. 1E, according to some embodiments, a second dielectric layer 110 is formed on the metal layer 108, and a third dielectric layer 111 is formed on the second dielectric layer 110. In some embodiments, the material composition of the second dielectric layer 110 is different from the material composition of the third dielectric layer 111. In some embodiments, the second dielectric layer 110 comprises SiO₂Or a low-k material. In some embodiments, the second dielectric layer 110 has the same material composition as the first dielectric layer 104. In some embodiments, the third dielectric layer 111 comprises a high-k dielectric material. As used herein, the term "high-k dielectric" refers to a dielectric having a dielectric constant greater than or equal to about 3.9 (which is SiO)₂K value of (c) dielectric constant k. The material of the high-k dielectric layer may be any suitable material. Examples of materials for the high-k dielectric layer include, but are not limited to, Al₂O₃、HfO₂、ZrO₂、La₂O₃、TiO₂、SrTiO₃、LaAlO₃、Y₂O₃、Al₂O_xN_y、HfO_xN_y、ZrO_xN_y、La₂O_xN_y、TiO_xN_y、SrTiO_xN_y、LaAlO_xN_y、Y₂O_xN_y、SiON、SiN_xSilicates thereof and alloys thereof. Each value of x is independently from 0.5 to 3, and each value of y is independently from 0 to 2.

Although the example embodiment illustrates two dielectric layers 110, 111 as being formed on metal layer 108, any number of dielectric layers may be formed on metal layer 108. For example, in some embodiments, the second dielectric layer 110 is formed on the metal layer 108 instead of the third dielectric layer 111. Furthermore, in some embodiments, neither the second dielectric layer 110 nor the third dielectric layer 111 is formed on the metal layer 108, and thus the process described with respect to fig. 1E is skipped.

Referring to fig. 1F, the first dielectric layer 104, the first barrier layer 106, the metal layer 108, the second dielectric layer 110, and the third dielectric layer 111 are removed to define a grid structure 112, according to some embodiments. In some embodiments, each of the grid structures 112 includes at least one of a first dielectric structure 104 defined from the first dielectric layer 104, a first barrier structure 106 defined from the first barrier layer 106, a metal structure 108 defined from the metal layer 108, a second dielectric structure 110 'defined from the second dielectric layer 110, and a third dielectric structure 111' defined from the third dielectric layer 111. In some embodiments, each grid structure 112 is disposed between two adjacent pixels such that the first dielectric structure 104', the first barrier structure 106', the metal structure 108', the second dielectric structure 110', and the third dielectric structure 111' of a first grid structure 112 overlie a portion 119 of the substrate 101 between the first pixel 107 and the second pixel 107. In some embodiments, between each grid structure 112 and each pixel 107 is an optical path 117, through which optical path 117 radiation is directed from adjacent grid structures 112 to a pixel 107 between adjacent grid structures 112.

In some embodiments, portions of the first dielectric layer 104, the first barrier layer 106, the metal layer 108, the second dielectric layer 110, and the third dielectric layer 111 are removed by an etching process. In some embodiments, the etching process comprises forming a photoresist layer over the third dielectric layer 111 and patterning the photoresist layer such that some portions of the underlying third dielectric layer 111 are covered by the photoresist layer while other portions of the third dielectric layer 111 are uncovered or exposed.

In some embodiments, after patterning the photoresist layer, the portions of the third dielectric layer 111 not covered by the photoresist layer are exposed to an etchant that removes or etches away portions of the third dielectric layer 111, as well as portions of the second dielectric layer 110, the metal layer 108, the first barrier layer 106, and the first dielectric layer 104 under the uncovered portions of the third dielectric layer 111. In some embodiments, depending on the material composition of the layers 104, 106, 108, 110, and 111 and the etch selectivity of the layers 104, 106, 108, 110, and 111, an etch process may be performed in multiple stages using different etch chemistries or different etch recipes to remove portions of the first dielectric layer 104, the first barrier layer 106, the metal layer 108, the second dielectric layer 110, and the third dielectric layer 111.

In some embodiments, the sidewalls of the grid structure 112 are vertical or in a plane perpendicular to the top surface of the substrate 101. In some embodiments, the sidewalls of the grid structure 112 are tapered (such as illustrated in fig. 6). In some embodiments, different layers of the grid structure 112 have different sidewall angles, such as where the third dielectric structure 111' has a different sidewall angle than at least one of the second dielectric structure 110', the metal structure 108', the first barrier structure 106', or the first dielectric structure 104 '. In some embodiments, at least one layer shrinks (such as depicted in fig. 7) such that a width of a middle portion of the at least one layer is less than a width of an upper portion of the at least one layer above the middle portion and less than a width of a lower portion of the at least one layer below the middle portion. In some embodiments, the sidewalls of the various layers are vertical, coplanar with one another, uniformly tapered, or have various taper angles (resulting in one or more of the structures 104', 106', 108', 110', 111' having different sidewall angles), as a function of the manner in which the etch process or processes are performed.

In some embodiments, the portion of the substrate 101 overlying the pixel 107 remains covered or hidden by at least a portion of the first dielectric layer 104 after the etching process or processes. Thus, after the grid structure 112 is formed, the pixels 107 continue beneath the first dielectric layer 104. In some embodiments, portions of the substrate 101 overlying the pixels 107 are exposed due to the etching process or processes.

Referring to fig. 1G, a second barrier layer 118 is formed on the grid structure 112, according to some embodiments. In some embodiments, the second barrier layer 118 is further formed on the first dielectric layer 104. In some embodiments, the second barrier layer 118 is conformally formed over the grid structure 112 and the first dielectric layer 104. In some embodiments, the second barrier layer 118 may be formed in a non-conformal manner. In some embodiments, the second barrier layer 118 contacts sidewalls of at least one of the third dielectric structure 111', the second dielectric structure 110', the metal structure 108', the first barrier structure 106', or the first dielectric structure 104 '. In some embodiments, the second barrier layer 208 contacts sidewalls of the first dielectric layer 104 (such as sidewalls of the first dielectric structure 104') and a top surface of the first dielectric layer 104. In some embodiments, the thickness of the second barrier layer 208 is not uniform. For example, as illustrated by fig. 5, the width 502 of the second barrier layer 118 proximate the intermediate sidewall portions of the grid structure 112 is less than the width 504 of the second barrier layer 118 proximate the lower sidewall portions of the grid structure 112. In some embodiments, the second barrier layer 118 comprises SiOx, SiN_x、SiC_x、TiN_x、TaN_x、HfO_x、TaO_x、AlO_xOr other suitable material. In some embodiments, the second barrier layer 118 has the same material composition as the first barrier layer 106.

In some embodiments, the second barrier layer 118 comprises multiple layers, such as a first TiN layer that provides isolation for the metal structure 108', and then a second Ti layer that provides improved adhesion to a subsequently formed passivation layer 122. In some embodiments, the first TiN layer has a thickness of about 35 angstroms. In some embodiments, the second Ti layer has a thickness of about 100 angstroms. In some embodiments, the second barrier layer 118 has a thickness between about 10 angstroms and 2,000 angstroms.

In some embodiments where the portion of the substrate 101 overlying the pixel 107 remains hidden by the first dielectric layer 104 after the etch process or processes, the first dielectric layer 104 separates the second barrier layer 118 from the portion of the substrate 101 overlying the pixel 107, and thus from the pixel 107. In some embodiments where portions of the overlying pixels 107 of the substrate 101 are exposed after the etching process or processes, the second barrier layer 118 may contact portions of the overlying pixels 107 of the substrate 101.

Referring to fig. 1H, a portion of the second barrier layer 118 is removed, according to some embodiments. In some embodiments, a portion of the second barrier layer 118 overlying the first dielectric layer 104 and between the grid structures 112 is removed by an etching process. In some embodiments where portions of the substrate 101 overlying the pixels 107 are covered by the first dielectric layer 104, removal of portions of the second barrier layer 118 exposes the first dielectric layer 104. In some embodiments in which portions of the substrate 101 overlying the pixels 107 are not covered by the first dielectric layer 104, removal of the portion of the second barrier layer 118 exposes portions of the substrate 101 overlying the pixels 107. In some embodiments, a portion of the second barrier layer 118 overlying the third dielectric layer 111 is also removed by the etching process. In some embodiments, the second etching process is a blanket etching process without using a photoresist mask.

Referring to fig. 1I, a passivation layer 122 is formed on the grid structure 112, according to some embodiments. In some embodiments where portions of the substrate 101 overlying the pixels 107 are covered by the first dielectric layer 104, the passivation layer 122 is formed on the first dielectric layer 104. In some embodiments where portions of the substrate 101 overlying the pixels 107 are covered by the first dielectric layer 104, the passivation layer 122 contacts a top surface of the first dielectric layer 104. In some embodiments where portions of the substrate 101 overlying the pixels 107 are not covered by the first dielectric layer 104, the passivation layer 122 contacts the backside of the portions of the substrate 101 overlying the pixels 107. In some embodiments, the passivation layer 122 contacts the sidewalls of the second barrier layer 118.

In some embodiments, the passivation layer 122 is formed using a conformal deposition process to deposit a material having a material composition different from the material composition of the second barrier layer 118. In some embodiments, the passivation layer 122 has a thickness between about 10 angstroms and about 2,000 angstroms. In some embodiments, the passivation layer 122 comprises a material that is substantially optically transparent to the wavelengths of radiation intended to be received by the pixels 107.

Referring to fig. 1J, according to some embodiments, filter materials 130, 132 are formed within the optical path 117 between the grid structures 112. In some embodiments, a first filter material 130 is deposited between a first pair of adjacent grid structures 112 and overlying the first pixels 107 so as to filter certain wavelengths (colors) of radiation channeled through the first filter material 130 to the first pixels 107. In some embodiments, a second filter material 132 is deposited between the second pair of adjacent grid structures 112 and overlying the second pixels 107 so as to filter certain wavelengths (colors) of radiation channeled through the second filter material 132 to the second pixels 107. In some embodiments, the first filter material 130 and the second filter material 132 have different material compositions to enable different wavelengths to be filtered. In some embodiments, the passivation layer 122 is disposed between the filter materials 130, 132 and the first dielectric layer 104, or between the filter materials 130, 132 and portions of the substrate 101 overlying the pixels 107.

In some embodiments, the second barrier layer 118 provides isolation between the metal structure 108' and the passivation layer 122. In some embodiments, the second barrier layer 118 provides improved adhesion to the passivation layer 122 relative to a structure in which the second barrier layer 118 is not provided. In some embodiments, by providing isolation and adhesion, diffusion of the metal structure 108 'through the passivation layer 122 is mitigated, thereby mitigating the possibility of the metal structure 108' causing interference with the optical path 117.

Fig. 2A-2I are cross-sectional views of a semiconductor device 200 with a second barrier layer 208 formed according to some embodiments. In some embodiments, the semiconductor device 200 comprises a CMOS image sensor, such as a backside illuminated CMOS image sensor.

Referring to fig. 2A, according to some embodiments, a substrate 101 including a pixel array 105 is provided. The substrate 101 has a front side 109 and a back side 102. The pixel array 105 includes a plurality of pixels 107, such as photodiodes, phototransistors, etc., formed within the substrate 101. In some embodiments, the pixels 107 are configured to sense radiation, such as incident light, projected from the backside 102 toward the substrate 101. Radiation entering the substrate 101 through the backside 102 is detected by one or more of the pixels 107. In some embodiments, the pixel 107 includes a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, a transfer transistor, and the like. The pixels 107 may vary from one another to have different junction depths, thicknesses, widths, etc. Even though 2 pixels are depicted, any number of pixels may be formed within the substrate 101. In some embodiments, isolation regions 103, such as backside isolation regions, are disposed between pixels 107 such that the isolation regions 103 are offset from the pixels 107 in a direction perpendicular to a direction 114 of radiation travel that enters the substrate 101 and is detected by the pixels 107. In some embodiments, the isolation region 103 is a Shallow Trench Isolation (STI) structure.

According to some embodiments, an interconnect structure 113 is formed on the front side 109 of the substrate 101. In some embodiments, the interconnect structure 113 includes a plurality of patterned dielectric and conductive layers that provide interconnections, such as routing, between various doped features, circuitry, and input/output terminals of the semiconductor element 100. In some embodiments, the interconnect structure 113 includes an interlevel dielectric and multilevel interconnect structures, such as contacts, vias, metal lines, and the like. For illustrative purposes, the interconnect structure 113 includes the conductive lines 115 and vias/contacts 116 illustrated in fig. 2A, which are merely exemplary, and the actual positioning and configuration may vary depending on design requirements.

Fig. 2B to 2I are cross-sectional views of a grid array formed on the substrate 101. Referring to fig. 2B, a first dielectric layer 104 is formed on the substrate 101 according to some embodiments. In some embodiments, the first dielectric layer 104 comprises a material that is substantially optically transparent to the wavelengths of radiation intended to be received by the pixels 107. In some embodiments, the first dielectric layer 104 comprises SiO₂Or a low-k material.

Referring to fig. 2C, a first barrier layer 106 is formed on the first dielectric layer 104, according to some embodiments. In some embodiments, the first barrier layer 106 includes a metallic material. Examples of metallic materials include, but are not limited to, W, Cu, Al, Co, Ni, Ti, Ta, alloys thereof, or other suitable metallic materials. In some embodiments, the first barrier layer 106 comprises a dielectric material. Examples of dielectric materials include, but are not limited to, SiO_x、SiN_x、SiC_x、TiN_x、TaN_x、HfO_x、TaO_x、AlO_xOr other suitable dielectric material, wherein x is a value greater than or equal to 1. In some embodiments, the first barrier layer 106 comprises a single material layer. In some embodiments, the first barrier layer 106 includes multiple material layers. For example, the first barrier layer 106 may comprise SiN_xLayer of SiO_xLayer and another SiN_xAnd (3) a layer.

Referring to fig. 2D, a metal layer 108 is formed on the first barrier layer 106, according to some embodiments. In some embodiments, the metal layer 108 comprises tungsten or other suitable metallic material. Referring to fig. 2E, the first dielectric layer 104, the first barrier layer 106, and the metal layer 108 are removed to define the grid structure 202, according to some embodiments. In some embodiments, each of the grid structures 202 includes at least one of a first dielectric structure 104' defined from the first dielectric layer 104, a first barrier structure 106' defined from the first barrier layer 106, and a metal structure 108' defined from the metal layer 108. In some embodiments, each lattice structure 202 is disposed between two adjacent pixels such that the first dielectric structure 104', the first barrier structure 106', and the metal structure 108' of a first lattice structure 112 overlie a portion 119 of the substrate 101 between the first pixel 107 and the second pixel 107. In some embodiments, between each grid structure 202 and each pixel 107 is an optical path 117, through which optical path 117 radiation is directed from adjacent grid structures 202 to a pixel 107 between adjacent grid structures 202. In some embodiments, the etching process includes a photolithography and etching process to define the grid structure 202.

In some embodiments, portions of the first dielectric layer 104, the first barrier layer 106, and the metal layer 108 are removed by an etching process. In some embodiments, the etch process includes forming a photoresist layer over the metal layer 108 and patterning the photoresist layer such that some portions of the underlying metal layer 108 are covered by the photoresist layer while other portions of the metal layer 108 are uncovered or exposed.

In some embodiments, after patterning of the photoresist layer, the portions of the metal layer 108 not covered by the photoresist layer are exposed to an etchant that removes or etches away portions of the metal layer 108, as well as portions of the first barrier layer 106 and the first dielectric layer 104 under the uncovered portions of the metal layer 108. In some embodiments, depending on the material composition of the layers 104, 106, and 108 and the etch selectivity of the layers 104, 106, and 108, the etch process may be performed in multiple stages using different etch chemistries or different etch recipes to remove portions of the first dielectric layer 104, the first barrier layer 106, and the metal layer 108.

In some embodiments, the sidewalls of the grid structure 202 are vertical or in a plane perpendicular to the top surface of the substrate 101. In some embodiments, the sidewalls of the grid structure 202 are tapered (such as illustrated in fig. 6). In some embodiments, different layers of the grid structure 202 have different sidewall angles, such as where the metal structure 108' has a different sidewall angle than at least one of the first barrier structure 106' or the first dielectric structure 104 '. In some embodiments, at least one layer shrinks (such as depicted in fig. 7) such that a width of a middle portion of the at least one layer is less than a width of an upper portion of the at least one layer above the middle portion and less than a width of a lower portion of the at least one layer below the middle portion. In some embodiments, the sidewalls of the various layers are vertical, coplanar with one another, uniformly tapered, or have various taper angles (resulting in one or more of the structures 104', 106', 108' having different sidewall angles), as a function of the manner in which the etch process or processes are performed.

In some embodiments, the portion of the substrate 101 overlying the pixel 107 remains covered or hidden by at least a portion of the first dielectric layer 104 after the etching process or processes. Thus, after the grid structure 202 is formed, the pixels 107 continue beneath the first dielectric layer 104. In some embodiments, portions of the substrate 101 overlying the pixels 107 are exposed due to the etching process or processes.

Referring to fig. 2F, a second barrier layer 208 is formed on the grid structure 202, according to some embodiments. In some embodiments, the second barrier layer 208 is further formed on the first dielectric layer 104. In some embodiments, the second barrier layer 208 is conformally formed over the grid structure 202 and the first dielectric layer 104. In some embodiments, the second barrier layer 208 may be formed in a non-conformal manner. In some embodiments, the second barrier layer 208 contacts sidewalls of the metal structure 108'. In some embodiments, the second barrier layer 208 contacts sidewalls of the first dielectric layer 104 (such as sidewalls of the first dielectric structure 104') and a top surface of the first dielectric layer 104. In some embodiments, the second barrier layer 208 comprises SiOx, SiN_x、SiC_x、TiN_x、TaN_x、HfO_x、TaO_x、AlO_xOr other suitable material. In some embodiments, the second barrier layer 208 has the same material composition as the first barrier layer 106.

In some embodiments, the second barrier layer 208 comprises multiple layers, such as a first TiN layer that provides isolation for the metal structure 108', and then a second Ti layer that provides improved adhesion to a subsequently formed passivation layer 216. In some embodiments, the first TiN layer has a thickness of about 35 angstroms. In some embodiments, the second Ti layer has a thickness of about 100 angstroms. In some embodiments, second barrier layer 208 has a thickness between about 10 angstroms and 2,000 angstroms.

In some embodiments where the portion of the substrate 101 overlying the pixel 107 remains hidden by the first dielectric layer 104 after the etch process or processes, the first dielectric layer 104 separates the second barrier layer 208 from the portion of the substrate 101 overlying the pixel 107. In some embodiments where portions of the overlying pixels 107 of the substrate 101 are exposed after the etching process or processes, the second barrier layer 208 may contact portions of the overlying pixels 107 of the substrate 101.

Referring to fig. 2G, a portion of the second barrier layer 208 is removed, according to some embodiments. In some embodiments, a portion of the second barrier layer 208 overlying the first dielectric layer 104 and between the grid structures 202 is removed by an etching process. In some embodiments where portions of the substrate 101 overlying the pixels 107 are covered by the first dielectric layer 104, removal of portions of the second barrier layer 208 exposes the first dielectric layer 104. In some embodiments where portions of the substrate 101 overlying the pixels 107 are not covered by the first dielectric layer 104, removal of the portion of the second barrier layer 208 exposes portions of the substrate 101 overlying the pixels 107. In some embodiments, the etching process utilizes a photoresist mask to protect a portion of the overlying metal structure 108' of the second barrier layer 208 from the etching process. In some embodiments, the portion 208' of the second barrier layer 208 overlies the pixel 107 due to the use of a photoresist mask for the etch process.

Referring to fig. 2H, a passivation layer 216 is formed on the grid structure 202, according to some embodiments. In some embodiments where portions of the substrate 101 overlying the pixels 107 are covered by the first dielectric layer 104, a passivation layer 216 is formed on the first dielectric layer 104. In some embodiments where portions of the substrate 101 overlying the pixels 107 are covered by the first dielectric layer 104, the passivation layer 216 contacts a top surface of the first dielectric layer 104. In some embodiments where portions of the substrate 101 overlying the pixels 107 are not covered by the first dielectric layer 104, the passivation layer 216 contacts the backside of the portions of the substrate 101 overlying the pixels 107. In some embodiments, the passivation layer 216 contacts the sidewalls and top surface of the second barrier layer 208.

In some embodiments, the passivation layer 216 is formed using a conformal deposition process to deposit a material having a material composition different from the material composition of the second barrier layer 208. In some embodiments, the passivation layer 216 has a thickness between about 10 angstroms and about 2,000 angstroms. In some embodiments, the passivation layer 216 comprises a material that is substantially optically transparent to the wavelengths of radiation intended to be received by the pixels 107.

Referring to fig. 2I, according to some embodiments, filter materials 130, 132 are formed within the optical path 117 between the grid structures 202. In some embodiments, a first filter material 230 is deposited between a first pair of adjacent grid structures 202 and overlying the first pixels 107 so as to filter certain wavelengths (colors) of radiation channeled through the first filter material 230 to the first pixels 107. In some embodiments, a second filter material 232 is deposited between the second pair of adjacent grid structures 202 and overlying the second pixels 107 so as to filter certain wavelengths (colors) of radiation channeled through the second filter material 232 to the second pixels 107. In some embodiments, the first filter material 230 and the second filter material 232 have different material compositions to enable different wavelengths to be filtered. In some embodiments, the passivation layer 122 is disposed between the filter materials 130, 132 and the first dielectric layer 104, or between the filter materials 130, 132 and portions of the substrate 101 overlying the pixels 107.

In some embodiments, the second barrier layer 208 provides isolation between the metal structure 108' and the passivation layer 216. In some embodiments, the second barrier layer 208 provides improved adhesion to the passivation layer 216 relative to a structure in which the second barrier layer 208 is not provided. In some embodiments, by providing isolation and adhesion, diffusion of the metal structure 108 'through the passivation layer 216 is mitigated, thereby mitigating the possibility of the metal structure 108' causing interference with the optical path 117.

Fig. 3 is a cross-sectional view of a semiconductor device 300 having a second barrier layer 118 formed therein, in accordance with some embodiments. The semiconductor device 300 differs from the semiconductor device 100 illustrated in fig. 1J in that the second barrier layer 118 is etched according to the process described with respect to fig. 2G such that the second barrier layer 118 is disposed between the top surface of the third dielectric structure 111' and the bottom surface of the passivation layer 122. Furthermore, in some embodiments, the portion 302 of the second barrier layer 118 overlies the pixel 107 due to the use of a photoresist mask for the etching process.

Fig. 4 is a cross-sectional view of a semiconductor device 400 having a second barrier layer 208 formed therein, in accordance with some embodiments. The semiconductor device 400 differs from the semiconductor device 200 shown in fig. 2I in that the second barrier layer 208 is etched according to the process described with respect to fig. 1H such that the second barrier layer 208 is removed from the top surface of the metal structure 108' and the top surface of the first dielectric layer 104.

Fig. 5 is a cross-sectional view of a semiconductor device 500 having a second barrier layer 118 formed therein, in accordance with some embodiments. The semiconductor device 500 differs from the semiconductor device 100 illustrated in fig. 1J in that the second barrier layer 118 is non-conformally formed on the grid structure 112 such that a width 502 of a first portion of the second barrier layer 118 is different from a width 504 of a second portion of the second barrier layer 118. In some embodiments, the width 504 near the bottom or top of the second barrier layer 118 is greater than the width 502 of the second barrier layer 118 near the middle portion of the second barrier layer 118. It should be appreciated that although example embodiments illustrate the second barrier layer 118 as being non-conformally formed during the formation of a semiconductor device 500 similar to the semiconductor device 100, the second barrier layer 118 may also be non-conformally formed during the formation of any of the semiconductor devices 200, 300, 400.

Fig. 6 is a cross-sectional view of a semiconductor device 600 having a metal structure 108', the metal structure 108' having a contracted configuration due to an etching process that removes a portion of the metal layer 108 to form the metal structure 108 '. For example, in some embodiments, the width 602 in the middle portion of the metal structure 108' is less than the width 604 in the lower portion of the metal structure 108' below the middle portion and less than the width 606 in the upper portion of the metal structure 108' above the middle portion. In some embodiments where the metal structure 108' has a constricted configuration, the second barrier layer 118 may be formed in a non-conformal manner such that the width of the second barrier layer 118 adjacent the middle portion of the metal structure 108' is greater than the width of the second barrier layer 118 adjacent the first barrier structure 106', the second dielectric structure 110', the third dielectric structure 111', and so on. In some embodiments where the metal structure 108' has a contracted configuration, the second barrier layer 118 may be formed conformally, and the width of the passivation layer 122 or the width of the filters 130, 132 adjacent to the middle portion of the metal structure 108' is greater than the width of the passivation layer 122 or the width of the filters 130, 132 adjacent to the first barrier structure 106', the second dielectric structure 110', the third dielectric structure 111', etc.

Fig. 7 is a cross-sectional view of a semiconductor device 700 formed with a grid structure 112, the grid structure 112 having a tapered configuration due to the etching process or processes. In some embodiments, the average width 701 of the first dielectric structure 104 'is greater than the average width 702 of the first barrier structure 106'. In some embodiments, the average width 702 of the first barrier structure 106 'is greater than the average width 703 of the metal structure 108'. In some embodiments, the average width 703 of the metal structure 108 'is greater than the average width 704 of the second dielectric structure 110'. In some embodiments, the average width 704 of the second dielectric structure 110 'is greater than the average width 705 of the third dielectric structure 111'.

In some embodiments, a semiconductor device is provided that includes a pixel array, a metal structure, a first barrier layer, and a passivation layer. The pixel array comprises a first pixel and a second pixel. The metal structure overlies a portion of the substrate between the first pixel and the second pixel. The first barrier layer is adjacent to the side wall of the metal structure. The passivation layer is adjacent to a sidewall of the first barrier layer, wherein the first barrier layer is between the passivation layer and the metal structure.

In some embodiments, the semiconductor device further comprises a second barrier layer disposed under the metal structure.

In some embodiments, the second barrier layer and the first barrier layer comprise the same material composition.

In some embodiments, the first barrier layer covers the metal structure.

In some embodiments, the passivation layer overlies the first barrier layer.

In some embodiments, the first barrier layer is in contact with sidewalls of the metal structure, and the passivation layer is in contact with sidewalls of the first barrier layer.

In some embodiments, the first barrier layer is in contact with sidewalls of the metal structure and the passivation layer is in contact with a top surface of the metal structure.

In some embodiments, the semiconductor device further includes a dielectric layer overlying the first pixel and underlying the metal structure, the passivation layer contacting the dielectric layer.

In some embodiments, the first barrier layer is in contact with sidewalls of the dielectric layer.

In some embodiments, the semiconductor device further includes a dielectric layer over the metal structure, the first barrier layer being adjacent to sidewalls of the dielectric layer.

In some embodiments, the semiconductor element further includes a filter material overlying the first pixel and adjacent to the sidewall of the passivation layer.

In some embodiments, a semiconductor device is provided that includes a pixel array, a first barrier layer, a metal structure, and a second barrier layer. The pixel array comprises a first pixel and a second pixel. The first barrier layer overlies a portion of the substrate between the first pixel and the second pixel. The metal structure overlies the first barrier layer and a portion of the substrate between the first pixel and the second pixel. The second barrier layer is adjacent to the sidewalls of the metal structure and contacts the sidewalls of the first barrier layer.

In some embodiments, the first barrier layer and the second barrier layer comprise the same material composition.

In some embodiments, the semiconductor device further comprises a passivation layer, and the second barrier layer is between the metal structure and the passivation layer.

In some embodiments, the semiconductor device further comprises a first dielectric layer disposed below the first barrier layer.

In some embodiments, the semiconductor device further comprises a passivation layer, wherein the passivation layer and the second barrier layer contact the first dielectric layer.

In some embodiments, the first barrier layer contacts the first dielectric layer.

In some embodiments, a method for forming a semiconductor device is provided. The method includes forming a metal structure on a first dielectric layer and overlying a portion of a substrate between a first pixel and a second pixel. The method also includes forming a first barrier layer over the metal structure and the first dielectric layer. The method further includes removing a portion of the first barrier layer over the first dielectric layer to expose a top surface of the first dielectric layer. The method also includes forming a filter on a top surface of the first dielectric layer after removing a portion of the first barrier layer.

In some embodiments, the method further comprises forming a passivation layer on the top surface of the first dielectric layer after removing the portion of the first barrier layer and before forming the filter.

In some embodiments, the method further includes removing a portion of the first barrier layer over the metal structure, and forming a passivation layer over the metal structure after removing the portion of the first barrier layer over the metal structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Various operations of embodiments are provided herein. The order in which some or all of the operations are described should not be construed as to imply that these operations are necessarily order dependent. Alternative orderings of preparation with the present description should be understood. In addition, it should be understood that not all operations are necessarily present in each embodiment provided herein. Also, it should be understood that not all operations are necessary.

It will be appreciated that layers, features, elements, etc. depicted herein are illustrated with particular dimensions (such as structural dimensions or orientations) relative to one another, e.g., for simplicity and ease of understanding, and in one or more embodiments, their actual dimensions are substantially different from those illustrated herein. In addition, there are a variety of techniques for forming the layers, features, components, etc. mentioned herein, such as etching techniques, implantation techniques, doping techniques, spin-on techniques, sputtering techniques (such as magnetron or ion beam sputtering), growth techniques (such as thermal growth), or deposition techniques (such as CVD, PVD, PECVD, or ALD).

Moreover, "exemplary" is used herein to mean serving as an example, instance, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". Furthermore, the use of "a" and "an" and the appended claims in this application is generally to be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. Also, at least one of A and B and/or the like generally means A or B or both A and B. Furthermore, to the extent that the terms "includes," has, "" with, "or variants thereof are used, such terms are intended to be inclusive in a manner similar to the term" comprising. Also, unless otherwise specified, "first," "second," or the like are not intended to imply temporal aspects, spatial aspects, ordering, or the like. Rather, such terms are used merely as terms of identification, names, etc. for features, elements, items, etc. For example, the first and second elements generally correspond to elements a and B, or two different or two identical elements or a same element.

Also, although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations, and is not limited only by the scope of the claims. In particular regard to the various functions performed by the above described components (e.g., elements, resources, etc.), the terms used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure. Furthermore, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.