阅读说明：本技术 多核嵌入式系统及其基于串口虚拟化实现通信的方法 (Multi-core embedded system and method for realizing communication based on serial port virtualization ) 是由 项智 杨明华 韦天保 徐华丽 于 2021-05-26 设计创作，主要内容包括：本发明提供一种多核嵌入式系统及其基于串口虚拟化实现通信的方法,所述多核嵌入式系统包括：片上系统,所述片上系统包括多核异构嵌入式处理器系统和可编程逻辑模块；所述可编程逻辑模块包括：通信模块,所述通信模块通过通信接口建立可编程逻辑模块与服务器系统之间的通信连接；串口控制器,所述串口控制器基于局部总线连接于多核异构嵌入式处理器系统和通信模块之间,所述串口控制器基于局部总线地址域和所述通信模块的地址域的转换从而实现将所述串口控制器虚拟化连接到所述服务器系统。本发明可以有效解决多核嵌入式系统在没有实际的物理串口链路的情况下无法实现串口数据通信的技术问题。(The invention provides a multi-core embedded system and a method for realizing communication based on serial port virtualization, wherein the multi-core embedded system comprises: the system on chip comprises a multi-core heterogeneous embedded processor system and a programmable logic module; the programmable logic module comprises: the communication module establishes communication connection between the programmable logic module and the server system through a communication interface; the serial port controller is connected between the multi-core heterogeneous embedded processor system and the communication module based on a local bus, and the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of a local bus address domain and an address domain of the communication module. The invention can effectively solve the technical problem that the multi-core embedded system can not realize serial data communication under the condition of no actual physical serial link.)

1. A multi-core embedded system, characterized by: the multi-core embedded system comprises:

the system on chip comprises a multi-core heterogeneous embedded processor system and a programmable logic module;

the programmable logic module comprises:

the communication module establishes communication connection between the programmable logic module and the server system through a communication interface;

the serial port controller is connected between the multi-core heterogeneous embedded processor system and the communication module based on a local bus, and the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of a local bus address domain and an address domain of the communication module.

2. The multi-core embedded system of claim 1, wherein: the programmable logic module is an FPGA, and the multi-core heterogeneous embedded processor system is a multi-core heterogeneous embedded ARM processor system; the server system is an X86 server system.

3. The multi-core embedded system according to claim 1 or 2, wherein: the multi-core heterogeneous embedded processor system adopts an MPSoC heterogeneous chip.

4. The multi-core embedded system of claim 1, wherein: the communication module is a PCI-Express communication module; the communication interface is a PCI-Express interface; the local bus is an AXI4 bus.

5. The multi-core embedded system according to claim 1 or 2, wherein: the multi-core heterogeneous embedded processor system comprises double-rate memory particles or memory chips, an embedded multimedia memory and a flash memory device based on a queue serial peripheral interface protocol.

6. The multi-core embedded system of claim 1, wherein: the serial port controller is an asynchronous receiving and transmitting serial port controller.

7. A method for realizing communication of a multi-core embedded system based on serial port virtualization is characterized in that: the method comprises the following steps:

connecting a programmable logic module of the multi-core embedded system with a server system through a communication module;

configuring a serial port controller based on a local bus in the programmable logic module; the serial port controller is connected between the multi-core heterogeneous embedded processor system and the communication module, and the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of a local bus address domain and an address domain of the communication module.

8. The method for realizing communication of the multi-core embedded system based on serial port virtualization according to claim 7, characterized in that: the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of the local bus address field and the address field of the communication module, and comprises the following steps:

the multi-core heterogeneous embedded processor system sends data to be sent by the multi-core heterogeneous embedded processor system to a serial port controller through a local bus by a serial port driver, the serial port controller sends the data to the communication module based on the conversion of a local bus address domain and an address domain of the communication module, and the communication module sends the data to be sent by the multi-core heterogeneous embedded processor system to a server system through a PCI-Express interface;

the multi-core heterogeneous embedded processor system receives data from the server system from the serial port controller through a serial port driver, and the serial port controller transmits the received data of the server system to the multi-core heterogeneous embedded processor system based on the conversion of a local bus address domain and an address domain of the communication module.

9. The method for realizing communication of the multi-core embedded system based on serial port virtualization according to claim 7 or 8, characterized in that: the programmable logic module is an FPGA, and the multi-core heterogeneous embedded processor system is a multi-core heterogeneous embedded ARM processor system; the server system is an X86 server system; the multi-core heterogeneous embedded processor system adopts an MPSoC heterogeneous chip.

10. The method for realizing communication based on serial port virtualization of the multi-core embedded system according to claim 9, characterized in that: the serial port controller is an asynchronous receiving and transmitting serial port controller.

Technical Field

The invention belongs to the technical field of embedded systems, and particularly relates to a multi-core embedded system and a method for realizing communication based on serial port virtualization.

Background

The MPSoC (Multi Processor System on Chip) is a second generation Multi-processing SoC System (System on Chip) from saints corporation, and includes an advanced power management System, a high-density on-Chip static memory, a high-speed transceiver with a single channel rate up to 32Gbps, a PCI-Express interface, and high-performance programmable logic.

The traditional MPSoC platform firmware generally requires an external UART, Ethernet or USB interface and an associated cable for software debugging and man-machine interaction. However, in the field of data centers, external interfaces such as the PCI-Express interface are not existed. Under the condition of not configuring UART, Ethernet and USB interfaces, software debugging and man-machine interaction of the MPSoC platform are inconvenient.

Disclosure of Invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a multi-core embedded system and a method for implementing communication based on serial port virtualization, so as to solve the technical problem that the multi-core embedded system in the prior art cannot implement serial port data communication without an actual physical serial port link.

An embodiment of the present invention provides a multi-core embedded system, including: the system on chip comprises a multi-core heterogeneous embedded processor system and a programmable logic module; the communication module establishes communication connection between the programmable logic module and the server system through a communication interface; the programmable logic module comprises: the communication module establishes communication connection between the programmable logic module and the server system through a communication interface; the serial port controller is connected between the multi-core heterogeneous embedded processor system and the communication module based on a local bus, and the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of a local bus address domain and an address domain of the communication module.

In an embodiment of the present application, the programmable logic module is an FPGA, and the multi-core heterogeneous embedded processor system is a multi-core heterogeneous embedded ARM processor system; the server system is an X86 server system.

In an embodiment of the present application, the multi-core heterogeneous embedded processor system employs an MPSoC heterogeneous chip.

In an embodiment of the present application, the communication module is a PCI-Express communication module; the communication interface is a PCI-Express interface; the local bus is an AXI4 bus.

In an embodiment of the present application, the multi-core heterogeneous embedded processor system includes a double-rate memory granule or a memory chip, an embedded multimedia memory, and a flash memory device based on a queue serial peripheral interface protocol.

In an embodiment of the application, the serial port controller is an asynchronous transceiving serial port controller.

The embodiment of the application also provides a method for realizing communication of the multi-core embedded system based on serial port virtualization, which comprises the following steps: connecting a programmable logic module of the multi-core embedded system with a server system through a communication module; configuring a serial port controller based on a local bus in the programmable logic module; the serial port controller is connected between the multi-core heterogeneous embedded processor system and the communication module, and the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of a local bus address domain and an address domain of the communication module.

In an embodiment of the present application, the virtualizing, by the serial port controller, the connection to the server system based on the conversion between the local bus address field and the address field of the communication module includes: the multi-core heterogeneous embedded processor system sends data to be sent by the multi-core heterogeneous embedded processor system to a serial port controller through a local bus by a serial port driver, the serial port controller sends the data to the communication module based on the conversion of a local bus address domain and an address domain of the communication module, and the communication module sends the data to be sent by the multi-core heterogeneous embedded processor system to a server system through a PCI-Express interface; the multi-core heterogeneous embedded processor system receives data from the server system from the serial port controller through a serial port driver, and the serial port controller transmits the received data of the server system to the multi-core heterogeneous embedded processor system based on the conversion of a local bus address domain and an address domain of the communication module.

In an embodiment of the present application, the programmable logic module is an FPGA, and the multi-core heterogeneous embedded processor system is a multi-core heterogeneous embedded ARM processor system; the server system is an X86 server system; the multi-core heterogeneous embedded processor system adopts an MPSoC heterogeneous chip.

In an embodiment of the application, the serial port controller is an asynchronous transceiving serial port controller.

As described above, the online upgrade method and system of the multi-core embedded system of the present invention have the following advantages:

1. the serial port controller is arranged in the programmable logic module of the system on chip, the serial port controller realizes the virtual connection of the serial port controller to the Server system based on the conversion of a local bus address field and an address field of the communication module, so that the serial port (ARM serial port) of the multi-core heterogeneous embedded ARM processor system in the MPSoC processor system is communicated with the serial port of the programmable logic module (FPGA), and the serial port of the programmable logic module (FPGA) is communicated with the Server system (X86 Server) through a PCIe bus to realize the aims of serial port data communication and data interaction of the heterogeneous processors, thereby effectively solving the technical problem that the multi-core embedded system in the prior art can not realize the serial port data communication without an actual physical serial port link.

2. The multi-core embedded system is simple in implementation mode, and the MPSoC platform can realize software debugging and man-machine interaction without additional hardware interfaces and cables.

Drawings

FIG. 1 is a schematic diagram of the schematic structure of the multi-core embedded system of the present invention.

FIG. 2 is a schematic diagram of the framework structure of the multi-core embedded system of the present invention.

FIG. 3 is a schematic diagram of the communication principle of the multi-core embedded system of the present invention.

FIG. 4 is a diagram of a software framework of the multi-core embedded system according to the present invention.

FIG. 5 is a schematic diagram illustrating a communication flow of the multi-core embedded system according to the present invention.

Fig. 6 is a communication flow diagram of the server system according to the present invention.

Fig. 7 is a flowchart illustrating an online upgrade method for a multi-core embedded system according to the present invention.

Description of the element reference numerals

10 server system

20 multi-core embedded system

200 system on chip

210 multi-core heterogeneous embedded processor system

201 MPSoC heterogeneous chip

211 memory module

212 memory

213 flash memory module

214 universal asynchronous receiving and transmitting transmitter

215 extended multifunctional IO interface

216 Embedded multimedia storage controller

217 embedded multimedia memory

220 embedded programmable logic module

221 serial port controller

222 communication module

S100 to S200

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.

The embodiment aims to provide a multi-core embedded system and a method for realizing communication based on serial port virtualization, which are used for solving the technical problem that the multi-core embedded system in the prior art cannot realize serial port data communication without an actual physical serial port link.

The principle and implementation of the online upgrade method and system of the multi-core embedded system of the present invention will be described in detail below, so that those skilled in the art can understand the online upgrade method and system of the multi-core embedded system of the present invention without creative work.

Example 1

The present embodiment provides a multi-core embedded system 20. FIG. 1 is a schematic diagram of a multi-core embedded system 20 according to the present invention. As shown in fig. 1, in this embodiment, the multi-core embedded system 20 includes: a system on a chip 200, the system on a chip 200 including a multi-core heterogeneous embedded processor system 210 and an embedded programmable logic module 220.

The technical means adopted by the multi-core embedded system 20 to realize the serial port of the heterogeneous virtual machine in the embodiment is data communication of the serial port of the heterogeneous processor. The data interaction is achieved by communicating the serial port of the multi-core heterogeneous embedded processor system 210(ARM) in the multi-core embedded system 20 with the serial port of the embedded programmable logic module 220(FPGA), and the serial port of the embedded programmable logic module 220(FPGA) communicates with the Server system 10 (e.g., X86 Server) through a PCIe bus.

In this embodiment, the server system 10 is configured to provide upper computer functions of the multi-core embedded system 20, such as software debugging and human-computer interaction. Specifically, the server system 10 is, but not limited to, an X86 server system 10.

Fig. 2 is a schematic diagram of a schematic framework structure of the multi-core embedded system 20 of the present embodiment. As shown in fig. 2, in the embodiment, the multi-core heterogeneous embedded processor system 210 employs an MPSoC heterogeneous chip 201. Further, in this embodiment, the embedded Programmable logic module 220 is an FPGA (Field Programmable Gate Array), and the multi-core heterogeneous embedded processor system 210 is a multi-core heterogeneous embedded ARM processor system.

In this embodiment, the embedded programmable logic module 220 is an FPGA, and the embedded programmable logic module 220 maps the programmable logic addressing unit of the embedded programmable logic module 220 into the server system 10 through the local bus. Wherein the local bus is, but not limited to, AXI4-LITE bus.

That is, in the present embodiment, the embedded programmable logic module 220 implements address mapping via the AXI4-LITE bus. Specifically, the programmable logic addressing unit is mapped inside the embedded programmable logic module 220(FPGA) through the AXI4-LITE bus into the server system 10(X86 server system), and the server system 10(X86 server system) accesses the programmable logic addressing unit through the PCI-Express bus. In this embodiment, the data bit width of the AXI4-LITE bus is 32 bits, and the address bit width is 32 bits.

In this embodiment, the programmable logic module includes: a communication module 222, wherein the communication module 222 establishes a communication connection between the programmable logic module 220 and the server system 10 through a communication interface. In the present embodiment, the communication module 222 is preferably a PCI-Express communication module; the communication interface is a PCI-Express interface.

To implement a heterogeneous virtual machine serial port, in this embodiment, the embedded programmable logic module 220 includes: a serial port controller 221; the serial port controller 221 is connected between the multi-core heterogeneous embedded processor system 210 and the communication module 222 based on a local bus (AXI4-LITE bus), and the serial port controller 221 realizes the virtual connection of the serial port controller 221 to the server system 10 based on the conversion of the local bus address domain and the address domain of the communication module 222.

In this embodiment, the serial controller 221 is an asynchronous transceiving serial controller, and the embedded programmable logic module 220 implements asynchronous transceiving data communication with the multicore heterogeneous embedded ARM processor system through the asynchronous transceiving serial controller. Namely, the bridging of data communication between the server system 10(X86 server system) and the multi-core heterogeneous embedded ARM processor system is realized by connecting the serial port controller 221 based on the AXI4-LITE bus interface to the server system virtually inside the embedded programmable logic module 220 (FPGA).

Specifically, the PCI-Express bus data transmission between the service system 10 and the programmable logic module 220(FPGA) is based on a PCI-Express bus address domain, the AXI4-LITE bus data transmission between the programmable logic module 220(FPGA) and the multi-core embedded ARM processor system is based on an AXI4-LITE bus address domain, the two address domains cannot directly perform data transmission, the serial port controller 221 performs the conversion from the AXI4-LITE bus address domain to the PCI-Express bus address domain, and the serial port controller 221 realizes the communication bridging between the multi-core embedded processor system 210 and the service system 10 by performing the conversion from the AXI4-LITE bus address domain to the PCI-Express bus address domain, namely corresponding to the realization of the virtual connection of the serial port controller 221 to the PCI-Express interface.

That is to say, the serial port controller 221 embedded in the programmable logic module 220 is connected to the serial port of the multi-core heterogeneous embedded ARM processor system through an AXI4-LITE bus, and the serial port controller 221 embedded in the programmable logic module 220 communicates with the server system 10(X86 server system) through a PCIe bus, so as to achieve the purpose that the multi-core embedded system 20 achieves serial port data communication without an actual physical serial port link.

As shown in fig. 2, in the present embodiment, the multi-core heterogeneous embedded processor system 210 employs an MPSoC heterogeneous chip 201, and the multi-core heterogeneous embedded processor system 210 further includes a memory module 211 connected to the MPSoC heterogeneous chip 201, a memory 212, a flash memory module 213, and the like. Further, in the present embodiment, the Multi-memory module 211 is, but not limited to, a double-rate memory granule or a memory chip, the memory 212 is, but not limited to, an Embedded multimedia memory (eMMC), and the flash memory module 213 is, but not limited to, a Queue Serial Peripheral Interface (QSPI) based flash memory. The double rate memory granule or the memory chip preferably adopts a fourth generation double rate dynamic memory granule or a dynamic memory chip (DDR 4).

In addition, as shown in fig. 3, the multi-core heterogeneous embedded processor system 210 is provided with an embedded multimedia memory 217, an embedded multimedia memory controller 216 controlling the embedded multimedia memory 217, and a universal asynchronous receiver transmitter 214 (UART). The universal asynchronous transceiver 214 is connected to the serial controller 221 of the embedded programmable logic module 220(FPGA) through an extended multifunctional IO interface 215(EMIO), the serial controller 221 of the embedded programmable logic module 220(FPGA) is connected to the communication module 222(PCIE communication module) through an AXI4_ data line, and the communication module 222(PCIE communication module) is connected to the server system 10(X86 server system) through a communication interface and a PCIE _ data line.

Fig. 4 is a schematic diagram of a software framework of the multi-core embedded system 20 according to the embodiment. As shown in fig. 4, the server system 10(X86 server system) includes an application program and a communication device driver (i.e., PCIE device driver); the application program converts characters input by the equipment terminal into ASCII codes and then sends the ASCII codes to the PCIE equipment driver, and the application program receives the ASCII codes from the PCIE equipment driver, converts the ASCII codes into the characters and outputs the characters to the equipment terminal. The PCIE device driver is configured to implement an interaction function between the server system 10(X86 server system) and a PCIE device embedded in the programmable logic module 220(FPGA), and implement an interaction function with a PCIE device driver in the multi-core embedded system 20.

The multi-core heterogeneous embedded processor system 210 comprises an application program (ARM application program) running in the embedded Linux system, a universal asynchronous receiver/transmitter device driver, and a universal asynchronous receiver/transmitter 214 driven by the universal asynchronous receiver/transmitter device driver, wherein after the application program of the embedded Linux system is started and run, the universal asynchronous receiver/transmitter device driver drives the universal asynchronous receiver/transmitter 214, and the output information is sent to a serial port controller 221 embedded in a programmable logic module 220(FPGA) through the universal asynchronous receiver/transmitter 214.

In this embodiment, the specific communication process between the multi-core embedded system 20 and the server system 10 is as follows:

the multi-core heterogeneous embedded processor system 210 sends data to be sent by the multi-core heterogeneous embedded processor system to a serial port controller 221 through a serial port driver, the serial port controller 221 sends the data to a PCI-Express interface based on the conversion between a local bus address domain and an address domain of the communication module, and the PCI-Express interface sends the sent data of the multi-core heterogeneous embedded processor system to the server system 10; the multi-core heterogeneous embedded processor system 210 receives data from the server system 10 from the serial controller 221 through a serial driver, and the serial controller 221 transfers the received data of the server system 10 into the multi-core heterogeneous embedded processor system based on the conversion between the local bus address domain and the address domain of the communication module.

Specifically, in this embodiment, a specific communication process between the multi-core embedded system 20 and the server system 10 is as follows:

1) as shown in fig. 5, for a multi-core heterogeneous embedded ARM processor system:

the Linux system of the multi-core heterogeneous embedded ARM processor system is started, a universal asynchronous transceiver 214 device serial port driver of the multi-core heterogeneous embedded ARM processor system sends data to a serial port controller 221 embedded in a programmable logic module 220(FPGA), then data communication of the Linux system is monitored, when the Linux system sends the data, the serial port driver sends the data to the serial port controller 221 embedded in the programmable logic module 220(FPGA), when the Linux system receives the data, the serial port driver receives the data from the serial port controller 221 embedded in the programmable logic module 220(FPGA), and sends the data to the Linux system.

2) As shown in fig. 6, for the server system 10(X86 server system):

a PCIE device driver of the server system 10 (for example, X86 server system) is initialized, and the server system 10 simultaneously monitors data from the serial port controller 221 embedded in the programmable logic module 220(FPGA) and data of the terminal device. When the receiving end of the serial port controller 221 is monitored to have data, the data of the serial port controller 221 is read, and then the read data is converted into characters to be output to the terminal device for display. When it is monitored that data is input into the terminal device, the characters input into the terminal device are converted into ASCII codes and sent to the sending end of the serial port controller 221.

Therefore, in the multi-core embedded system 20 in this embodiment, the serial port controller 221 is disposed in the embedded programmable logic module 220 of the system-on-chip 200, so that the serial port (serial port of the ARM) of the multi-core heterogeneous embedded ARM processor system in the mpoc processor system communicates with the serial port of the embedded programmable logic module 220(FPGA), and the serial port of the embedded programmable logic module 220(FPGA) communicates with the Server system 10(X86 Server) through the PCIe bus to achieve the purpose of heterogeneous processor serial port data communication and data interaction, thereby effectively solving the technical problem that the multi-core embedded system 20 cannot achieve serial port data communication without an actual physical serial port link in the prior art, and the soc mpo can achieve software debugging and man-machine interaction without additional hardware interfaces and cables.

Example 2

As shown in fig. 7, this embodiment provides an online upgrade method for a multi-core embedded system, which is applied to an mposc platform, and the online upgrade method for the multi-core embedded system includes the following steps:

step S100, connecting a programmable logic module of the multi-core embedded system with a server system through a communication module;

step S200, configuring a serial port controller based on a local bus in the programmable logic module; the serial port controller realizes the virtual connection of the serial port controller to the server system based on the conversion of the local bus address field and the address field of the communication module.

In this embodiment, the virtualizing, by the serial port controller, the connection to the server system based on the conversion between the local bus address field and the address field of the communication module includes: the multi-core heterogeneous embedded processor system sends data to be sent by the multi-core heterogeneous embedded processor system to a serial port controller through a local bus by a serial port driver, the serial port controller sends the data to the communication module based on the conversion of a local bus address domain and an address domain of the communication module, and the communication module sends the data to be sent by the multi-core heterogeneous embedded processor system to a server system through a PCI-Express interface; the multi-core heterogeneous embedded processor system receives data from the server system from the serial port controller through a serial port driver, and the serial port controller transmits the received data of the server system to the multi-core heterogeneous embedded processor system based on the conversion of a local bus address domain and an address domain of the communication module.

In this embodiment, the programmable logic module is an FPGA, the serial port controller is an asynchronous transceiving serial port controller, and the multi-core heterogeneous embedded processor system is a multi-core heterogeneous embedded ARM processor system; the server system is an X86 server system; the multi-core heterogeneous embedded processor system adopts an MPSoC heterogeneous chip.

The online upgrade method and the implementation principle of the multi-core embedded system in this embodiment are the same as the implementation principle of the multi-core embedded system 20 in embodiment 1, and similar or identical technical features between the embodiments are not described again.

In summary, the serial port controller is arranged in the programmable logic module of the system on chip, and the serial port controller is connected to the Server system in a virtualized manner based on the conversion between the local bus address field and the address field of the communication module, so that the serial port (serial port of the ARM) of the multi-core heterogeneous embedded ARM processor system in the MPSoC processor system is communicated with the serial port of the programmable logic module (FPGA), and the serial port of the programmable logic module (FPGA) is communicated with the Server system (X86 Server) through the PCIe bus to achieve the purpose of serial port data communication and data interaction of the heterogeneous processor, thereby effectively solving the technical problem that the serial port data communication cannot be achieved by the multi-core embedded system in the prior art without an actual physical serial port link; the multi-core embedded system is simple in implementation mode, and the MPSoC platform can realize software debugging and man-machine interaction without additional hardware interfaces and cables. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.