阅读说明：本技术 半导体存储装置 (Semiconductor memory device with a plurality of memory cells ) 是由 和田政春 池田圭司 于 2019-12-30 设计创作，主要内容包括：一形态中的半导体存储装置具有多条字线、多条位线、及多个第1半导体晶体管。多条字线沿着第1方向。多条位线沿着不同于所述第1方向的第2方向,且具有第1、第2、及第3面。第1面朝着与所述第1、第2方向都不同的第3方向。第2面朝着与所述第2、第3方向都不同的第4方向。第3面配置在所述第2面的相反侧。多个第1半导体晶体管具有连接于所述多条字线中的任一条字线的栅极、及连接于所述多条位线中的任一条位线的所述第1面、及所述第2或第3面的沟道。(In one aspect, a semiconductor memory device has a plurality of word lines, a plurality of bit lines, and a plurality of 1 st semiconductor transistors. The plurality of word lines are along a 1 st direction. The plurality of bit lines are along a 2 nd direction different from the 1 st direction and have 1 st, 2 nd, and 3 rd planes. The 1 st face faces a 3 rd direction different from the 1 st and 2 nd directions. The 2 nd face faces a 4 th direction different from the 2 nd and 3 rd directions. The 3 rd surface is disposed on the opposite side of the 2 nd surface. The 1 st semiconductor transistors have gates connected to any one of the word lines, and channels connected to the 1 st surface and the 2 nd or 3 rd surface of any one of the bit lines.)

1. A semiconductor memory device has:

a plurality of word lines along a 1 st direction; a plurality of bit lines along a 2 nd direction different from the 1 st direction, and having a 1 st surface facing a 3 rd direction different from the 1 st and 2 nd directions, a 2 nd surface facing a 4 th direction different from the 2 nd and 3 rd directions, and a 3 rd surface disposed on an opposite side of the 2 nd surface; and a plurality of 1 st semiconductor transistors including gates connected to any one of the plurality of word lines, and channels connected to the 1 st surface and the 2 nd or 3 rd surface of any one of the plurality of bit lines.

2. The semiconductor memory device according to claim 1, wherein

Channels of the 1 st semiconductor transistors are alternately connected to the 2 nd and 3 rd planes along any one of the bit lines.

3. The semiconductor storage device according to claim 1 or 2, wherein

The channels of the 1 st semiconductor transistors are connected to one of the 2 nd and 3 rd surfaces along any one of the word lines.

4. The semiconductor memory device according to any one of claims 1 to 3, wherein

The plurality of word lines have a 1 st portion connected to gates of the plurality of 1 st semiconductor transistors, and a 2 nd portion which is not connected to the gates and has a width narrower than the 1 st portion.

5. The semiconductor memory device according to any one of claims 1 to 4, wherein

Further comprising: a plurality of 2 nd word lines arranged to face the plurality of word lines with the plurality of bit lines interposed therebetween; and a plurality of 2 nd semiconductor transistors each including a gate connected to any one of the plurality of 2 nd word lines, a 4 th surface connected to any one of the plurality of bit lines on a side opposite to the 1 st surface, and a channel on the 2 nd or 3 rd surface.

6. The semiconductor memory device according to any one of claims 1 to 5, wherein

The channels of one of the 1 st semiconductor transistors and one of the 2 nd semiconductor transistors are connected to one of the 2 nd and 3 rd surfaces.

7. The semiconductor memory device according to any one of claims 1 to 5, wherein

A channel of one of the 1 st semiconductor transistors is connected to one of the 2 nd and 3 rd surfaces, and a channel of one of the 2 nd semiconductor transistors is connected to the other of the 2 nd and 3 rd surfaces.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein

The channel includes an oxide semiconductor, the semiconductor storage device also having an oxide layer configured between the bit line and the channel and different from the oxide semiconductor.

9. The semiconductor memory device according to claim 8, wherein

The oxide semiconductor contains indium-gallium-zinc-oxide, and the oxide layer contains one of indium-gallium-silicon-oxide, gallium oxide, aluminum oxide, and hafnium oxide.

10. The semiconductor memory device according to any one of claims 1 to 9, wherein

And a plurality of capacitors respectively connected to channels of the plurality of 1 st semiconductor transistors.

Technical Field

Embodiments of the present invention relate to a semiconductor memory device.

Background

A semiconductor memory device having a bit line, a word line, and a memory cell (a transistor and a capacitor) connected to the bit line and the word line is currently used. Data can be written in and read out from the memory cell by applying voltages to selected bit lines and word lines.

Semiconductor memory devices have been increasingly densified, and bit line widths have become smaller. Therefore, the resistance between the bit line and the transistor increases, which may hinder the semiconductor memory device from increasing in speed.

Disclosure of Invention

The invention provides a semiconductor memory device which realizes low resistance of connection between a bit line and a transistor.

In one aspect, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of 1 st semiconductor transistors. The plurality of word lines are along a 1 st direction. The plurality of bit lines are along a 2 nd direction different from the 1 st direction and have 1 st, 2 nd, and 3 rd planes. The 1 st face faces a 3 rd direction different from the 1 st and 2 nd directions. The 2 nd face faces a 4 th direction different from the 2 nd and 3 rd directions. The 3 rd surface is disposed on the opposite side of the 2 nd surface. The 1 st semiconductor transistors have gates connected to any one of the word lines and channels connected to the 1 st surface and the 2 nd or 3 rd surface of any one of the bit lines.

Drawings

Fig. 1 is a perspective view schematically showing a semiconductor memory device according to an embodiment.

Fig. 2 is a perspective view schematically showing a memory cell.

Fig. 3 is a cross-sectional view schematically showing a memory cell.

Fig. 4 is a top view schematically showing the configuration of a memory cell in the embodiment.

Fig. 5 is a top view schematically showing the arrangement of a memory cell in the comparative method.

Fig. 6 is a top view schematically showing the arrangement of a memory cell in modification 1.

Fig. 7 is a top view schematically showing the arrangement of a memory cell in modification 2.

Fig. 8 is a top view schematically showing the arrangement of a memory cell in modification 3.

Fig. 9 is a flowchart showing an example of a manufacturing process of the semiconductor memory device.

Fig. 10 is a cross-sectional view schematically showing a semiconductor memory device in a manufacturing process.

Fig. 11 is a sectional view schematically showing a semiconductor memory device in a manufacturing process.

Fig. 12 is a sectional view schematically showing a semiconductor memory device in a manufacturing process.

Fig. 13 is a sectional view schematically showing a semiconductor memory device in a manufacturing process.

Fig. 14 is a sectional view schematically showing a semiconductor memory device in a manufacturing process.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings. Fig. 1 is a perspective view schematically showing a semiconductor memory device according to an embodiment. The semiconductor memory device includes bit lines BL, word lines WL (WLu, WLd), and memory cells MC (MCu, MCd).

Bit lines BL (1) to BL (j) extending in the X-axis direction (an example of the 2 nd direction) are arranged in parallel in the Y-axis direction (j: an integer). The bit line BL has an upper surface (an example of a 1 st surface) facing a positive Z-axis direction (an example of a 3 rd direction different from both the 1 st and 2 nd directions), a lower surface (an example of a 4 th surface opposite to the 1 st surface) facing a negative Z-axis direction, and 2 side surfaces (an example of a 2 nd and 3 rd surfaces) facing a positive Y-axis direction (an example of a 4 th direction different from both the 2 nd and 3 rd directions and an opposite direction).

Word lines WLu (1) to wlu (i) and WLd (1) to WLd (i) extending in the Y-axis direction (an example of the 1 st direction) are arranged above and below (positive and negative directions of the Z-axis) bit line BL in the X-axis direction (i: an integer). The memory cells MCu (i, j) and MCd (i, j) are arranged above the intersection of the bit line bl (i) and the word line wlu (j) and below the intersection of the bit line bl (i) and the word line wld (j).

As described below, the memory cells MCu (i, j), MCd (i, j) are connected to the upper surface (or lower surface) and the side surface of the bit line bl (i). As a result, the contact resistance between the memory cell MC and the bit line BL can be reduced.

Fig. 2 is a perspective view showing memory cells MC (MCu, MCd) connected to bit lines BL and word lines WL (WLu, WLd). Fig. 3 is a cross-sectional view schematically showing the memory cell MC (MCu, MCd). The memory cell MC (MCu, MCd) is formed by connecting a transistor 10(10u, 10d) and a capacitor 30(30u, 30 d). In fig. 2, the transistor 10 is shown separately from the capacitor 30 in view of visibility, and the substrate 21 and the interlayer insulating layers 22 to 27, which will be described later, are omitted.

The transistors 10u (an example of the 1 st semiconductor Transistor) and 10d (an example of the 2 nd semiconductor Transistor) are oxide semiconductor transistors arranged vertically and having an oxide semiconductor as the channel layer 13, and are so-called Surrounding Gate Transistors (SGTs) arranged so that the channel layer 13 is surrounded by the Gate electrode 14. The transistor 10 is also a so-called vertical transistor in which a source electrode 11, a gate electrode 14, and a drain electrode 12 are arranged in the thickness direction (Z direction) of a substrate 21.

The capacitor 30(30u, 30d) includes a cell electrode 31, an insulating film 32, and a plate electrode 33. The cell electrode 31 is connected to the drain electrode 12 of the transistor 10. The transistor 10 operates as a switching transistor of a DRAM (Dynamic Random Access Memory), and thereby charges are accumulated and held in the capacitor 30.

The transistor 10(10u, 10d) includes a bit line BL (source electrode 11), a drain electrode 12, a channel layer (oxide semiconductor layer) 13, a gate electrode 14 (word line WL (WLu, WLd)), a gate insulating layer 15, and an oxide layer 17.

The source electrode 11 and the drain electrode 12 may be made of a conductive material (e.g., a metal compound, a semiconductor, or a conductive oxide). The source electrode 11 and the drain electrode 12 may be made of a composite material (for example, a laminated structure of metal and conductive oxide, or a laminated structure of tungsten (W) and Indium Tin Oxide (ITO)). For example, the surfaces of the source and drain electrodes 11 and 12 on the channel layer 13 side may be indium tin oxide. The source electrode 11 constitutes a part of the bit line BL.

The drain electrode 12 is connected to the cell electrode 31 of the capacitor 30. By causing a current to flow from the drain electrode 12 to the capacitor 30, electric charges are injected into the capacitor 30.

The channel layer 13 (an example of a channel) electrically connects the source electrode 11 and the drain electrode 12. When the transistor 10 is turned on, a channel, which is a current path, is formed in the channel layer 13. The channel layer 13 is an oxide semiconductor, and contains indium (In), for example. The channel layer 13 contains, for example, indium oxide and gallium oxide, indium oxide and zinc oxide, or indium oxide and tin oxide. For example, so-called igzo (ingazno) containing indium oxide, gallium oxide, and zinc oxide (indium-gallium-zinc-oxide).

The gate electrode 14 is disposed between and apart from the source electrode 11 and the drain electrode 12, and constitutes a part of the word line WL. The gate electrode 14 is, for example, a metal compound, or a semiconductor. The gate electrode 14 is made of, for example, any one of W (tungsten), Ti (titanium), TiN (titanium nitride), Mo (molybdenum), Co (cobalt), and Ru (ruthenium).

The gate insulating layer 15 surrounds the outer periphery of the channel layer 13. The gate insulating layer 15 is, for example, an oxide or an oxynitride (e.g., silicon oxide).

The oxide layer 17 is disposed between the channel layer 13 and the source electrode 11 (bit line BL), and can reduce the connection resistance between the channel layer 13 and the source electrode 11. The channel layer 13 is an oxide semiconductor and contains oxygen. Therefore, oxygen in the channel layer 13 may combine with the metal of the source electrode 11 (bit line BL) to form a high-resistance metal oxide layer at the interface therebetween. The oxide layer 17 functions as a barrier layer for preventing oxygen in the channel layer 13 from reacting with the metal in the source electrode 11 (bit line BL), and prevents the formation of a metal oxide layer.

When the channel layer 13 is indium-gallium-zinc-oxide (IGZO: In-Ga-Zn oxide), the oxide layer 17 may be selected from indium-gallium-silicon-oxide (e.g., InGaSiO), gallium oxide (e.g., Ga)₂O₃) Aluminum oxide (e.g., Al)₂O₃) And hafnium oxide (e.g., HfO)₂) Any one of the above.

The substrate 21 is a semiconductor (e.g., silicon) substrate. The interlayer insulating layers 22 to 27 are, for example, oxides (e.g., silicon oxide) and electrically separate the upper and lower layers.

Fig. 4 shows a positional relationship of the memory cell MC (channel layer 13), the bit line BL (source electrode 11), and the word line WL (gate electrode 14) on the XY plane. Here, as shown in fig. 1 to 3, the memory cells MCu (i, j) and MCd (i, j) are arranged vertically along the Z axis. However, as described below, the memory cells MCu (i, j) and MCd (i, j) may be arranged to be shifted in the XY plane. This is also true in fig. 6 and 7 described later.

As shown in fig. 2 to 4, the memory cell MC (channel layer 13) is arranged near the center of the word line WL (gate electrode 14). On the other hand, the memory cell MC (channel layer 13) is arranged near a side (side surface) thereof with respect to the bit line BL (source electrode 11). That is, the center axis C0 of the channel layer 13 does not coincide with the center axis C1 of the bit line BL, but is arranged near the side of the bit line BL. Therefore, the memory cell MC (channel layer 13) is connected to the upper surface (or lower surface) and the side surface of the source electrode 11 (bit line BL). Therefore, the contact area between the channel layer 13 and the bit line BL can be secured, and the connection resistance can be reduced. As a result, the semiconductor memory device is easily speeded up.

Here, as shown in fig. 4, the memory cells MC are alternately arranged on two opposite side surfaces (2 side surfaces in the positive and negative directions of the Y axis) of the bit line BL along the bit line BL. On the other hand, the memory cell MC is disposed along the word line WL on one of the opposing side surfaces. More specifically, the memory cells MC are arranged on the positive Y-axis side of the odd-numbered word lines WL (1), WL (3), and … …, and on the negative Y-axis side of the even-numbered word lines WL (2), WL (4), and … ….

The memory cells MC are alternately arranged on both side surfaces of the bit line BL, thereby ensuring a distance between the memory cells MC on the same bit line BL. For example, if all the memory cells MC are arranged on the positive Y-axis direction side of the bit line BL, the distance between the memory cells MC adjacent in the X-axis direction (for example, the memory cells MC (1, 1) and MC (2, 1)) is smaller than the arrangement distance in fig. 4.

By securing the distance between the memory cells MC on the bit lines BL in this way, coupling (capacitive coupling) between the memory cells MC can be reduced. If the coupling between the memory cells MC increases, the adjacent memory cells MC may be affected (disturbed) when data is written into a certain memory cell MC. However, the distance between the memory cells MC may not be ensured. In this case, the connection resistance can be reduced.

(comparative system) fig. 5 shows the arrangement of memory cells MC in the comparative system. The memory cells MCu and MCd (channel layers 13) are arranged near the center of the bit line BL (source electrode 11) and connected only to the upper surface (or lower surface) of the bit line BL. The contact area of the upper surface of the bit line BL is larger than that in fig. 4. However, there is no contact on the side of the bit line BL, and therefore the total contact area is smaller than that of fig. 4, and the connection resistance increases. In addition, when there is no oxide layer 17, as described above, a metal oxide layer is formed at the interface of the channel layer 13 and the bit line BL, and the connection resistance may further increase.

(modification 1) fig. 6 shows the arrangement of the memory cell MC in modification 1. Here, the memory cell MC is disposed along the positive Y-axis side of the bit line BL (source electrode 11). In this case, the contact area between the channel layer 13 and the bit line BL may also be the same as that in fig. 4. Here, the width of the bit line BL is made smaller than that in fig. 4, but the size of the width does not affect the contact area. In this way, the width of the bit line BL can be reduced and the memory cell MC can be arranged on the side thereof.

(modification 2) fig. 7 shows the arrangement of the memory cell MC in modification 2. The arrangement of the memory cells MC is the same as that of fig. 4, but the width of the word line WL is not fixed. That is, the width of the word line WL is large at a portion where the memory cell MC (channel layer 13) is arranged (a substantially circular portion: an example of the 1 st portion), and is small at a portion where the memory cell MC is not arranged (a substantially rectangular portion: an example of the 2 nd portion). The width of the word line WL between the memory cells MC decreases. As a result, coupling (capacitive coupling), i.e., disturbance, between the memory cells MC is reduced.

(variation 3) fig. 8 shows the arrangement of the memory cell MC in variation 3. Here, the memory cells MCu and MCd are arranged in a staggered manner. That is, the channel layers 13 of the transistors 10u (i, j) and 10d (i, j) arranged vertically are connected to the opposite side surfaces of the bit line BL, respectively. That is, the channel layer 13 of the transistor 10u (i, j) is not directly connected to the channel layer 13 of the transistor 10d (i, j), the former being connected to either side surface (one of the 2 nd and 3 rd surfaces) of the bit line bl (j), and the latter being connected to the side surface (the other of the 2 nd and 3 rd surfaces) of the bit line bl (j) that faces the side surface. In this case, the memory cells MCu and MCd are connected to the upper surface (or lower surface) and the side surface of the bit line BL, and a connection area can be secured. Here, memory cell MCu (i, j) is arranged in the same manner as in fig. 4, and memory cell MCd (i, j) is arranged on the side of bit line bl (j) opposite to the side of bit line bl (j) on which memory cell MCu (i, j) is arranged.

In the above-described embodiment and modifications 1 and 2, the channel layers 13 of the transistors 10u (i, j) and 10d (i, j) arranged in the vertical direction are connected to the same side of the bit line bl (j). That is, the channel layer 13 of the transistor 10u (i, j) is connected to the channel layer 13 of the transistor 10d (i, j), and both are connected to either side surface (one of the 2 nd and 3 rd surfaces) of the bit line bl (j). However, in these examples, similarly to modification 3, the channel layers 13 of the transistors 10u (i, j) and 10d (i, j) may be connected to the respective opposite side surfaces of the bit line bl (j). That is, the channel layer 13 of the transistor 10u (i, j) is not directly connected to the channel layer 13 of the transistor 10d (i, j), the former being connected to either side surface (one of the 2 nd and 3 rd surfaces) of the bit line bl (j), and the latter being connected to the side surface (the other of the 2 nd and 3 rd surfaces) of the bit line bl (j) that faces the side surface.

(manufacturing method) next, a manufacturing method of the semiconductor memory device will be described. Fig. 9 is a flowchart showing an example of a manufacturing procedure of the semiconductor memory device. Fig. 10 to 14 are schematic cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment.

(1) Fabrication of lower memory cell MCd (step S11, fig. 10) memory cell MCd is fabricated. On the substrate 21, a capacitor 30d, a transistor 10d (a drain electrode 12, a word line WLd, a channel layer 13, a gate insulating layer 15), and interlayer insulating layers 22 to 24 are formed. At this stage, the source electrode 11 (bit line BL) is not formed. The process may be performed in the same manner as in the fabrication of a general semiconductor memory device, and thus, a detailed description thereof will be omitted. However, the axis C0 of the channel layer 13 is offset from the axis C1 of the bit line BL.

(2) Production of laminate (step S12, fig. 11) a laminate was produced. That is, as described below, the oxide layer 17, the bit line BL (source electrode 11), the interlayer insulating layer 25, the word line WLu (gate electrode 14), the interlayer insulating layer 26, and the drain electrode 12 are formed in this order on the interlayer insulating layer 24. At this time, (the pattern of) the oxide layer 17 is formed before the bit line BL (the source electrode 11), and as a result, the oxide layer 17 is disposed on the lower surface of the bit line BL.

(3) The formation of the through-hole H (step S13, fig. 12) forms the through-hole H (fig. 12) in the laminate. That is, a through hole H that penetrates the drain electrode 12, the interlayer insulating layer 26, the gate electrode 14, and the interlayer insulating layer 25 and reaches the bit line BL (source electrode 11) is formed. The axis C0 of the through hole H is along the side of the bit line BL (source electrode 11), and the side surface of the bit line BL is disposed in the through hole H. At this time, both the interlayer insulating layer 25 and the bit line BL are etched. However, the bit line BL is not actually etched because the magnitude of the etching rate of the interlayer insulating layer 25 is different from that of the bit line BL (the etching rate of the interlayer insulating layer 25 is large: the selectivity is large). As a result, the upper surface and one side surface of the bit line BL are exposed in the through hole H.

(4) Fabrication of the gate insulating layer 15 and the oxide layer 17 (low-resistance layer) (step S14, fig. 13) next, the gate insulating layer 15 is formed. The gate insulating layer 15 on the memory cell MCu side deposited at this time is connected to the gate insulating layer 15 on the memory cell MCd side. Further, an oxide layer 17 is formed. At this time, the oxide layer 17 is formed on the upper surface and the side surface of the bit line BL (source electrode 11). As a result, the oxide layers 17 are arranged on the upper and lower surfaces and the side surfaces of the bit line BL, together with the pattern of the oxide layer 17 formed in step S12. As described above, the oxide layer 17 prevents the formation of a high-resistance metal oxide layer on the interface of the channel layer 13 and the source electrode 11 (bit line BL). As a result, the resistance between the channel layer 13 and the source electrode 11 can be reduced.

(5) The channel layer 13 is formed (step S15, fig. 14) so that the through-hole H (fig. 14) is filled with the channel layer 13. The channel layer 13 on the memory cell MCu side deposited at this time is connected to the channel layer 13 on the memory cell MCd side.

(6) The capacitor 30u is fabricated (step S16, fig. 3) to form the capacitor 30u and the interlayer insulating layer 27. Through the above processes, the semiconductor memory device shown in fig. 1 to 4 is produced.

In the above, the memory cells MCu and MCd are arranged in the vertical direction. In the case of the structure in which the memory cells MCu and MCd are shifted in the XY plane as in modification 3, two opposing side surfaces of the bit line BL may be exposed, and the channel layers 13 of the respective memory cells MCu and MCd may be disposed on the two side surfaces.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof fall within the scope and spirit of the invention, and also fall within the scope of the invention described in the claims and equivalents thereof.