阅读说明：本技术 半导体器件 (Semiconductor device with a plurality of transistors ) 是由 金俊澈 洪相宇 于 2020-07-06 设计创作，主要内容包括：提供了一种半导体器件。所述半导体器件包括：基底,具有芯片区域和划道区域,划道区域具有在第一方向上延伸的第一边缘和在第二方向上延伸的第二边缘；第一绝缘夹层结构,位于划道区域上并且包括低k介电材料；第一导电结构,位于划道区域的与一个第一边缘相邻的部分上,并且均在竖直方向上延伸穿过第一绝缘夹层结构且在第一方向上延伸；第二绝缘夹层,位于第一绝缘夹层结构上并且包括其介电常数比第一绝缘夹层结构的介电常数大的材料；第一过孔,均在第一方向上延伸穿过第二绝缘夹层以接触一个第一导电结构；以及第一布线,公共地接触第一过孔的上表面。(A semiconductor device is provided. The semiconductor device includes: a substrate having a chip region and a scribe lane region, the scribe lane region having a first edge extending in a first direction and a second edge extending in a second direction; a first insulating sandwich structure located on the scribe lane region and comprising a low-k dielectric material; first conductive structures located on a portion of the scribe lane region adjacent to one of the first edges, and each extending in a vertical direction through the first insulating sandwich structure and extending in the first direction; a second insulating interlayer located on the first insulating interlayer structure and including a material having a dielectric constant greater than that of the first insulating interlayer structure; first vias each extending through the second insulating interlayer in a first direction to contact one of the first conductive structures; and a first wiring commonly contacting an upper surface of the first via.)

1. A semiconductor device, the semiconductor device comprising:

a substrate including a chip region and a scribe lane region surrounding the chip region, the scribe lane region having first edges opposite to each other and second edges opposite to each other, each first edge extending in a first direction, each second edge extending in a second direction crossing the first direction;

a first insulating sandwich structure located on the scribe lane region of the substrate, the first insulating sandwich structure comprising a low-k dielectric material;

first conductive structures on a portion of the scribe lane area of the substrate adjacent to one of the first edges, each of the first conductive structures extending through the first insulating interlayer structure in a vertical direction substantially perpendicular to the upper surface of the substrate and extending in the first direction;

a second insulating interlayer on the first insulating interlayer structure, the second insulating interlayer comprising a material having a dielectric constant greater than that of the first insulating interlayer structure;

first vias each extending in a first direction and through the second insulating interlayer to contact one of the first conductive structures; and

and a first wire commonly contacting an upper surface of the first via.

2. The semiconductor device according to claim 1, wherein each of the first conductive structures includes second wirings and second vias alternately and repeatedly stacked in a vertical direction, and the uppermost second wiring contacts the first via.

3. The semiconductor device according to claim 2, wherein an area of each second wiring is larger than an area of each second via in a plan view.

4. The semiconductor device according to claim 2, wherein each of the second wirings and each of the first and second vias has a bar shape extending in the first direction.

5. The semiconductor device according to claim 2, wherein each of the second wirings and each of the first and second vias has a net structure extending in the first direction.

6. The semiconductor device according to claim 2, wherein some of the second wirings and the second vias have a stripe shape extending in the first direction, and the other of the second wirings and the second vias have a net structure extending in the first direction.

7. The semiconductor device according to claim 1, wherein the first direction and the second direction are substantially perpendicular to each other, and the scribe lane region has a rectangular shape in a plan view.

8. The semiconductor device as set forth in claim 1,

wherein the first insulating sandwich structure includes a low-k dielectric layer and an etch stop layer alternately and repeatedly stacked in a vertical direction, and

wherein the low-k dielectric layer comprises porous silicon oxide, the etch stop layer comprises silicon carbonitride, and the second insulating interlayer comprises tetraethylorthosilicate.

9. The semiconductor device of claim 1, wherein the first conductive structure, the first via, and the first wire are part of a group of test elements.

10. The semiconductor device of claim 1, further comprising:

second conductive structures on a portion of the scribe lane area of the substrate adjacent to one second edge, each second conductive structure extending in a vertical direction through the first insulating interlayer structure and in a second direction;

second vias each extending in a second direction and through the second insulating interlayer to contact one of the second conductive structures; and

and a second wire commonly contacting an upper surface of the second via.

11. The semiconductor device as set forth in claim 1,

wherein the first insulating interlayer structure and the second insulating interlayer structure are further formed on the chip region of the substrate, and

wherein the semiconductor device further comprises:

a second conductive structure extending through the first insulating sandwich structure on the chip region of the substrate;

a second via extending through the second insulating interlayer on the chip region of the substrate; and

and a second wire on the second via hole on the chip region of the substrate.

12. The semiconductor device of claim 11, further comprising:

a first protective layer structure on the second insulating interlayer, the first protective layer structure covering the second wiring;

a redistribution layer on the first protective layer structure, the redistribution layer electrically connected to the second wiring; and

a second protective layer on the redistribution layer,

wherein at least a part of the first wiring is not covered with the first protective layer structure.

13. The semiconductor device according to claim 12, wherein the first protective layer structure comprises a first oxide layer, a nitride layer, and a second oxide layer sequentially stacked in a vertical direction.

14. The semiconductor device of claim 11, further comprising:

a bit line structure on the chip region of the substrate;

a contact plug adjacent to the bit line structure, the contact plug extending in a vertical direction; and

a capacitor located on the contact plug,

wherein the capacitor is electrically connected to the second conductive structure.

15. A semiconductor device, the semiconductor device comprising:

a substrate including a chip region and a scribe lane region surrounding the chip region, the scribe lane region having first edges opposite to each other and second edges opposite to each other, each first edge extending in a first direction, each second edge extending in a second direction crossing the first direction;

a contact plug located on the scribe line region of the substrate;

a conductive structure on the contact plug on a portion of the scribe lane region of the substrate adjacent to the one first edge, the conductive structure including first wirings and first vias alternately and repeatedly stacked in a vertical direction substantially perpendicular to an upper surface of the substrate; and

a second wiring commonly contacting an upper surface of the conductive structure,

wherein each first wire and each first via extends in a first direction.

16. The semiconductor device of claim 15, wherein the uppermost first via of each conductive structure is formed in the second insulating interlayer and the other first vias and first wires of each conductive structure are formed in the first insulating interlayer structure, and

wherein the material of the first insulating interlayer structure is softer than the material of the second insulating interlayer.

17. The semiconductor device as set forth in claim 16,

wherein the first insulating sandwich structure includes a low-k dielectric layer and an etch stop layer alternately and repeatedly stacked in a vertical direction, and

wherein the low-k dielectric layer comprises porous silicon oxide, the etch stop layer comprises silicon carbonitride, and the second insulating interlayer comprises tetraethylorthosilicate.

18. A semiconductor device, the semiconductor device comprising:

a substrate including a chip region and a scribe lane region surrounding the chip region, the scribe lane region having first edges opposite to each other and second edges opposite to each other, each first edge extending in a first direction, and each second edge extending in a second direction crossing the first direction, the substrate having first and second active patterns on the chip region and the scribe lane region, the first and second active patterns being defined by an isolation pattern on the substrate;

a gate structure disposed at an upper portion of the first active pattern;

a bit line structure on the chip region of the substrate;

a first contact plug on the first active pattern;

a capacitor on the first contact plug;

a second contact plug on the capacitor;

a third contact plug on the second active pattern;

a first insulating interlayer in which the second contact plug and the third contact plug are formed;

a second insulating interlayer structure on the first insulating interlayer;

conductive structures on a portion of the scribe lane area of the substrate adjacent to one of the first edges, each conductive structure extending through the second insulating interlayer structure in a vertical direction substantially perpendicular to the upper surface of the substrate and extending in the first direction;

a third insulating interlayer on the second insulating interlayer structure, the third insulating interlayer comprising a material having a dielectric constant greater than that of the second insulating interlayer structure;

first vias each extending in a first direction and through the third insulating interlayer to contact one of the conductive structures on the scribe area of the substrate; and

and a first wire commonly contacting an upper surface of the first via.

19. The semiconductor device of claim 18, wherein each conductive structure comprises second wires and second vias stacked alternately and repeatedly in a vertical direction, and the uppermost second wire contacts the first via.

20. The semiconductor device according to claim 19, wherein each of the second wirings and each of the first and second vias has a bar shape extending in the first direction.

Technical Field

Example embodiments of the present disclosure relate to semiconductor devices, and more particularly, to DRAM devices.

Background

A wafer (wafer) may include a plurality of chip regions and scribe regions surrounding them, and a Test Element Group (TEG), an align key, and the like for testing electrical characteristics of elements on the chip regions may be formed on the scribe regions. After the semiconductor chips are formed on the wafer, a dicing process for dicing the wafer and the structures thereon may be performed through the scribe lane regions, so that the semiconductor chips may be divided. Due to the structure such as the TEG on the scribe lane, the cutting process may not be easily performed.

Disclosure of Invention

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate, a first insulating interlayer structure, a first conductive structure, a second insulating interlayer, a first via, and a first wire. The substrate may include a chip region and a scribe lane region surrounding the chip region. The scribe lane region may have a first edge opposite to each other and a second edge opposite to each other. Each of the first edges may extend in a first direction, and each of the second edges may extend in a second direction crossing the first direction. The first insulating sandwich structure may be formed on a scribe lane region of the substrate and may include a low-k dielectric material. The first conductive structure may be formed on a portion of the scribe lane region of the substrate adjacent to one first edge. Each of the first conductive structures may extend through the first insulating sandwich structure in a vertical direction substantially perpendicular to the upper surface of the substrate, and may extend in the first direction. The second insulating interlayer may be formed on the first insulating interlayer structure, and may include a material having a dielectric constant greater than that of the first insulating interlayer structure. The first vias may each extend in a first direction and through the second insulating interlayer to contact one of the first conductive structures. The first wire may commonly contact an upper surface of the first via.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate, a contact plug, a conductive structure, and a second wiring. The substrate may include a chip region and a scribe lane region surrounding the chip region. The scribe lane region may have a first edge opposite to each other and a second edge opposite to each other. Each of the first edges may extend in a first direction, and each of the second edges may extend in a second direction crossing the first direction. The contact plug may be formed on a scribe lane region of the substrate. The conductive structure may be formed on the contact plug on a portion of the scribe lane region of the substrate adjacent to one of the first edges. The conductive structure may include first wirings and first vias alternately and repeatedly stacked in a vertical direction substantially perpendicular to the upper surface of the substrate. The second wiring may commonly contact an upper surface of the conductive structure. Each of the first wirings and each of the first vias may extend in the first direction.

According to example embodiments of the inventive concepts, a semiconductor device may include a substrate, a gate structure, a bit line structure, a first contact plug, a capacitor, a second contact plug, a third contact plug, a first insulating interlayer, a second insulating interlayer structure, a conductive structure, a third insulating interlayer, a first via, and a first wiring. The substrate may include a chip region and a scribe lane region surrounding the chip region. The scribe lane region may have a first edge opposite to each other and a second edge opposite to each other. Each of the first edges may extend in a first direction, and each of the second edges may extend in a second direction crossing the first direction. The substrate may have first and second active patterns on the chip region and the scribe lane region, and the first and second active patterns may be defined by an isolation pattern on the substrate. The gate structure may be disposed at an upper portion of the first active pattern. The bit line structure may be formed on a chip region of a substrate. The first contact plug may be formed on the first active pattern. The capacitor may be formed on the first contact plug. The second contact plug may be formed on the capacitor. The third contact plug may be formed on the second active pattern. The second contact plug and the third contact plug may be formed in the first insulating interlayer. The second insulating interlayer structure may be formed on the first insulating interlayer. The conductive structure may be formed on a portion of the scribe lane region of the substrate adjacent to one of the first edges. Each of the first conductive structures may extend through the second insulating interlayer structure in a vertical direction substantially perpendicular to the upper surface of the substrate and may extend in the first direction. A third insulating interlayer may be formed on the second insulating interlayer structure. The third insulating interlayer may include a material having a dielectric constant greater than that of the second insulating interlayer structure. The first vias may each extend in the first direction and through the third insulating interlayer to contact one of the conductive structures on the scribe area of the substrate. The first wire may commonly contact an upper surface of the first via.

In the method of manufacturing a semiconductor device according to example embodiments, the semiconductor chip and the TEG may be formed on a chip region and a scribe lane region of the wafer, respectively, and when the wafer is diced through the scribe lane region to separate the semiconductor chip, the dicing process may be guided by the conductive structure included in the TEG, and an impact generated by the dicing process may be prevented from being diffused to the semiconductor chip. Accordingly, the semiconductor chip may have improved electrical characteristics.

Drawings

Fig. 1 to 25 are plan and sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts.

Fig. 26 is a plan view illustrating a semiconductor device according to an example embodiment, and fig. 27 includes cross sections taken along lines a-a ', C-C ', and D-D ' of a region Y and a region Z corresponding to the plan views.

Detailed Description

The above and other aspects and features of the semiconductor device and the method of manufacturing the same according to example embodiments will become readily apparent from the following detailed description with reference to the accompanying drawings. It will be understood that, although the terms first, second, and/or third may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section, or a third element, component, region, layer or section without departing from the teachings of the inventive concept.

Fig. 1 to 25 are plan and sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments of the inventive concepts. Specifically, fig. 1 to 3, 5, 8, 12, 17, and 20 to 22 are plan views, and fig. 4, 6 and 7, 9 to 11, 13 to 16, 18 to 19, and 23 to 25 are sectional views.

Fig. 2 is an enlarged plan view of a region X of fig. 1, fig. 4, 6 and 7, 9 to 11, 13 to 16 and 18 include cross-sections taken along lines a-a ', B-B' and C-C 'of regions Y and Z of the corresponding plan views, and fig. 19 and 23 to 25 include cross-sections taken along lines a-a', C-C 'and D-D' of regions Y and Z of the corresponding plan views.

Hereinafter in the specification (not necessarily in the claims), two directions substantially parallel to the upper surface of the substrate 100 and substantially perpendicular to each other may be defined as a first direction and a second direction, respectively, and a direction substantially parallel to the upper surface of the substrate 100 and at an acute angle to each of the second direction and the first direction may be defined as a third direction.

Referring to fig. 1 and 2, the substrate 100 may include a first region I and a fourth region IV, and the first region I may include a second region II and a third region III.

Substrate 100 may be a wafer comprising silicon, germanium, silicon-germanium, or a group III-V compound semiconductor, such as GaP, GaAs, or GaSb. In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) wafer or a germanium-on-insulator (GOI) wafer.

The first region I of the substrate 100 may be a chip region in which a pattern for a semiconductor chip may be formed. In an example embodiment, the plurality of first regions I may be spaced apart from each other in each of the first and second directions. Each of the first regions I may include a second region II in which a memory cell may be formed and thus the second region II may be referred to as a cell region, and a third region III in which a peripheral circuit pattern for driving the memory cell may be formed and thus the third region III may be referred to as a peripheral circuit region.

The fourth region IV of the substrate 100 may be formed between the first regions I, and may be a scribe lane (or scribe line) region for cutting the pattern on the substrate 100 into semiconductor chips. In example embodiments, a TEG for testing electrical characteristics or faults of elements included in the semiconductor chip, an alignment key (alignment key) for alignment in a photolithography process, and the like may be formed on the fourth region IV of the substrate 100.

Hereinafter, a method of forming elements on a Y region included in the first region I of the substrate 100 will be illustrated with reference to fig. 3 to 18, and then a method of forming elements on a Y region and a Z region respectively included in the first region I and the fourth region IV of the substrate 100 will be illustrated with reference to fig. 19 to 25.

In example embodiments, the TEG on the fourth region IV of the substrate 100 may be formed to have substantially the same structure as that of some elements on the second region II or the third region III of the substrate 100. Therefore, when the elements are illustrated with reference to fig. 3 to 18, the structure on the fourth region IV of the substrate 100 will not be illustrated, and when the elements are illustrated with reference to fig. 19 to 25, it may be assumed that the structure on the third region III of the substrate 100 is also formed on the fourth region IV of the substrate 100.

Referring to fig. 3 and 4, first and second active patterns 105 and 108 may be formed on second and third regions II and III of the substrate 100, respectively, and an isolation pattern 110 may be formed on the substrate 100 to cover sidewalls of the first and second active patterns 105 and 108.

The first and second active patterns 105 and 108 may be formed by removing an upper portion of the substrate 100 to form a first recess. The plurality of first active patterns 105 may be spaced apart from each other in the first and second directions. Each of the first active patterns 105 may longitudinally extend in the third direction.

The isolation pattern 110 may be formed by: an isolation layer is formed on the substrate 100 to fill the first recess, and the isolation layer is planarized until upper surfaces of the first and second active patterns 105 and 108 may be exposed. In example embodiments, the planarization process may include a Chemical Mechanical Polishing (CMP) process and/or an etch-back process.

After forming an impurity region in the substrate 100 by performing, for example, an ion implantation process, the first active pattern 105 and the isolation pattern 110 on the second region II of the substrate 100 may be partially etched to form a second recess longitudinally extending in the first direction.

The first gate structure 160 may be formed in the second recess. The first gate structure 160 may include: a first gate insulating layer 130 on a surface of the first active pattern 105 exposed by the second recess; a first gate electrode 140 on the first gate insulating layer 130 to fill a lower portion of the second recess; and a first gate mask 150 on the first gate electrode 140 to fill an upper portion of the second recess. The first gate structures 160 may longitudinally extend in a first direction, and the plurality of first gate structures 160 may be spaced apart from each other in a second direction.

The first gate insulating layer 130 may be formed by performing a thermal oxidation process on a surface of the first active pattern 105 exposed by the second recess, and thus the first gate insulating layer 130 may include, for example, silicon oxide.

Referring to fig. 5 and 6, a thermal oxidation process may be performed on the upper surface of the second active pattern 108 on the third region III of the substrate 100 to form a second gate insulating layer 600, and an insulating layer structure 200 may be formed on the first active pattern 105 and the isolation pattern 110 on the second region II of the substrate 100.

In example embodiments, the insulating layer structure 200 may include a first insulating layer 170, a second insulating layer 180, and a third insulating layer 190, which are sequentially stacked. The first and third insulating layers 170 and 190 may include an oxide such as silicon oxide, and the second insulating layer 180 may include a nitride such as silicon nitride.

The first conductive layer 210 and the first mask 220 may be sequentially formed on the insulating layer structure 200, the second gate insulating layer 600, and the isolation pattern 110, and the first conductive layer 210 and the insulating layer structure 200 may be etched using the first mask 220 as an etch mask to form the first opening 230 exposing the first active pattern 105.

The first conductive layer 210 may include, for example, polysilicon doped with impurities, and the first mask 220 may include, for example, nitride of silicon nitride.

During the etching process, the first active pattern 105, the isolation pattern 110, and an upper portion of the first gate mask 150 exposed by the first opening 230 may also be etched to form a third recess. For example, the bottom of the first opening 230 may be referred to as a third recess. The bottom of the first opening 230 may be located at a lower vertical level than the top surfaces of the first active pattern 105, the isolation pattern 110, and the first gate mask 150.

In example embodiments, the first opening 230 may expose an upper surface of a central portion of each of the first active patterns 105 extending in the third direction, and thus a plurality of first openings 230 may be formed in the first and second directions.

The second conductive layer 240 may be formed to fill the first opening 230.

In example embodiments, the second conductive layer 240 may be formed by: a preliminary second conductive layer is formed on the first active pattern 105, the isolation pattern 110, the first gate mask 150, and the first mask 220 to fill the first opening 230, and an upper portion of the preliminary second conductive layer is removed through a CMP process and/or an etch-back process. Second conductive layer 240 may have an upper surface that is substantially coplanar with the upper surface of first conductive layer 210. Terms such as "same," "equal," "planar," or "coplanar," as used herein, when referring to an orientation, layout, position, shape, size, quantity, or other measure, do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measure, but are intended to encompass nearly the same orientation, layout, position, shape, size, quantity, or other measure within acceptable variations that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize such meaning unless context or other statement indicates otherwise.

In example embodiments, the plurality of second conductive layers 240 may be spaced apart from each other in the first and second directions on the second region II of the substrate 100. The second conductive layer 240 may comprise, for example, doped polysilicon, and may be incorporated into the first conductive layer 210. For example, a side surface of the second conductive layer 240 may contact a side surface of the first conductive layer 210.

Referring to fig. 7, after removing the first mask 220, a third conductive layer 250, a barrier layer 270, and a first metal layer 280 may be sequentially formed on the first conductive layer 210 and the second conductive layer 240.

In an example embodiment, the third conductive layer 250 may include substantially the same material as that of the first and second conductive layers 210 and 240. For example, third conductive layer 250 may comprise doped polysilicon, and thus, in some embodiments, third conductive layer 250 may be merged with first conductive layer 210 and second conductive layer 240.

A second mask (not shown) may be formed to cover a portion of the first metal layer 280 on the second region II of the substrate 100, a second gate mask 618 may be formed to partially cover a portion of the first metal layer 280 on the third region III of the substrate 100, and the first metal layer 280, the barrier layer 270, the third conductive layer 250, the first conductive layer 210, and the second gate insulating layer 600 may be sequentially etched using the second mask and the second gate mask 618 as an etch mask.

Accordingly, a second gate structure 628 may be formed on the third region III of the substrate 100. The second gate structure 628 may include a second gate insulating pattern 608, a second conductive pattern 218, a fifth conductive pattern 258, a second blocking pattern 278, a second metal pattern 288, and a second gate mask 618 sequentially stacked on the second active pattern 108. The second conductive pattern 218 and the fifth conductive pattern 258 may include the same material and thus may be combined with each other to form the second gate electrode 268.

The gate spacer 630 may be formed to cover sidewalls of the second gate structure 628, and impurities may be implanted into an upper portion of the second active pattern 108 adjacent to the second gate structure 628 to form the source/drain layer 109.

After removing the second mask, a first insulating interlayer may be formed on the second and third regions II and III of the substrate 100, and the first insulating interlayer may be planarized until the first metal layer 280 and the second gate mask 618 may be exposed to form a first insulating interlayer pattern 640 surrounding the second gate structure 628 and the gate spacer 630 on the third region III of the substrate 100. The first insulating interlayer pattern 640 may include an oxide such as silicon oxide.

A capping layer 290 may be formed on the first metal layer 280, the first interlayer insulating pattern 640, and the second gate mask 618. The capping layer 290 may comprise a nitride such as silicon nitride.

Referring to fig. 8 and 9, a portion of the capping layer 290 located on the second region II of the substrate 100 may be etched to form a first cap pattern 295, and the first metal layer 280, the barrier layer 270, the third conductive layer 250, the first and second conductive layers 210 and 240, and the third insulating layer 190 may be sequentially etched using the first cap pattern 295 as an etch mask.

In example embodiments, the first cover patterns 295 may longitudinally extend in the second direction, and a plurality of the first cover patterns 295 may be spaced apart from each other in the first direction on the second region II of the substrate 100. A portion of the capping layer 290 located on the third region III of the substrate 100 may remain as the second cap pattern 298.

Through an etching process, on the second region II of the substrate 100, the third conductive pattern 245, the fourth conductive pattern 255, the first barrier pattern 275, the first metal pattern 285, and the first cap pattern 295 may be sequentially stacked on the first active pattern 105, the isolation pattern 110, and the first gate mask 150 in the first opening 230, and the third insulating pattern 195, the first conductive pattern 215, the fourth conductive pattern 255, the first barrier pattern 275, the first metal pattern 285, and the first cap pattern 295 may be sequentially stacked on the second insulating layer 180 of the insulating layer structure 200 at the outer side of the first opening 230.

As shown above, the first, second, and third conductive layers 210, 240, and 250 may be merged with each other, and thus the sequentially stacked third and fourth conductive patterns 245 and 255 and the sequentially stacked first and fourth conductive patterns 215 and 255 may each form one first conductive structure 265. Hereinafter, the first conductive structure 265, the first barrier pattern 275, the first metal pattern 285, and the first cap pattern 295, which are sequentially stacked, may be referred to as a bit line structure 305.

In example embodiments, the bit line structures 305 may longitudinally extend in the second direction on the second region II of the substrate 100, and the plurality of bit line structures 305 may be spaced apart from each other in the first direction.

Referring to fig. 10, a first spacer layer may be formed on the upper surfaces of the first active pattern 105, the isolation pattern 110, and the first gate mask 150 exposed by the first opening 230, the sidewalls of the first opening 230, the second insulating layer 180, the first cap pattern 295, and the second cap pattern 298 to cover the bit line structure 305, and a fourth insulating layer and a fifth insulating layer may be sequentially formed on the first spacer layer.

The first spacer layer may also cover sidewalls of the third insulation pattern 195 between the second insulation layer 180 and the bit line structure 305, and the fifth insulation layer may fill the first opening 230.

The fourth insulating layer and the fifth insulating layer may be etched by an etching process. In example embodiments, the etching process may be performed by a wet etching process, and other portions of the fourth and fifth insulating layers except for the portion in the first opening 230 may be removed. Accordingly, most of the entire surface of the first spacer layer (e.g., the entire surface except for its portion in the first opening 230) may be exposed, and portions of the fourth and fifth insulating layers remaining in the first opening 230 may form the fourth and fifth insulating patterns 320 and 330, respectively.

A second spacer layer may be formed on the exposed surface of the first spacer layer and the fourth and fifth insulating patterns 320 and 330 in the first opening 230, and the second spacer layer may be anisotropically etched to form a second spacer 340 on the surface of the first spacer layer and the fourth and fifth insulating patterns 320 and 330 to cover sidewalls of the bit line structure 305.

A dry etching process may be performed using the first and second cover patterns 295 and 298 and the second spacers 340 as an etching mask to form a second opening 350 exposing the upper surface of the first active pattern 105. An upper surface of the isolation pattern 110 and an upper surface of the first gate mask 150 may be exposed by the second opening 350.

Through a dry etching process, portions of the first spacer layer on the upper surfaces of the first and second cover patterns 295 and 298 and the upper surface of the second insulating layer 180 may be removed, and thus the first spacer 315 covering the sidewalls of the bit line structure 305 may be formed. During the dry etching process, the first and second insulating layers 170 and 180 may be partially removed, so that the first and second insulating patterns 175 and 185 may remain under the bit line structure 305. The first, second, and third insulating patterns 175, 185, and 195 sequentially stacked under the bit line structure 305 may form an insulating pattern structure.

Referring to fig. 11, a third spacer layer may be formed on the upper surfaces of the first and second cover patterns 295 and 298, the outer sidewalls of the second spacer 340, portions of the upper surfaces of the fourth and fifth insulation patterns 320 and 330, and the upper surfaces of the first active patterns 105, the isolation patterns 110, and the first gate mask 150 exposed by the second opening 350, a third mask (not shown) covering the third region III of the substrate 100 may be formed on the third spacer layer, and the third spacer layer may be anisotropically etched to form third spacers 375 covering sidewalls of the bit line structure 305.

The third spacer layer may include nitride such as silicon nitride, and may be combined with the second cover pattern 298. In addition, the third mask may include a material having an etch selectivity with respect to the third spacer layer, for example, a photoresist pattern.

The first spacer 315, the second spacer 340, and the third spacer 375 sequentially stacked from the sidewall of the bit line structure 305 on the second region II of the substrate 100 in a horizontal direction substantially parallel to the upper surface of the substrate 100 may be referred to as a preliminary spacer structure.

The third mask may be removed by, for example, an ashing process and/or a stripping process, and an upper portion of the first active pattern 105 may be removed by an etching process to form the fourth recess 390 connected to the second opening 350.

The lower contact plug layer 400 may be formed to fill the second opening 350 and the fourth recess 390 on the second region II of the substrate 100, and the lower contact plug layer 400 may be planarized until upper surfaces of the first and second cap patterns 295 and 298 may be exposed.

In example embodiments, the lower contact plug layer 400 may longitudinally extend in the second direction, and the plurality of lower contact plug layers 400 may be formed to be spaced apart from each other by the bitline structure 305 in the first direction.

Referring to fig. 12 and 13, a fourth mask (not shown) including third openings, each of which may extend in the first direction and be spaced apart from each other in the second direction on the second region II of the substrate 100, may be formed on the first cap pattern 295 and the lower contact plug layer 400, and the lower contact plug layer 400 may be etched using the fourth mask as an etch mask.

In example embodiments, each of the third openings may overlap the first gate structure 160 in a vertical direction substantially perpendicular to the upper surface of the substrate 100. Through the etching process, a fourth opening may be formed to expose an upper surface of the first gate mask 150 of the first gate structure 160 between the bit line structures 305 on the second region II of the substrate 100.

After removing the fourth mask, a third cover pattern 410 may be formed on the second region II of the substrate 100 to fill the fourth opening. The third cap pattern 410 may include nitride such as silicon nitride. In example embodiments, the third cover patterns 410 may extend in the first direction between the bit line structures 305, and a plurality of third cover patterns 410 may be formed in the second direction.

Accordingly, the lower contact plug layer 400 extending in the second direction between the bit line structures 305 may be divided into a plurality of lower contact plugs 405 spaced apart from each other in the second direction by the third cover pattern 410 on the second region II of the substrate 100.

Referring to fig. 14, an upper portion of the lower contact plug 405 may be removed to expose an upper portion of the preliminary spacer structure on the sidewall of the bit line structure 305, and upper portions of the second and third spacers 340 and 375 of the exposed preliminary spacer structure may be removed.

The upper portion of the lower contact plug 405 may be further removed. Accordingly, the upper surface of the lower contact plug 405 may be located at a lower vertical level than the uppermost surfaces of the second and third spacers 340 and 375.

A fourth spacer layer may be formed on the bit line structure 305, the preliminary spacer structure, the second and third cap patterns 298 and 410, and the lower contact plug 405, and may be anisotropically etched, so that the fourth spacer 425 may be formed to cover the first, second and third spacers 315, 340 and 375 on each of opposite sidewalls of the bit line structure 305 in the first direction, and an upper surface of the lower contact plug 405 may be exposed.

A metal silicide pattern 435 may be formed on the exposed upper surface of the lower contact plug 405. An upper surface of the metal silicide pattern 435 may be located at a lower vertical level than uppermost surfaces of the second and third spacers 340 and 375. In an example embodiment, the metal silicide pattern 435 may be formed by: a second metal layer is formed on the first, second, and third cap patterns 295, 298, and 410, the fourth spacer 425, and the lower contact plug 405, heat-treated, and an unreacted portion of the second metal layer is removed. The metal silicide pattern 435 may include, for example, cobalt silicide, nickel silicide, titanium silicide, or the like.

Referring to fig. 15, a first sacrificial layer may be formed on the first, second, and third cap patterns 295, 298, and 410, the metal silicide pattern 435, and the lower contact plug 405, the first sacrificial layer may be planarized until upper surfaces of the first, second, and third cap patterns 295, 298, and 410 may be exposed, and a first hole may be formed on the third region III of the substrate 100.

The first sacrificial layer may include, for example, silicon on hard mask (SOH), an Amorphous Carbon Layer (ACL), or the like.

A first hole may vertically extend through the second cover pattern 298 and the first insulating interlayer pattern 640 to expose an upper surface of the source/drain layer 109 on the third region III of the substrate 100.

After removing the first sacrificial layer, an upper contact plug layer 450 may be formed on the first, second, and third cap patterns 295, 298, and 410, the first, second, and third and fourth spacers 315, 340, 375, and 425, the metal silicide pattern 435, the lower contact plug 405, and the source/drain layer 109, and the upper contact plug layer 450 may be planarized.

In example embodiments, the upper surface of the upper contact plug layer 450 may be located at a higher vertical level than the upper surfaces of the first, second, and third cover patterns 295, 298, and 410.

Referring to fig. 16, a second hole 470 may be formed on the second region II of the substrate 100, and the upper contact plug layer 450 may be patterned on the third region III of the substrate 100.

The second hole 470 may be formed by removing an upper portion of the upper contact plug layer 450, an upper portion of the first cap pattern 295, and upper portions of the first, third, and fourth spacers 315, 375, and 425. The second hole 470 may expose an upper surface of the second spacer 340.

When the second hole 470 is formed, the upper contact plug layer 450 may be divided into a plurality of upper contact plugs 455 on the second region II of the substrate 100. In example embodiments, the plurality of upper contact plugs 455 may be formed in the first direction and the second direction, and may be arranged in a honeycomb pattern in a plan view. Each of the upper contact plugs 455 may have a circular, elliptical, or polygonal shape in plan view.

The lower contact plug 405, the metal silicide pattern 435, and the upper contact plug 455 sequentially stacked on the second region II of the substrate 100 may form a contact plug structure.

The upper contact plug layer 450 may be patterned on the third region III of the substrate 100 to form a first contact plug 458, and the first contact plug 458 may be electrically connected to the source/drain layer 109.

The exposed second spacers 340 may be removed to form air gaps 345 connected to the second holes 470. The second spacers 340 may be removed by, for example, a wet etching process.

In example embodiments, not only a portion of the second spacer 340 directly exposed by the second hole 470 but also other portions of the second spacer 340 in parallel with the directly exposed portion thereof in a horizontal direction may be removed. For example, in addition to the portion of the second spacer 340 exposed by the second hole 470 and not covered by the upper contact plug 455, a portion of the second spacer 340 adjacent to the exposed portion in the second direction to be covered by the third cap pattern 410 and a portion of the second spacer 340 adjacent to the exposed portion in the second direction to be covered by the upper contact plug 455 may be removed.

The second insulating interlayer 480 and the third insulating interlayer 490 may be sequentially stacked to fill a space between the second hole 470 on the second region II of the substrate 100 and the first contact plug 458 on the third region III of the substrate 100. The second insulating interlayer 480 and the third insulating interlayer 490 may also be sequentially stacked on the third cap pattern 410.

The second insulating interlayer 480 may include a material having a low gap filling property, and thus may not fill the air gap 345 under the second hole 470. The air gap 345 may also be referred to as an air spacer 345 and may form a spacer structure with the first, third, and fourth spacers 315, 375, 425. For example, the air gap 345 may be a spacer including air. The term "air" as discussed herein may refer to atmospheric air or other gases that may be present during the manufacturing process.

Referring to fig. 17 and 18, the capacitor 540 may be formed such that the capacitor 540 contacts the upper surface of the upper contact plug 455.

Specifically, the first etch stop layer 500 and the molding layer (not shown) may be sequentially formed on the upper contact plug 455, the second insulating interlayer 480, the third insulating interlayer 490, and the first contact plug 458, and the first etch stop layer 500 and the molding layer may be partially etched to form a fifth opening partially exposing the upper surface of the upper contact plug 455.

A lower electrode layer (not shown) may be formed on sidewalls of the fifth opening, the exposed upper surface of the upper contact plug 455, and the molding layer, and a second sacrificial layer (not shown) may be formed on the lower electrode layer to fill the fifth opening. The lower electrode layer and the second sacrificial layer may be planarized until an upper surface of the molding layer may be exposed to divide the lower electrode layer. The second sacrificial layer and the molding layer may be removed by, for example, a wet etching process, and thus the lower electrode 510 having a cylindrical shape may be formed (in a plan view) on the exposed upper surface of the upper contact plug 455. Alternatively, the lower electrode 510 may have a pillar shape filling the fifth opening.

A dielectric layer 520 may be formed on surfaces of the lower electrode 510 and the first etch stop layer 500, and an upper electrode 530 may be formed on the dielectric layer 520, so that a capacitor 540 including the lower electrode 510, the dielectric layer 520, and the upper electrode 530 may be formed.

A fourth insulating interlayer 550 may be formed to cover the capacitor 540. A fourth insulating interlayer 550 may be formed on the second and third regions II and III of the substrate 100. The fourth insulating interlayer 550 may include an oxide such as silicon oxide.

As mentioned above, hereinafter, it is assumed that elements on the third region III of the substrate 100 have also been formed on the fourth region IV of the substrate 100, and structures that may be formed on the second region II, the third region III, and the fourth region IV of the substrate 100 will be shown.

Referring to fig. 19, a fifth insulating interlayer 700 may be formed on the fourth insulating interlayer 550. The second contact plug 712 may be formed to vertically extend through the fourth insulating interlayer 550 and the fifth insulating interlayer 700 to contact the capacitor 540 on the second region II of the substrate 100, the third contact plug 714 may be formed to vertically extend through the fourth insulating interlayer 550 and the fifth insulating interlayer 700 to contact the first contact plug 458 on the third region III of the substrate 100, and the fourth contact plug 716 may be formed to vertically extend through the fourth insulating interlayer 550 and the fifth insulating interlayer 700 to contact the first contact plug 458 on the fourth region IV of the substrate 100. The fifth insulating interlayer 700 may include silicon oxide such as tetraethyl orthosilicate (TEOS).

A sixth insulating interlayer 720 may be formed on the fifth insulating interlayer 700 and the second, third, and fourth contact plugs 712, 714, and 716, and first, second, and third routing lines 722, 724, and 726 may be formed to vertically extend through the sixth insulating interlayer 720 to contact the second, third, and fourth contact plugs 712, 714, and 716, respectively.

A second etch stop layer 730 and a seventh insulating interlayer 740 may be sequentially formed on the sixth insulating interlayer 720 and the first, second, and third wirings 722, 724, and 726. The first, second, and third vias 751, 753, and 755 may be formed to vertically extend through the lower portion of the seventh insulating interlayer 740 and the second etch stop layer 730 to contact the first, second, and third wirings 722, 724, and 726, respectively, and the fourth, fifth, and sixth wirings 752, 754, and 756 may be formed to extend through the upper portion of the seventh insulating interlayer 740 to contact the first, second, and third vias 751, 753, and 755, respectively. In example embodiments, the first, second, and third vias 751, 753, and 755, and the fourth, fifth, and sixth wires 752, 754, and 756 may be simultaneously formed through a dual damascene process, however, the inventive concept may not be limited thereto, and may each be independently formed through a single damascene process.

A third etch stop layer 760 and an eighth insulating interlayer 770 may be sequentially formed on the seventh insulating interlayer 740 and the fourth, fifth and sixth wirings 752, 754 and 756. The fourth, fifth, and sixth vias 781, 783, and 785 may be formed to vertically extend through the lower portion of the eighth interlayer insulating layer 770 and the third etch stop layer 760 to contact the fourth, fifth, and sixth wirings 752, 754, and 756, respectively, and the seventh, eighth, and ninth wirings 782, 784, and 786 may be formed to extend through the upper portion of the eighth interlayer insulating layer 770 to contact the fourth, fifth, and sixth vias 781, 783, and 785, respectively.

A fourth etch stop layer 790 and a ninth insulating interlayer 800 may be sequentially formed on the eighth insulating interlayer 770 and the seventh wiring 782, the eighth wiring 784 and the ninth wiring 786. Seventh, eighth, and ninth vias 811, 813, and 815 may be formed to vertically extend through the fourth etch stop layer 790 and the ninth interlayer insulation layer 800 to contact the seventh, eighth, and ninth wirings 782, 784, and 786, respectively, and tenth, eleventh, and twelfth wirings 822, 824, and 826 may be formed on the ninth interlayer insulation layer 800 to contact the seventh, eighth, and ninth vias 811, 813, and 815, respectively.

In an example embodiment, each of the sixth, seventh and eighth insulating interlayers 720, 740 and 770 may include a low-k dielectric material, for example, silicon oxide doped with fluorine or carbon, porous silicon oxide (SiOCH), spin-on organic polymer, inorganic polymer such as HSSQ, MSSQ, or the like, each of the second, third and fourth etch stop layers 730, 760 and 790 may include, for example, silicon carbonitride (SiCN), and the ninth insulating interlayer 800 may include, for example, oxide of TEOS. In some embodiments, the second, third, and fourth etch stop layers 730, 760, and 790 and the sixth, seventh, and eighth insulating interlayers 720, 740, and 770 may be referred to as an insulating interlayer structure, and the ninth insulating interlayer 800 may include a material having a dielectric constant greater than that of the insulating interlayer structure.

Fig. 20 is a plan view illustrating a layout of wires and vias in region Z according to an example embodiment.

With further reference to fig. 19 and 20, each of the third wiring 726, the sixth wiring 756, and the ninth wiring 786 and each of the third via 755, the sixth via 785, and the ninth via 815 may have a bar shape extending longitudinally in the second direction when viewed in a plan view, and the twelfth wiring 826 thereon may have a polygonal, circular, or elliptical shape such as a rectangle. Fig. 20 shows a twelfth wiring 826 having a rectangular shape.

As described above, the TEG, the align key, and the like may be formed on the fourth region IV of the substrate 100, and pads (or referred to as "pads") of the TEG may be formed on the region Z of the fourth region IV of the substrate 100. The twelfth wiring 826, which may be formed at the highest level on the region Z, may have a polygonal shape or a circular shape so that a probe for applying a voltage to the TEG may easily contact the TEG. The third, sixth, and ninth wirings 726, 756, and 786 under the twelfth wiring 826 may not directly contact the probes, and thus the third, sixth, and ninth wirings 726, 756, and 786 may not have a polygonal shape or a circular shape, but may have a stripe shape extending in the second direction.

Each of the third, sixth, and ninth vias 755, 785, and 815, which may be formed between the third, sixth, ninth, and twelfth wirings 726, 756, 786, and 826, may also have a bar shape extending in the second direction.

In an example embodiment, the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755, the sixth via 785, and the ninth via 815 may be stacked in a vertical direction, and thus the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755, the sixth via 785, and the ninth via 815 may form a second conductive structure extending in the second direction and in the vertical direction. Each of the second conductive structures may be substantially perpendicular to the upper surface of the substrate 100. For example, when viewed in cross section, a vertical central axis of each of the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755 and the sixth via 785 may extend in a direction substantially perpendicular to the top surface of the substrate 100. In some embodiments, the vertical central axes of each of the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755 and the sixth via 785 may be substantially aligned with each other when viewed in cross-section.

In some embodiments, the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755 and the sixth via 785 may be referred to as conductive structures. For example, each of the conductive structures formed on a portion of the scribe lane area adjacent to the first edge E1 (see fig. 26) of the substrate 100 may include a third wire 726, sixth wires 756 and ninth wires 786, and third and sixth vias 755 and 785. Each ninth via 815 may be formed to extend through the ninth interlayer insulating layer 800 to contact a corresponding one of the conductive structures including the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785, and the twelfth wiring 826 may be commonly contacted to the upper surface of the ninth via 815 to be formed on the upper surfaces of the ninth interlayer insulating layer 800 and the ninth via 815.

Each of the third wiring 726, the sixth wiring 756, the ninth wiring 786, and the twelfth wiring 826 may have an area larger than an area of each of the third via 755, the sixth via 785, and the ninth via 815 when viewed in a plan view; however, the inventive concept may not be limited thereto.

Fig. 21 and 22 are plan views illustrating layouts of wirings and vias according to example embodiments.

Referring to fig. 21, each of the third, sixth, and ninth wirings 726, 756, and 786 and the third, sixth, and ninth vias 755, 785, and 815 may have a mesh structure extending in the second direction.

The mesh structure may include first extension portions connected to each other by second extension portions, each of the first extension portions may extend longitudinally in the second direction, each of the second extension portions may extend longitudinally in the first direction, and in the first direction, the material may not move through the mesh structure from one side of the mesh structure to the other side thereof.

Referring to fig. 22, some of the third, sixth, and ninth wirings 726, 756, and 786 and the third, sixth, and ninth vias 755, 785, and 815 may have a bar shape extending in the second direction, and others of the third, sixth, and ninth wirings 726, 756, and 786 and the third, sixth, and ninth vias 755, 785, and 815 may have a mesh structure extending in the second direction. Fig. 22 shows that each of the wirings and the vias located at both ends has a bar shape in the first direction, and each of the wirings and the vias located in the middle has a mesh structure.

Referring to fig. 23, a first protective layer structure may be formed on the tenth, eleventh, and twelfth wires 822, 824, and 826 and the ninth interlayer insulating layer 800, and a tenth via 860 may be formed to vertically extend through the first protective layer structure to contact the tenth, eleventh, and twelfth wires 822, 824, and 826. A redistribution layer 870 may be formed on the first protective layer, and the redistribution layer 870 may contact an upper surface of the tenth via 860.

In example embodiments, the first protective layer structure may include a first oxide layer 830, a nitride layer 840, and a second oxide layer 850 sequentially stacked. The redistribution layer 870 may contact a top surface of the second oxide layer 850.

The redistribution layer 870 may be formed on the second and third regions II and III of the substrate 100, and the redistribution layer 870 may be formed only on an edge portion of the fourth region IV of the substrate 100. The redistribution layer 870 may include, for example, a seed layer (seed layer) and a third metal layer sequentially stacked. The seed layer may include a metal such as copper, ruthenium, nickel, gold, tungsten, etc., and may be formed by, for example, Physical Vapor Deposition (PVD). The third metal layer may be formed by a plating process using a plating solution including an electrolyte solution containing metal ions (e.g., copper ions, ruthenium ions, nickel ions, gold ions, tungsten ions, etc.).

Referring to fig. 24, a second protective layer 880 may be formed on the redistribution layer 870 and the second oxide layer 850, and a portion of the second protective layer 880 located on the fourth region IV of the substrate 100 and a portion of the first protective layer structure located under the second protective layer 880 may be removed to form a sixth opening 890 exposing an upper surface of the twelfth wiring 826.

The second protective layer 880 may include a photosensitive organic material such as polyimide, and thus may include a thermosetting organic polymer and a photosensitive material. In example embodiments, the second protective layer 880 may be formed by a spin coating process, and the second protective layer 880 may be cured by a heat treatment.

The semiconductor chips may be respectively formed on the first region I of the substrate 100 through the above processes.

Referring to fig. 25, a cutting process or a dicing process may be performed such that the semiconductor chips on the first region I of the substrate 100, respectively, may be spaced apart from each other, and thus a seventh opening 900 may be formed on the fourth region IV of the substrate 100.

The cutting process may include, for example, a laser cutting process, a blade cutting process, etc., and a grinding process for removing the backside portion of the substrate 100 may also be performed before or after the cutting process.

In example embodiments, on the fourth region IV of the substrate 100, seventh openings 900 formed through a cutting process may be formed between second conductive structures adjacent in the first direction, and each of the second conductive structures may extend in the second direction. Therefore, the impact generated by the cutting process can be absorbed by the second conductive structure without being diffused outward.

Specifically, when the cutting process is performed, a cutting force is not diffused in a vertical direction but diffused in a horizontal direction in the sixth, seventh and eighth insulating interlayers 720, 740 and 770, and the sixth, seventh and eighth insulating interlayers 720, 740 and 770 include a low-k dielectric material, which may be relatively soft, between the fifth and ninth insulating interlayers 700 and 800 including a relatively hard material. However, in example embodiments, the second conductive structures in the sixth, seventh and eighth insulating interlayers 720, 740 and 770 may extend in the vertical direction and the second direction, and thus the seventh opening 900 may be guided by the second conductive structures to be formed between the second conductive structures in the vertical direction.

Further, unlike on the first region I of the substrate 100, the first protective layer structure may not remain on the portion of the twelfth wiring 826 where the seventh opening 900 is formed, and thus the impact of the cutting force may not be diffused toward the first region I of the substrate 100 through the first protective layer structure.

Accordingly, impact diffusion to the first region I of the substrate 100 may be minimized during the dicing process on the fourth region IV of the substrate 100, and thus the semiconductor chip on the first region I of the substrate 100 may have improved characteristics, which are shown in fig. 26 and 27.

Fig. 26 is a plan view illustrating a semiconductor device according to an example embodiment, and fig. 27 includes cross sections taken along lines a-a ', C-C ', and D-D ' of a region Y and a region Z corresponding to the plan views.

Referring to fig. 26, 27, and 20, a fourth region IV of the substrate 100 surrounding the first region I of the substrate 100 may include first edges E1 opposite to each other in the first direction and second edges E2 opposite to each other in the second direction, each of the first edges E1 may extend in the second direction, and each of the second edges E2 may extend in the first direction. The outer contour of the fourth area IV of the substrate 100 may have a rectangular shape if the first direction and the second direction are substantially perpendicular to each other. Alternatively, if the first and second directions are not perpendicular to each other, the outer contour of the fourth area IV of the substrate 100 may have a parallelogram shape.

A portion of the TEG may remain on the fourth region IV of the substrate 100, and in particular, at least a portion of the pad of the TEG may remain on a portion of the region Z adjacent to the first edge E1.

The pad of the TEG may include a second conductive structure having a third wiring 726, a third via 755, a sixth wiring 756, a sixth via 785, a ninth wiring 786, and a ninth via 815, which are sequentially stacked in a vertical direction, and a twelfth wiring 826 commonly contacting upper surfaces of the plurality of second conductive structures.

In example embodiments, the second conductive structure may extend in a direction (i.e., a second direction) substantially parallel to the extending direction of the first edge E1, and the plurality of second conductive structures may be formed to be spaced apart from each other in the first direction. The third wire 726, the third via 755, the sixth wire 756, the sixth via 785 and the ninth wire 786 included in the second conductive structure may be formed in the sixth insulating interlayer 720, the seventh insulating interlayer 740 and the eighth insulating interlayer 770 including a low-k dielectric material, and the ninth via 815 included in the second conductive structure may be formed in the ninth insulating interlayer 800 including silicon oxide such as TEOS.

Up to now, the structure on the region Z adjacent to the first edge E1 in the fourth region IV of the substrate 100 surrounding the first region I of the substrate 100 has been mainly shown, however, a similar structure may also be formed on a region (e.g., region W) adjacent to the second edge E2 in the fourth region IV of the substrate 100.

For example, in the region W formed adjacent to the second edge E2, the third, sixth, and ninth wirings 726, 756, and 786, and the third and sixth vias 755 and 785 may be formed and may be referred to as a conductive structure. For example, each of the conductive structures formed on the portion of the scribe lane area of the substrate 100 adjacent to the second edge E2 may include a third wire 726, a sixth wire 756, and a ninth wire 786, and a third via 755 and a sixth via 785. Each conductive structure may be substantially perpendicular to the upper surface of the substrate 100. For example, when viewed in cross section, a vertical central axis of each of the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755 and the sixth via 785 may extend in a direction substantially perpendicular to the top surface of the substrate 100. In some embodiments, the vertical central axes of each of the third wire 726, the sixth wire 756, and the ninth wire 786, and the third via 755 and the sixth via 785 may be substantially aligned with each other when viewed in cross-section. Each ninth via 815 may be formed to extend through the ninth interlayer insulating layer 800 to contact a corresponding one of conductive structures including the third wiring 726, the sixth wiring 756, and the ninth wiring 786, and the third via 755 and the sixth via 785, and the twelfth wiring 826 may be commonly contacted to the upper surface of the ninth via 815 to be formed on the upper surface of the ninth interlayer insulating layer 800 and the upper surface of the ninth via 815.

Specifically, in the example of the area W, the seventh opening 900 may be formed to extend in a direction substantially parallel to the extending direction of the second edge E2. For example, the seventh opening 900 may be formed to extend in the first direction between the second conductive structures, and each of the second conductive structures may extend in the first direction through a cutting process or a dicing process. Accordingly, the cutting process may be guided by the second conductive structure extending in the first direction, and thus the seventh opening 900 may be formed not in the horizontal direction but in the vertical direction. Therefore, the impact generated by the dicing process may be blocked by the second conductive structure so as not to diffuse into the inside of the semiconductor chip.

While the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept as set forth by the following claims.