阅读说明：本技术 半导体元件及其制备方法 (Semiconductor element and method for manufacturing the same ) 是由 黄至伟 于 2020-07-20 设计创作，主要内容包括：本公开提供一种半导体元件及其制备方法。该半导体元件具有一基底；多个电容接触点,位在该基底上；所述多个电容接触点的至少其一具有一颈部以及一头部,该头部位在该颈部上,其中该头部的一上宽度大于该颈部的一上宽度；多个位元线接触点以及多个位元线,所述多个位元线接触点位在该基底上,所述多个位元线位在所述多个位元线接触点上,其中所述多个位元线的至少其一为一波形线,该波形线在二相邻电容接触点之间延伸；以及一电容结构,位在该头部上。(The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device has a substrate; a plurality of capacitive contacts on the substrate; at least one of the plurality of capacitive contacts has a neck and a head, the head is on the neck, wherein an upper width of the head is greater than an upper width of the neck; a plurality of bit line contacts on the substrate and a plurality of bit lines on the plurality of bit line contacts, wherein at least one of the plurality of bit lines is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure located on the head.)

1. A semiconductor component, comprising:

a substrate;

a plurality of capacitive contacts on the substrate, at least one of the plurality of capacitive contacts having a neck and a head, the head being on the neck, wherein an upper width of the head is greater than an upper width of the neck;

a plurality of bit line contacts on the substrate and a plurality of bit lines on the plurality of bit line contacts, wherein at least one of the plurality of bit lines is a wavy line extending between two adjacent capacitor contacts; and

a capacitor structure located on the head.

2. The semiconductor device as defined in claim 1, wherein the upper width of the head portion is greater than a lower width of the head portion.

3. The semiconductor device of claim 1, wherein the upper width of the neck portion is substantially the same as a lower width of the head portion.

4. The semiconductor device as defined in claim 1, wherein the head portion has an arcuate sidewall.

5. The semiconductor device of claim 1, wherein the head portion has a tapered profile.

6. The semiconductor device of claim 1, further comprising a conductive feature comprising tungsten, the conductive feature being on the substrate.

7. The semiconductor device of claim 6, further comprising a cladding layer comprising tungsten nitride, the cladding layer being on a top surface of the conductive feature.

8. The semiconductor device as defined in claim 6, wherein the conductive member is located under the capacitor structure.

9. The semiconductor device as defined in claim 6, wherein the conductive member is located on the capacitor structure.

10. The semiconductor device of claim 6, further comprising a plurality of word lines in said substrate and a doped region between a pair of said plurality of word lines, wherein said conductive feature is on said doped region.

11. A method for manufacturing a semiconductor device includes:

providing a substrate;

forming a plurality of bit line contacts on a first portion of the substrate;

forming a plurality of bit lines on the plurality of bit line contacts;

forming a capacitor contact point on a second portion of the substrate, the capacitor contact point having a neck portion and a head portion on the neck portion, wherein an upper width of the head portion is greater than an upper portion of the neck portion; and

forming a capacitor structure on the head;

wherein at least one of the bit lines is a wavy line extending between two adjacent capacitive contacts.

12. The method of claim 11, wherein forming a capacitive contact comprises:

forming a contact hole, wherein the contact hole is a dielectric stack, the dielectric stack is provided with a first layer and a second layer, and the second layer is positioned on the first layer;

removing a portion of the second layer surrounding the contact hole to form a transfer hole, the transfer hole having a narrow portion in the first layer and a wide portion in the second layer; and

filling a conductive material into the transfer hole.

13. The method of claim 12, wherein the contact hole is integrally formed with a bitline trench in the second layer.

14. The manufacturing method of a semiconductor element according to claim 13, further comprising: filling the bit line trench and a lower portion of the contact hole with a filling material.

15. The method of claim 14, wherein removing a portion of the second layer surrounding the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.

16. The manufacturing method of a semiconductor element according to claim 11, further comprising:

forming a conductive feature comprising tungsten on the substrate; and

a cladding layer comprising tungsten nitride is formed on a top surface of the conductive feature.

17. The manufacturing method of a semiconductor element according to claim 16, further comprising: cleaning the conductive feature prior to forming a coating comprising tungsten nitride on a top surface of the conductive feature, wherein cleaning the conductive feature comprises applying a reducing agent to the top surface of the conductive feature, the reducing agent being titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

18. The method of manufacturing a semiconductor device according to claim 16, further comprising forming a plurality of capacitor structures on the capacitor contact.

19. The method according to claim 18, wherein the conductive member is disposed under the plurality of capacitor structures.

20. The method for manufacturing a semiconductor device according to claim 18, wherein the conductive member is located on the plurality of capacitor structures.

Technical Field

The present disclosure claims priority and benefit of 2019/09/13 application U.S. official application No. 16/570,750, the contents of which are incorporated herein by reference in their entirety.

The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, to a semiconductor device having a clad layer and a method for manufacturing the semiconductor device having the clad layer.

Background

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually becoming smaller to meet the increasing demand for computing power. However, during the process of scaling down, various problems are added and the final electronic characteristics, quality and yield are affected. Thus, there is a continuing challenge to achieve improved quality, yield, and reliability.

The above description of "prior art" merely provides background and is not an admission that the above description of "prior art" discloses the subject matter of the present disclosure, does not constitute prior art to the present disclosure, and any description of "prior art" above should not be taken as an admission that it forms part of the present disclosure.

Disclosure of Invention

An embodiment of the present disclosure provides a semiconductor device, including: a substrate; a plurality of capacitive contacts on the substrate, at least one of the plurality of capacitive contacts having a neck and a head, the head being on the neck, wherein an upper width of the head is greater than an upper width of the neck; a plurality of bit line contacts on the substrate and a plurality of bit lines on the plurality of bit line contacts, wherein at least one of the plurality of bit lines is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure located on the head.

In some embodiments of the present disclosure, the upper width of the head is greater than a lower width of the head.

In some embodiments of the present disclosure, the upper width of the neck is substantially the same as a lower width of the head.

In some embodiments of the present disclosure, the head has an arcuate sidewall.

In some embodiments of the present disclosure, the head has a tapered profile.

In some embodiments of the present disclosure, the semiconductor device further includes a conductive feature comprising tungsten, the conductive feature being on the substrate.

In some embodiments of the present disclosure, the semiconductor device further comprises a cladding layer comprising tungsten nitride, the cladding layer being on a top surface of the conductive feature.

In some embodiments of the present disclosure, the conductive member is located under the capacitive structure.

In some embodiments of the present disclosure, the conductive member is located on the capacitive structure.

In some embodiments of the present disclosure, the semiconductor device further includes a plurality of word lines in the substrate and a doped region between a pair of the plurality of word lines, wherein the conductive feature is on the doped region.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method comprises the following steps: providing a substrate; forming a plurality of bit line contacts on a first portion of the substrate; forming a plurality of bit lines on the plurality of bit line contacts; forming a capacitor contact point on a second portion of the substrate, the capacitor contact point having a neck portion and a head portion on the neck portion, wherein an upper width of the head portion is greater than an upper portion of the neck portion; and forming a capacitor structure on the head; wherein at least one of the bit lines is a wavy line extending between two adjacent capacitor contacts.

In some embodiments of the present disclosure, forming a capacitive contact comprises: forming a contact hole, wherein the contact hole is a dielectric stack, the dielectric stack is provided with a first layer and a second layer, and the second layer is positioned on the first layer; removing a portion of the second layer surrounding the contact hole to form a transfer hole, the transfer hole having a narrow portion in the first layer and a wide portion in the second layer; and filling a conductive material into the transfer hole.

In some embodiments of the present disclosure, the contact hole is integrally formed with a bit line trench in the second layer.

In some embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes: filling the bit line trench and a lower portion of the contact hole with a filling material.

In some embodiments of the present disclosure, removing a portion of the second layer surrounding the contact hole is performed after filling the lower portion of the contact hole with a sacrificial material.

In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes: forming a conductive feature comprising tungsten on the substrate; and forming a cladding layer comprising tungsten nitride on a top surface of the conductive feature.

In some embodiments of the present disclosure, the method for manufacturing a semiconductor device further includes: cleaning the conductive feature prior to forming a coating comprising tungsten nitride on a top surface of the conductive feature, wherein cleaning the conductive feature comprises applying a reducing agent to the top surface of the conductive feature, the reducing agent being titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

In some embodiments of the present disclosure, the method of manufacturing a semiconductor device further includes forming a plurality of capacitor structures on the capacitor contact.

In some embodiments of the present disclosure, the conductive member is located under the plurality of capacitive structures.

In some embodiments of the present disclosure, the conductive member is located on the plurality of capacitive structures.

Misalignment between the subsequently formed capacitor structure and the capacitor contact can be dramatically resolved because the capacitor contact with the neck and the head has a tapered profile. In addition, the cladding layer can reduce the formation of defects in the semiconductor element; thereby correspondingly increasing the yield of the semiconductor device.

The foregoing has outlined rather broadly the features and advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Other technical features and advantages, which constitute the subject of the present disclosure, will be described below. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the disclosure as set forth in the appended claims.

Drawings

The disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein like reference numerals refer to like elements, when considered in conjunction with the accompanying drawings.

Fig. 1 is a flow chart illustrating a method for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 2 and 3 are schematic cross-sectional views of a portion of a semiconductor manufacturing process according to an embodiment of the present disclosure.

Fig. 4 is a top view of the semiconductor device of fig. 3.

Fig. 5-7 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 8 is a top view of the semiconductor device of fig. 7.

FIG. 9 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

FIG. 10 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 11 is a top view of the semiconductor device of fig. 10.

FIG. 12 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 13 is a top view of the semiconductor device of fig. 12.

FIG. 14 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 15 is a top view of the semiconductor device of fig. 14.

FIG. 16 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 17 is a top view of the semiconductor device of fig. 16.

FIG. 18 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 19 is a top view of the semiconductor device of fig. 18.

FIG. 20 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 21 is a top view of the semiconductor device of fig. 20.

Fig. 22-25 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 26 is a top view of the semiconductor device of fig. 25.

Fig. 27-30 are cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Fig. 31-32 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Description of reference numerals:

101: substrate

103: insulation structure

105: active region

201: word line

203: bottom layer

205: intermediate layer

207: top layer

209: trench opening

301: first doped region

303: second doped region

401: contact point

402: contact hole

402-1: filling material

403: capacitance contact point

403-1: neck part

403-2: head part

403-3: arc side wall

404: conversion hole

404-1: narrow part

404-2: wide part

405: bit line contact

407: first coating layer

408: bit line trench opening

408-1: filling material

409: bit line

411: embolism

413: bottom hole

415: first conductive layer

417: second coating layer

419: third coating layer

421: the first barrier layer

501: capacitor structure

503: capacitor trench

505: bottom electrode

507: capacitor isolation layer

509: top electrode

801: first isolation film

803: second isolation film

805: third isolation film

807: fourth barrier film

809: fifth barrier film

811: sixth barrier film

813: seventh barrier film

W1: upper width

W2: upper width

X: direction of rotation

Y: direction of rotation

Z: direction of rotation

10: preparation method

S11: step (ii) of

S13: step (ii) of

S15: step (ii) of

S17: step (ii) of

S19: step (ii) of

S21: step (ii) of

S23: step (ii) of

S25: step (ii) of

Detailed Description

Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these examples are merely illustrative and are not intended to limit the scope of the present disclosure. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed intermediate the first and second features such that the first and second features may not be in direct contact. In addition, embodiments of the present disclosure may repeat reference numerals and/or letters in the various examples. These repetitions are for simplicity and clarity and do not, in themselves, represent a particular relationship between the various embodiments and/or configurations discussed, unless specifically stated in the context.

Furthermore, for ease of description, spatially relative terms such as "below", "lower", "above", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as such.

It will be understood that forming one element over (on), connecting to (connecting to), and/or coupling to (connecting to) another element may include embodiments in which the elements are formed in direct contact, and may also include embodiments in which additional elements are formed between the elements such that the elements are not in direct contact.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

Unless otherwise indicated in the context, when representing orientation (orientation), layout (layout), location (location), shape (shapes), size (sizes), quantity (amounts), or other measurements (measures), then terms (terms), such as "same", "equal", "flat", or "coplanar", as used herein, are not necessarily meant to refer to exactly the same orientation, layout, location, shape, size, quantity, or other measurement, but are meant to include, within acceptable differences, more or less the exact same orientation, layout, location, shape, size, quantity, or other measurement, which may occur, for example, as a result of manufacturing processes. The term "substantially" may be used herein to convey this meaning. Such as, for example, substantially identical (substitionally the same), substantially equal (substitionally equivalent), or substantially flat (substitional planar), exactly identical, equal, or flat, or they may be identical, equal, or flat within acceptable differences that may occur, for example, as a result of a manufacturing process.

In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics (semiconductor characteristics), and an electro-optical device (electro-optical device), a light-emitting display device (light-emitting display device), a semiconductor circuit (semiconductor circuit), and an electronic device (electronic device) are included in the scope of the semiconductor device.

It should be understood that in the description of the present disclosure, the upper (above) is the direction corresponding to the Z-direction arrow, and the lower (below) is the opposite direction corresponding to the Z-direction arrow.

The following description provides detailed steps and structures in order to provide a thorough understanding of the present disclosure. It is apparent that the implementation of the disclosure does not limit the specific details known to a person skilled in the art. In addition, well-known structures and steps are not shown in detail to avoid unnecessarily limiting the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure may be practiced in other embodiments, which depart from the specific details. The scope of the present disclosure is not limited by the detailed description but is defined by the related application documents.

Fig. 1 is a flow chart illustrating a method 10 for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 2 and 3 are schematic cross-sectional views of a portion of a semiconductor manufacturing process according to an embodiment of the present disclosure. Fig. 4 is a top view of the semiconductor device of fig. 3.

Referring to fig. 1 and 2, in step S11, a substrate 101 may be provided. For example, the substrate 101 may be formed of the following materials: silicon, doped silicon, silicon germanium (silicon germanium), silicon on insulator (silicon on insulator), silicon on sapphire (silicon on sapphire), silicon germanium on insulator (silicon germanium on insulator), silicon carbide (silicon carbide), germanium (germanium), gallium arsenide (gallium arsenide), gallium phosphide (gallium phosphide), gallium arsenide phosphide (gallium arsenide phosphide), indium phosphide (indium phosphide), indium gallium phosphide (indium phosphide).

Referring to fig. 3 and 4, in step S13, a plurality of insulating structures 103 may be formed in the substrate 101. In the cross-sectional view, the plurality of isolation structures 103 are spaced apart from one another and define a plurality of active regions 105. For example, the plurality of insulating structures 103 may be made of an isolation material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, fluorine-doped silicon, or the like. From a top view, the plurality of active regions 105 extend along a direction that is oblique with respect to the direction X. It should be understood that in the present disclosure, silicon oxynitride refers to a material containing silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a material containing silicon, nitrogen, and oxygen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

Fig. 5 and 7 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 8 is a top view of the semiconductor device of fig. 7.

Referring to fig. 1 and 5-8, in step S15, a plurality of word lines 201 may be formed in the substrate 101. In the illustrated embodiment, a plurality of word lines 201 may extend along the direction X. Each word line 201 has a bottom layer 203, a middle layer 205, a top layer 207, and a trench opening 209. Referring to fig. 5, in the illustrated embodiment, a photolithography process may be used to pattern the substrate 101 to define the locations of the trench openings 209. An etch process, such as an anisotropic dry etch process, may be performed to form a plurality of trench openings 209 in the substrate 101. Referring to fig. 6, a plurality of bottom layers 203 may be correspondingly formed and bonded to the plurality of trench openings 209 and the bottoms of the plurality of trench openings 209. For example, the bottom layers 203 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

Referring to fig. 7 and 8, a plurality of middle layers 205 may be correspondingly formed on a plurality of bottom layers 203. The top surfaces of the intermediate layers 205 may be lower than a top surface of the substrate 101. For example, the plurality of intermediate layers 205 may be made of doped polysilicon, a metallic material, or a metal silicide. For example, the metal silicide may be nickel silicide, platinum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tantalum silicide, tungsten silicide, or the like. A plurality of top layers 207 may be correspondingly formed on the plurality of intermediate layers 207. The top surfaces of the plurality of top layers 207 may be at the same level as the top surface of the substrate 101. For example, the top layers 207 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like.

FIG. 9 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 1 and 9, in step S17, a plurality of first regions and second regions may be formed in the active region 105 of the substrate 101. The doped regions may include a first doped region 301 and a plurality of second doped regions 303. First doped region 301 is located between two adjacent word lines 201. The second doped regions 303 are respectively located between the plurality of insulation structures 103 and the plurality of word lines 201. The first doped region 301 and the second doped region 301 are doped with a dopant, such as phosphorus (phosphorous), arsenic (arsenic) or antimony (antimony). The first doped region 301 and the second doped region 301 have doping concentrations in the range of 1E17 atoms/cm, respectively³To 1E19 atoms/cm³。

FIG. 10 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 11 is a top view of the semiconductor device of fig. 10.

Referring to fig. 1, 10 and 11, in step S19, a plurality of contact points 401 are formed on the substrate 101. A first isolation film 801 may be formed on the substrate 101. For example, the first isolation film 801 may be silicon nitride, silicon oxide, silicon oxynitride, undoped silicate glass (undoped silicate glass), borosilicate glass (borosilicate glass), phosphosilicate glass (phosphosilicate glass), borophosphosilicate glass (borophosphosilicate glass), or a combination thereof, but is not limited thereto. A plurality of contact points 401 may be formed in the first isolation film 801. A photolithography process may be used to pattern the first isolation film 801 to define the locations of the plurality of contacts 401. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of openings in the first isolation film 801. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt or other suitable metal or metal alloy, is deposited in the openings to form the contacts 401, which may be a metallization process such as chemical vapor deposition, physical vapor deposition, coating, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

In some embodiments, referring to fig. 10 and 11, the contact 401 is deposited on the first doped region 301 and electrically connected to the first doped region 301. In the illustrated embodiment, a contact 401 is formed comprising tungsten. When the top surface of the contact 401 is exposed to oxygen or air, defects are easily formed on a top surface of the contact 401 containing tungsten. The defects can affect the yield of the semiconductor device.

FIG. 12 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 13 is a top view of the semiconductor device of fig. 12.

Referring to fig. 1, 12 and 13, a plurality of bit line contacts 405 may be formed on the substrate 101. (only a bit line contact 405 is shown in fig. 12.) a second isolation film 803 may be formed over the first isolation film 801. The second isolation film 803 may be made of the same material as the first isolation film 801, but is not limited thereto. A photolithography process may be used to pattern the second isolation film 803 to define the locations of the bit line contacts 405. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of openings in the second isolation film 803. A top surface of the contact 401 may be exposed through the plurality of bit line openings. A cleaning process using a reducing agent may optionally be performed to remove the defects (defects) on the top surface of the tungsten-containing contact 401. The reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

Referring to fig. 12 and 13, after the cleaning process, a first cladding layer (first cladding layer)407 containing tungsten nitride may be formed to cover the bottom and sidewalls of the bit line contact openings. The first cladding layer 407 may prevent the top surface of the contact 401 containing tungsten from being exposed to oxygen or air; the first cladding layer 407 may reduce the formation of defects on the top surface of the contact 401 containing tungsten. A conductive material, such as aluminum, copper, tungsten, cobalt or other suitable metal alloys, may be deposited in the plurality of bit line contact openings by a metallization process, such as chemical vapor deposition, physical vapor deposition, coating, or the like, to form the plurality of bit line contacts 405. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

Referring to fig. 12 and 13, a plurality of bit line contacts 405 are correspondingly electrically connected to the contacts 401; that is, a plurality of bit line contacts 405 are electrically coupled to the first doped region 301.

FIG. 14 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 15 is a top view of the semiconductor device of fig. 14.

Referring to fig. 1, 14 and 15, in step S21, a plurality of bit lines 409 may be formed on the substrate 101. (only a bit line 409 is shown in FIG. 14.) A third isolation film 805 may be formed on the second isolation film 803. The third isolation film 805 may be made of the same material as the first isolation film 801, but is not limited thereto. A photolithography process may be used to pattern the third isolation film 805 to define the locations of the bit lines 409. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of bit line trench openings 408 in the third isolation film 805. In some embodiments, the photolithography process may also pattern the third isolation film 805 to define the locations of the contact holes 402, and an etching process may be performed to form the contact holes 402, wherein the contact holes 402 pass through the third isolation film 805, the second isolation film 803 and the first isolation film 801. In other words, the contact hole 402 is a very deep opening, while the bit line trench opening 408 is a relatively very shallow opening.

FIG. 16 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 17 is a top view of the semiconductor device of fig. 16. The bitline trench opening 408 and the contact hole 402 can be filled by a process such as chemical vapor deposition, physical vapor deposition, coating, or the like. In some embodiments, the contact hole 402 is deeper than the bit line trench opening 408, and the bit line trench opening 408 may be completely filled with a fill material 408-1, and the contact hole 402 may be partially filled with a fill material 402-1, wherein the fill material 402-1 may be the same as the fill material 408-1. In some embodiments, the upper portion of the contact hole 402 in the third isolation film 805 is not filled with the filling material 402-1.

FIG. 18 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 19 is a top view of the semiconductor device of fig. 18. In some embodiments, an etching process, such as an anisotropic etching process, may be performed to remove a portion of the third isolation film 805 surrounding the contact hole 402 to form a plurality of conversion holes 404, wherein the plurality of conversion holes 404 have a narrow portion 404-1 and a wide portion 404-2, the narrow portion 404-1 is occupied by the filling material 402-1 in the second isolation film 803, and the wide portion 404-2 is occupied in the third isolation film 805.

FIG. 20 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 21 is a top view of the semiconductor device of fig. 20. In some embodiments, fill material 402-1 and fill material 408-1 are stripped from the transfer hole 404 and the bit line trench opening 408, respectively. After stripping the filling material, a conductive material, such as aluminum, copper, tungsten, cobalt or other suitable metal or metal alloy, may be deposited in the bit line trench openings 408 to form bit lines 406 and capacitor contacts 403 in the transfer holes 404 by a metallization process, such as chemical vapor deposition, physical vapor deposition, coating or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

In some embodiments, capacitive contact 403 has a neck 403-1 and a head 403-2, head 403-2 being located on neck 403-1, wherein an upper width W1 of head 403-2 is greater than an upper width W2 of neck 403-1. In some embodiments, the upper width W2 of neck 403-1 is substantially the same as a lower width of head 403-2. In some embodiments, head 403-2 has an arcuate sidewall 403-3. In some embodiments, the head has a tapered profile.

Referring to fig. 20 and 21, a plurality of bit lines 409 may extend along the direction Y, and the top of the diagram shows a wavy line. A plurality of bit line contacts 405 are located at the intersections of the plurality of bit lines 409 and the plurality of active regions 105. The plurality of bit lines 409 in the form of wavy lines can increase a contact area between the plurality of bit line contacts 405 and the plurality of active regions 105; therefore, a contact resistance between the bit line contacts 405 and the active regions 105 can be reduced.

FIG. 22 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Referring to fig. 1 and 22, a plurality of plugs (plugs)411 may be formed on the substrate 101. A fourth isolation film 807 may be formed on the third isolation film 805. The fourth isolation film 807 may be made of the same material as the first isolation film 801, but not limited thereto. A photolithography process may be used to pattern the fourth isolation film 807 to define the locations of the plurality of plugs 411. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of plug openings, which pass through the fourth isolation film 807. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the plug openings by a metallization process, such as chemical vapor deposition, physical vapor deposition, coating, or the like, to form plugs 411 over the heads 403-2. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

Fig. 23-25 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. Fig. 26 is a top view of the semiconductor device of fig. 25.

Referring to fig. 1 and 23 to 26, in step S25, a plurality of capacitor structures 501 may be formed on the substrate 101. Each capacitor structure 501 may have a bottom electrode 505, a capacitor isolation layer 507, and a top electrode 509. Referring to fig. 23, a fifth isolation film 809 may be formed on the fourth isolation film 807. The fifth isolation film 809 may be made of the same material as the first isolation film 801, but is not limited thereto. A photolithography process may be used to pattern the fifth isolation film 809 to define the locations of the plurality of capacitor trenches 503. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a plurality of capacitor trenches 503, and the plurality of capacitor trenches 503 pass through the fifth isolation film 809. The plurality of plugs 411 may be exposed through the plurality of capacitor trenches 503.

Referring to fig. 24, a plurality of bottom electrodes 505 may be correspondingly formed in the plurality of electrode trenches 503, respectively; in other words, a plurality of bottom electrodes 505 may be inwardly formed in the fifth isolation film 809. For example, the plurality of bottom electrodes 505 may be made of doped polysilicon, metal silicide, aluminum, copper, or tungsten. The plurality of bottom electrodes 505 may be respectively connected to the plurality of plugs 411.

Referring to fig. 24, a capacitor isolation layer 507 may be formed to connect sidewalls and bottoms of the plurality of bottom electrodes 505 and a top surface of the fifth isolation film 809. The capacitive isolation layer 507 may be a single layer or multiple layers. In the illustrated embodiment, the capacitive isolation layer 507 may be a single layer or multiple layers. Specifically, the capacitor isolation layer 507 may be a single layer made of a high dielectric constant material, such as barium strontium titanate (barium titanate), lead zirconate titanate (lead zirconate titanate), titanium oxide (titanium oxide), aluminum oxide (aluminum oxide), hafnium oxide (hafnium oxide), yttrium oxide (yttrium oxide), zirconium oxide (zirconium oxide), or the like. Alternatively, in another embodiment, the capacitive isolation layer 507 may be formed of multiple layers, which are composed of silicon oxide, silicon nitride and silicon oxide.

Referring to fig. 25 and 26, a top electrode 509 may be formed to fill the plurality of capacitor trenches 503 and cover the capacitor isolation layer 507. For example, the top electrode 509 may be made of doped polysilicon, copper, or aluminum.

Fig. 27-29 are cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure. In some embodiments, a bottom via 413 and a first conductive layer 415 may be formed on the substrate 101. Referring to fig. 27, a sixth isolation film 811 may be formed on the fifth isolation film 809. The sixth isolation film 811 may be made of the same material as the first isolation film 801, but is not limited thereto. A photolithography process may be used to pattern the sixth isolation film 811 to define the location of the bottom via 413. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a bottom via opening, which penetrates through the sixth isolation film 811. After the etching process, a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal or metal alloy, is deposited in the bottom via opening by a metallization process, such as chemical vapor deposition, physical vapor deposition, coating, or the like, to form the bottom via 413 in the sixth isolation film 811. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

Referring to fig. 27, in the illustrated embodiment, a bottom via 413 comprising tungsten is formed. When the top surface of bottom via 403 is exposed to oxygen or air, a top surface of bottom via 413 comprising tungsten is susceptible to defects. The defects may affect the yield of the semiconductor device.

Referring to fig. 28, a seventh isolation film 813 may be formed on the sixth isolation film 811. The seventh isolation film 813 may be made of the same material as the first isolation film 801, but is not limited thereto. A photolithography process may be used to pattern the seventh isolation film 813 to define the location of the first conductive layer 415. After the photolithography process, an etching process, such as an anisotropic dry etching process, may be performed to form a first conductive layer trench in the seventh isolation film 813. The top surface of the bottom penetration hole 413 may be exposed through the first conductive layer trench. A cleaning process using a reducing agent may optionally be performed to remove the defects (defects) on the top surface of the bottom via 413 comprising tungsten. The reducing agent may be titanium tetrachloride, tantalum tetrachloride, or a combination thereof.

Referring to fig. 28 and 29, after the cleaning process, a second cladding layer 417 comprising tungsten nitride may be formed to cover a bottom and sidewalls of the first conductive layer trench. The second cladding layer 417 may prevent the top surface of the bottom via 413 comprising tungsten from being exposed to oxygen or air; the second cladding layer 417 may reduce the formation of defects on the top surface of the bottom via 413 including tungsten. The first conductive layer 415 may be formed by depositing a conductive material, such as aluminum, copper, tungsten, cobalt, or other suitable metal alloys, in the first conductive layer trenches by a metallization process, such as chemical vapor deposition, physical vapor deposition, coating, or the like. After the metallization process, a planarization process, such as chemical mechanical polishing, may be performed to remove excess deposited material and provide a substantially planar surface for subsequent processing steps.

FIG. 30 is a schematic cross-sectional view of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 30, a semiconductor device may include a substrate 101, a plurality of insulating structures 103, a plurality of word lines 201, a plurality of doped regions, a plurality of isolation films, a plurality of contacts, a plurality of bit line contacts 405, a first cladding layer 407, a plurality of bit lines 409, a plurality of plugs 411, a bottom via 413, a first conductive layer 415, a second cladding layer 417, and a plurality of capacitor structures 501.

Referring to fig. 30, a plurality of insulating structures 103 may be disposed in the substrate 101 and spaced apart from each other. The plurality of isolation structures 103 may define a plurality of active regions 105. A plurality of word lines 201 may be disposed in the substrate 101 and spaced apart from each other. Each word line 201 includes a bottom layer 203, a middle layer 205, and a top layer 207. A plurality of bottom layers 203 may be respectively disposed inwardly in the substrate 101. The plurality of middle layers 205 may be respectively disposed on the plurality of bottom layers 203. The top surfaces of the intermediate layers 205 may be lower than a top surface of the substrate 101. A plurality of top layers 207 may be correspondingly disposed on the plurality of middle layers 205, respectively. The top surfaces of the plurality of top layers 207 are located at the same vertical level as the top surface of the substrate 101.

Referring to fig. 30, a plurality of doped regions may be disposed in a plurality of active regions 105 of a substrate 101. Each doped region has a first doped region 301 and a plurality of second doped regions 303. For each doped region, a first doped region 301 is disposed between two adjacent word lines 201. The second doped regions 303 are respectively disposed between the plurality of insulation structures 103 and the plurality of word lines 201.

Referring to fig. 30, a plurality of isolation films may be disposed on the substrate 101. The plurality of isolation films may include a first isolation film 801, a second isolation film 803, a third isolation film 805, a fourth isolation film 807, a fifth isolation film 809, a sixth isolation film 811, and a seventh isolation film 813. The first isolation film 801 may be disposed on the substrate 101. A plurality of contact points may be provided in the first isolation film 801. The plurality of contact points may include a contact point 401 and a plurality of second contact points 403. A contact 401 is disposed on the first doped region 301 and connected to the first doped region 301. The second contact points 403 are respectively disposed on the second doped regions 303 and respectively electrically connected to the second doped regions 303. In this embodiment, a contact 401 containing tungsten is formed.

Referring to fig. 30, a second isolation film 803 may be disposed on the first isolation film 801. A plurality of bit line contacts 405 may be disposed in the second isolation film 803. (only one bit line contact is shown in FIG. 30.) the first cladding layer 407 may be disposed in the second isolation film 803 and on a top surface of the contact 401; in other words, the first cladding layer 407 may be disposed between the plurality of bit line contacts 405 and the contacts 401. In addition, the first cladding layer 407 may be disposed on sidewalls of the plurality of bit line contacts 405 and bonded to sidewalls of the plurality of bit line contacts 405. The first cladding layer 407 may contain tungsten nitride.

Referring to fig. 30, a third isolation film 805 may be disposed on the second isolation film 803. A plurality of bit lines 409 may be disposed in the third isolation film 805 and on the plurality of bit line contacts 405 and the first cladding layer 407. (only a bit line 409 is shown in FIG. 30.) A fourth isolation film 807 may be provided on the third isolation film 805. A plurality of plugs 411 may be provided to penetrate through the fourth isolation film 807, the third isolation film 805, and the second isolation film 803. The plugs 411 may be respectively electrically connected to the second contacts 403.

Referring to FIG. 30, capacitor contact 403 has a neck 403-1 and a head 403-2, head 403-2 is located on neck 403-1, wherein an upper width W1 of head 403-2 is greater than an upper width W2 of neck 403-1. In some embodiments, the upper width W2 of neck 403-1 is approximately the same as a lower width of head 403-2. In some embodiments, head 403-2 has an arcuate sidewall 403-3. In some embodiments, the head has a tapered profile.

Referring to fig. 30, a fifth isolation film 809 may be disposed on the fourth isolation film 807. A plurality of capacitance structures 501 may be disposed in the fifth isolation film 809. The plurality of capacitor structures 501 may include a plurality of bottom electrodes 505, a capacitor isolation layer 507, and a top electrode 509. The bottom electrodes 505 may be disposed inwardly in the fifth isolation film 809 and electrically connected to the plugs 411, respectively. The capacitive isolation layer 507 may be disposed on the plurality of bottom electrodes 505. A top electrode 509 may be disposed on the capacitive isolation layer 507.

Referring to fig. 30, a sixth isolation film 811 may be disposed on the fifth isolation film 809. The bottom through hole 413 may be disposed in the sixth isolation film 811 and electrically connected to the top electrode 509. Bottom via 413 may comprise tungsten. A seventh barrier film 813 may be disposed on the sixth barrier film 811. The first conductive layer 415 may be disposed in the seventh isolation film 813 on the bottom penetration hole 413. The second cladding layer 417 may be disposed on a top surface of the bottom via 413, and the second cladding layer 417 may be disposed between the bottom via 413 and the first conductive layer 415. In addition, a second clad layer 417 may be disposed on the sidewall of the first conductive layer 415 and bonded to the sidewall of the first conductive layer 415. The second cladding layer 417 may contain tungsten nitride.

Fig. 31-32 are schematic cross-sectional views of a portion of a process for fabricating a semiconductor device according to an embodiment of the present disclosure.

Referring to fig. 31, the semiconductor device may include a plurality of third cladding layers 419. A plurality of third cladding layers 419 may be respectively disposed between the second contact point 403 and the plurality of plugs 411. In other words, a plurality of third cladding layers 419 may be respectively disposed on the top surfaces of the second contact points 403 containing tungsten. A plurality of third coating layers 419 may be respectively disposed on the sidewalls of the plurality of plugs 411 and coupled to the sidewalls of the plurality of plugs 411. Third plurality of cladding layers 419 may comprise tungsten nitride. In the present embodiment, only the first cladding layer 407, the second cladding layer 417, and the plurality of third cladding layers 419 are respectively provided on the contact point 401, the bottom penetration hole 413, and the second contact point 403; however, other conductive layers or vias may be suitable.

It should be understood that in the present embodiment, a cladding layer can be regarded as the first cladding layer 407, the second cladding layer 417 or the third cladding layer 419, but not limited thereto. A conductive feature may be used as the contact 401, the second contact 403, or the bottom via 413, but is not limited thereto.

Referring to fig. 32, the semiconductor device may include a first barrier layer (first barrier layer) 421. The first barrier layer 421 may be disposed between the first cladding layer 407 and the plurality of bit line contacts 405. For example, the first barrier layer 421 can be made of titanium, titanium nitride, titanium tungsten alloy, tantalum nitride, or a combination thereof. The first barrier layer 421 can improve adhesion (adhesion) between the first cladding layer 407 and the bit line contacts 405.

An embodiment of the present disclosure provides a semiconductor device, including: a substrate; a plurality of capacitive contacts on the substrate, at least one of the plurality of capacitive contacts having a neck and a head, the head being on the neck, wherein an upper width of the head is greater than an upper width of the neck; a plurality of bit line contacts on the substrate and a plurality of bit lines on the plurality of bit line contacts, wherein at least one of the plurality of bit lines is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure located on the head.

Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device. The preparation method comprises the following steps: providing a substrate; forming a plurality of bit line contacts on a first portion of the substrate; forming a plurality of bit lines on the plurality of bit line contacts; forming a capacitor contact point on a second portion of the substrate, the capacitor contact point having a neck portion and a head portion on the neck portion, wherein an upper width of the head portion is greater than an upper portion of the neck portion; and forming a capacitor structure on the head; wherein at least one of the bit lines is a wavy line extending between two adjacent capacitive contacts.

Misalignment between the subsequently formed capacitor structure and the capacitor contact can be dramatically resolved because the capacitor contact with the neck and the head has a tapered profile. In addition, the cladding layer can reduce the formation of defects in the semiconductor element; thereby correspondingly increasing the yield of the semiconductor device.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes described above may be performed in different ways and replaced with other processes or combinations thereof.

Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims of this disclosure.