阅读说明：本技术 显示装置 (Display device ) 是由 金炳善 郭源奎 金京花 金才源 朴亨埈 曹承延 崔埈源 于 2020-07-08 设计创作，主要内容包括：本公开涉及一种显示装置,所述显示装置包括：基底,包括显示区域和位于所述显示区域外部的外围区域,所述显示区域包括第一显示区域和第二显示区域；第一扇出部分,位于所述第一显示区域外部的所述外围区域的一部分中；第二扇出部分,位于所述第一扇出部分外部；第一电源线,与所述显示区域的一侧对应地位于所述外围区域中并且与所述第一扇出部分的至少一部分重叠；以及第二电源线,位于所述显示区域外部的所述外围区域中并且与所述第二扇出部分的至少一部分重叠。(The present disclosure relates to a display device, including: a substrate including a display area and a peripheral area outside the display area, the display area including a first display area and a second display area; a first fan-out section located in a portion of the peripheral region outside the first display region; a second fan-out section located outside the first fan-out section; a first power line in the peripheral region corresponding to one side of the display region and overlapping at least a portion of the first fan-out section; and a second power supply line in the peripheral region outside the display region and overlapping at least a portion of the second fan-out section.)

1. A display device, wherein the display device comprises:

a substrate including a display area and a peripheral area outside the display area, the display area including a first display area and a second display area;

a first fan-out section located in a portion of the peripheral region outside the first display region;

a second fan-out section located outside the first fan-out section;

a first power line in the peripheral region corresponding to one side of the display region and overlapping at least a portion of the first fan-out section; and

a second power supply line in the peripheral region outside the display region and overlapping at least a portion of the second fan-out section.

2. The display device according to claim 1, wherein the display device further comprises: a driving circuit interposed between the first and second fan-out sections corresponding to the first display region, and interposed between the second display region and the second fan-out section corresponding to the second display region.

3. The display device according to claim 2, wherein the driving circuit comprises: a first sub driving circuit and a second sub driving circuit each interposed between the first fan-out section and the second fan-out section and corresponding to the first display region, and

the first and second sub driving circuits are spaced apart from each other by a first distance.

4. The display device according to claim 3, wherein the drive circuit comprises: a third sub driving circuit and a fourth sub driving circuit each interposed between the second display region and the second fan-out section and corresponding to the second display region, and

the third sub driving circuit and the fourth sub driving circuit are spaced apart from each other by a second distance smaller than the first distance.

5. The display device of claim 4, wherein the first fan-out section includes first and second fan-out lines respectively located on different layers over the substrate, and

the first fanout lines and the second fanout lines are alternately arranged.

6. The display device of claim 5, wherein the second fan-out section includes a third fan-out line and a fourth fan-out line respectively located on different layers above the substrate, and

the third fanout lines and the fourth fanout lines are alternately arranged.

7. The display device according to claim 6, wherein the third fan-out line passes between the third sub-driver circuit and the fourth sub-driver circuit.

8. The display device according to claim 6, wherein the display device further comprises: a plurality of pixels located in the display area,

wherein the first power supply line is configured to supply a first power supply voltage to the plurality of pixels.

9. The display device according to claim 8, wherein the second power supply line is configured to supply a second power supply voltage to the plurality of pixels.

10. The display device according to claim 9, wherein the display device further comprises: a plurality of first data lines in the first display region and extending in a first direction,

wherein the first and second fanout lines are connected to the plurality of first data lines and configured to provide data signals to the plurality of pixels.

11. The display device according to claim 10, wherein the display device further comprises: a plurality of second data lines located in the second display area and extending in the first direction,

wherein the third and fourth fanout lines are connected to the plurality of second data lines and configured to provide data signals to the plurality of pixels.

12. The display device according to claim 10, wherein the display device further comprises: a plurality of scan lines located in the display area and extending in a second direction crossing the first direction,

wherein the driving circuit is configured to transmit a scan signal to each pixel through the plurality of scan lines.

13. The display device according to claim 5, wherein the display device further comprises: a thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, the gate electrode being insulated from the semiconductor layer, and the source electrode and the drain electrode being insulated from the gate electrode,

wherein the first fanout line includes a material identical to a material of the gate electrode, and the first power line includes a material identical to a material of the source electrode.

14. The display device according to claim 13, wherein the display device further comprises: a storage capacitor comprising a bottom electrode and a top electrode on the bottom electrode,

the first fanout line comprises a material which is the same as that of the bottom electrode or the top electrode.

15. The display device of claim 1, wherein the display area comprises rounded corners.

16. A display device, wherein the display device comprises:

a substrate including a display area and a peripheral area outside the display area, the display area including a first display area and a second display area;

a first fan-out section located in the peripheral region outside the first display region and including a first fan-out line and a second fan-out line;

a second fan-out section located outside the first fan-out section and including a third fan-out line and a fourth fan-out line;

a first power line overlapping at least a portion of the first fanout line and disposed above the first fanout line; and

a second power line overlapping with at least a portion of the third fanout line and disposed above the third fanout line.

17. The display device according to claim 16, wherein the display device further comprises: a driving circuit interposed between the first and second fan-out sections corresponding to the first display region, and interposed between the second display region and the second fan-out section corresponding to the second display region.

18. The display device according to claim 17, wherein the driving circuit comprises: a first sub driving circuit and a second sub driving circuit each interposed between the first fan-out section and the second fan-out section and corresponding to the first display region, and

the first and second sub driving circuits are spaced apart from each other by a first distance.

19. The display device according to claim 18, wherein the driving circuit comprises: a third sub driving circuit and a fourth sub driving circuit each interposed between the second display region and the second fan-out section and corresponding to the second display region, and

the third sub driving circuit and the fourth sub driving circuit are spaced apart from each other by a second distance smaller than the first distance.

20. The display device according to claim 16, wherein the first and second fan-out lines are located on different layers over the substrate, respectively, and the third and fourth fan-out lines are located on different layers over the substrate, respectively.

Technical Field

Aspects of one or more embodiments relate to a display device.

Background

With the development of the information-oriented society, the demand for display devices for displaying various images has increased. In addition, as display devices have become thinner and lighter in weight, the range of potential uses thereof has gradually expanded.

In order to increase the size of the display area in the display device, the so-called dead space may be reduced. In order to reduce the dead space outside the display region, a method of overlapping wirings arranged in the peripheral region may be utilized.

The above information disclosed in this background section is only for enhancement of understanding of the background and, thus, the information discussed in this background section does not necessarily constitute prior art.

Disclosure of Invention

Aspects of one or more embodiments relate to a display device, for example, to a display device having a reduced dead space.

In the display device according to the related art, the dead space in the corner portion may be wider than the dead space in the straight portion.

Aspects of one or more example embodiments include a display device in which dead space in corners is minimized or reduced. It should be understood, however, that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limiting the disclosure.

Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the provided embodiments of the disclosure.

According to some example embodiments, a display apparatus includes: a substrate including a display area and a peripheral area outside the display area, the display area including a first display area and a second display area; a first fan-out section located in a portion of the peripheral region outside the first display region; a second fan-out section located outside the first fan-out section; a first power supply line disposed in the peripheral region corresponding to one side of the display region and overlapping at least a portion of the first fan-out section; and a second power supply line disposed in the peripheral region outside the display region and overlapping at least a portion of the second fan-out section.

According to some example embodiments, the display apparatus may further include: a driving circuit disposed between the first fan-out section and the second fan-out section corresponding to the first display region, and disposed between the second display region and the second fan-out section corresponding to the second display region.

According to some example embodiments, the driving circuit may include: a first sub driving circuit and a second sub driving circuit each disposed between the first fan-out part and the second fan-out part and corresponding to the first display region, and the first sub driving circuit and the second sub driving circuit may be spaced apart from each other by a first distance.

According to some example embodiments, the driving circuit may include: a third sub driving circuit and a fourth sub driving circuit each disposed between the second display region and the second fan-out section and corresponding to the second display region, and the third sub driving circuit and the fourth sub driving circuit may be spaced apart from each other by a second distance smaller than the first distance.

According to some example embodiments, the first fan-out section may include first and second fan-out lines respectively arranged on different layers above the substrate, and the first and second fan-out lines may be alternately arranged.

According to some example embodiments, the second fan-out part may include third and fourth fan-out lines respectively arranged on different layers over the substrate, and the third and fourth fan-out lines may be alternately arranged.

According to some example embodiments, the third fan-out line may pass between the third sub driving circuit and the fourth sub driving circuit.

According to some example embodiments, the display apparatus may further include: a plurality of pixels arranged in the display area, wherein the first power line may supply a first power voltage to the plurality of pixels.

According to some example embodiments, the second power line may supply a second power voltage to the plurality of pixels.

According to some example embodiments, the display apparatus may further include: and a plurality of first data lines arranged in the first display region and extending in a first direction, wherein the first and second fanout lines may be connected to the plurality of first data lines and may supply data signals to the plurality of pixels.

According to some example embodiments, the display apparatus may further include: and a plurality of second data lines arranged in the second display region and extending in the first direction, wherein the third and fourth fanout lines may be connected to the plurality of second data lines and may supply data signals to the plurality of pixels.

According to some example embodiments, the display apparatus may further include: a plurality of scan lines arranged in the display region and extending in a second direction crossing the first direction, wherein the driving circuit may transmit a scan signal to each pixel through the plurality of scan lines.

According to some example embodiments, the display apparatus may further include: a thin film transistor including a semiconductor layer, a gate electrode, a source electrode, and a drain electrode, the gate electrode being insulated from the semiconductor layer, and the source electrode and the drain electrode being insulated from the gate electrode, wherein the first fanout line may include a material identical to a material of the gate electrode, and the first power line may include a material identical to a material of the source electrode.

According to some example embodiments, the display apparatus may further include: and a storage capacitor including a bottom electrode and a top electrode on the bottom electrode, wherein the first fanout line may include a material identical to a material of the bottom electrode or the top electrode.

According to some example embodiments, the display area may include rounded corners.

According to some example embodiments, a display apparatus includes: a substrate including a display area and a peripheral area outside the display area, the display area including a first display area and a second display area; a first fan-out section disposed in the peripheral region outside the first display region and including a first fan-out line and a second fan-out line; a second fan-out section disposed outside the first fan-out section and including a third fan-out line and a fourth fan-out line; a first power line overlapping at least a portion of the first fanout line and disposed above the first fanout line; and a second power line overlapping with at least a portion of the third fanout line and disposed above the third fanout line.

According to some example embodiments, the display apparatus may further include: a driving circuit disposed between the first fan-out section and the second fan-out section corresponding to the first display region, and disposed between the second display region and the second fan-out section corresponding to the second display region.

According to some example embodiments, the driving circuit may include: a first sub driving circuit and a second sub driving circuit each disposed between the first fan-out part and the second fan-out part and corresponding to the first display region, and the first sub driving circuit and the second sub driving circuit may be spaced apart from each other by a first distance.

According to some example embodiments, the driving circuit may include: a third sub driving circuit and a fourth sub driving circuit each disposed between the second display region and the second fan-out section and corresponding to the second display region, and the third sub driving circuit and the fourth sub driving circuit may be spaced apart from each other by a second distance smaller than the first distance.

According to some example embodiments, the first and second fanout lines may be respectively disposed on different layers above the substrate, and the third and fourth fanout lines may be respectively disposed on different layers above the substrate.

The above and other aspects, features and characteristics of specific embodiments of the present disclosure will become more apparent from the following description, the accompanying drawings and the present disclosure.

Drawings

The above and other aspects, features and characteristics of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a perspective view of a display device according to some example embodiments;

fig. 2 and 3 are plan views of a display device according to some example embodiments;

fig. 4 and 5 are equivalent circuit diagrams of pixels that may be included in a display device according to some example embodiments;

FIG. 6 is a plan view of a display device according to some example embodiments;

fig. 7 is a sectional view of the display device taken along line I-I' of fig. 6;

fig. 8A to 8C are sectional views of the display device taken along line II-II' of fig. 6;

fig. 9A and 9B are sectional views of the display device taken along the line III-III' of fig. 6;

fig. 10 is a sectional view of the display device taken along line IV-IV' of fig. 6; and

fig. 11 is a sectional view of the display device taken along line V-V' of fig. 6.

Detailed Description

Reference will now be made in greater detail to aspects of some example embodiments that are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below in order to explain aspects of the present specification by referring to the figures only. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression "at least one (of) a, b and c" means only a, only b, only c, both a and b, both a and c, both b and c, all a, b and c, or their variations.

Hereinafter, the present embodiment is described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same or corresponding elements, and a repetitive description thereof is omitted.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components. It will be understood that when a layer, region or component is referred to as being "formed on" another layer, region or component, it can be directly or indirectly formed on the other layer, region or component. That is, for example, intervening layers, regions, or components may be present.

The size of elements in the drawings may be exaggerated for convenience of explanation. In other words, since the sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

In the following description, the x-axis, y-axis, and z-axis are not limited to three axes of a rectangular coordinate system, and may be explained in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

While certain embodiments may be implemented differently, certain process sequences may be performed differently than described. For example, two processes described in succession may be executed substantially concurrently, or may be executed in the reverse order to that described.

Fig. 1 is a perspective view of a display device 1 according to some example embodiments.

Referring to fig. 1, the display device 1 may include a display area DA on which an image is displayed and a peripheral area PA on which no image is displayed. The display device 1 may display an image by using light emitted from a plurality of pixels P arranged in the display area DA. No image is displayed on the peripheral area PA. The peripheral area PA may be an area outside the display area DA.

Hereinafter, although the display device 1 according to some example embodiments is described as an organic light emitting display device as an example, the display device according to embodiments of the present disclosure is not limited thereto. According to some example embodiments, the display device 1 may be various display devices, for example, an inorganic light emitting display and a quantum dot light emitting display. For example, the emission layer provided to the display element of the display device 1 may include an organic material, an inorganic material, quantum dots, an organic material and quantum dots, or an inorganic material and quantum dots.

Although fig. 1 shows the display device 1 having a flat display surface, the embodiment is not limited thereto. According to some example embodiments, the display device 1 may comprise a three-dimensional display surface or a curved display surface.

In the case where the display device 1 includes a three-dimensional display surface, the display device 1 may include a plurality of display regions each indicating a different direction, for example, including a polygonal prism-type display surface. According to some example embodiments, in the case where the display device 1 includes a curved display surface, the display device 1 may be implemented in various types, such as a flexible display device, a foldable display device, and a rollable display device.

In addition, fig. 1 shows a display device 1 applicable to a mobile phone terminal according to some example embodiments. According to some example embodiments, an electronic module, a camera module, a power supply module, and the like mounted on a main board are arranged on a stand/case together with the display device 1 to constitute a mobile phone terminal. The display device 1 according to some example embodiments may be applied to large electronic devices such as televisions, monitors, and small and medium electronic devices such as tablet devices, car navigation devices, game machines, and smart watches.

Although fig. 1 illustrates a case where the display area DA of the display apparatus 1 is a quadrangle, the shape of the display area DA may be a circle, an ellipse, or a polygon such as a triangle or a pentagon, according to some example embodiments.

Fig. 2 and 3 are plan views of a display device 1 according to some example embodiments.

Referring to fig. 2, the display area DA of the display apparatus 1 according to some example embodiments may include a first display area DA1 and a second display area DA 2. In addition, the four corners DA-C of the display area DA may have a rounded shape having a curvature (e.g., a set or predetermined curvature). The peripheral area PA may surround the display area DA. However, the shape of the display area DA and the shape of the peripheral area PA may be designed relatively.

Referring to fig. 3, the display device 1 may include a plurality of pixels P arranged in the display area DA. Each of the plurality of pixels P may include a display element such as an organic light emitting diode OLED. Each pixel P may emit, for example, red, green, blue or white light from the organic light emitting diode OLED. In this specification, the pixel P may be a pixel emitting red, green, blue, or white light as described above. Since the thin film encapsulation layer TFE (see, for example, fig. 7) covers the display area DA, the display area DA can be protected from external air or moisture.

Each pixel P may be electrically connected to an external circuit arranged in the peripheral area PA. The driving circuit 120, the pad unit 140, the data driving circuit 150, the first power line 160, and the second power line 170 may be arranged in the peripheral area PA.

The driving circuit 120 may supply a scan signal to each pixel P through the scan line SL and an emission control signal to each pixel P through the emission control line EL. The driving circuits 120 may be disposed at left and right sides of a display area DA interposed between the driving circuits 120. Some of the plurality of pixels P arranged in the display area DA may be electrically connected to at least one of the driving circuits 120 disposed at the left and right sides of the display area DA.

The pad unit 140 may be disposed on one side or an edge of the substrate 100. The pad unit 140 may be exposed and electrically connected to a printed circuit board PCB (not shown) as not being covered by the insulating layer. The pad unit of the printed circuit board PCB may be electrically connected to the pad unit 140 of the display device 1. The printed circuit board PCB may transmit signals or power of the controller to the display apparatus 1.

The control signals generated by the controller may be transmitted to the driving circuits 120 located at the left and right sides of the display area DA, respectively, through the printed circuit board PCB. The controller may supply a first power voltage to the first power line 160 through the first connection line 161 and supply a second power voltage to the second power line 170 through the second connection line 171.

The first power supply voltage may be supplied to each pixel P through the driving voltage line PL connected to the first power supply line 160, and the second power supply voltage may be supplied to the opposite electrode of each pixel P connected to the second power supply line 170. The driving voltage line PL may extend in the first direction (y direction). For example, the first power supply voltage may include a driving voltage ELVDD (see fig. 4), and the second power supply voltage may include a common voltage ELVSS (see fig. 4).

The data driving circuit 150 is electrically connected to the data lines DL. The data signal of the data driving circuit 150 may be supplied to each pixel P through a connection line connected to the pad unit 140 and a data line DL connected to the connection line. Although it is illustrated in fig. 3 that the data driving circuit 150 is disposed between the first power line 160 and the pad unit 140 over the substrate 100, the data driving circuit 150 may be disposed on a printed circuit board PCB according to some example embodiments.

The first power line 160 may include a first sub-line 162 and a second sub-line 163 parallel to each other and extending in the second direction (x direction), and the display area DA is interposed between the first and second sub-lines 162 and 163. The second power line 170 may have a ring shape having one open side and partially surrounding the display area DA.

Fig. 4 and 5 are equivalent circuit diagrams of pixels that may be included in the display device 1 according to some example embodiments.

Referring to fig. 4, each pixel P may include a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a driving thin film transistor Td, a switching thin film transistor Ts, and a storage capacitor Cst. The switching thin film transistor Ts is connected to the scan line SL and the data line DL, and may transmit a data signal Dm input through the data line DL to the driving thin film transistor Td in response to a scan signal Sn input through the scan line SL.

The storage capacitor Cst is connected to the switching thin film transistor Ts and the driving voltage line PL, and may store a voltage corresponding to a difference between the voltage transferred from the switching thin film transistor Ts and the first power supply voltage supplied to the driving voltage line PL.

The driving thin film transistor Td is connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light having a luminance (e.g., a set or predetermined luminance) by using a driving current.

Although it is illustrated in fig. 4 that the pixel circuit PC includes two thin film transistors and one storage capacitor, embodiments according to the present disclosure are not limited thereto. For example, as shown in fig. 5, the pixel circuit PC may include seven thin film transistors and one storage capacitor. Although it is illustrated in fig. 5 that the pixel circuit PC includes one storage capacitor, the pixel circuit PC may include two or more storage capacitors.

Referring to fig. 5, the pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of thin film transistors and storage capacitors. The thin film transistor and the storage capacitor may be connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

Although it is illustrated in fig. 5 that the pixels P are connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, the embodiment is not limited thereto. According to some example embodiments, at least one of the signal line SL, SL-1, EL, or DL, the initialization voltage line VL, or the driving voltage line PL may be shared by pixels adjacent to each other.

The signal lines include a scan line SL transmitting a scan signal Sn, a previous scan line SL-1 transmitting the previous scan signal Sn-1 to the first and second initializing thin film transistors T4 and T7, an emission control line EL transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL and transmitting a data signal. The driving voltage line PL transmits a driving voltage to the driving thin film transistor T1, and the initializing voltage line VL transmits an initializing voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED. Therefore, as shown in fig. 5, according to some example embodiments, the gate electrode of the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED may be configured to be initialized by receiving the initialization voltage Vint in response to the previous scan signal Sn-1 that turns on the first and second initialization thin film transistors T4 and T7.

The driving gate electrode G1 of the driving thin film transistor T1 is connected to the bottom electrode Cst1 of the storage capacitor Cst, and the driving source electrode S1 of the driving thin film transistor T1 controls the thin film transistor T1 by operationT5 is connected to the driving voltage line PL, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission controlling thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2, and may drive the current I_OLEDTo the organic light emitting diode OLED.

The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is concurrently (or simultaneously) connected to the driving voltage line PL by operating the controlling thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn transmitted through the scan line SL, and may perform a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and is concurrently (or simultaneously) connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6, and the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the bottom electrode Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn transmitted through the scan line SL, and may be diode-connected to the driving thin film transistor T1 by electrically connecting the driving gate electrode G1 to the driving drain electrode D1 of the driving thin film transistor T1.

The first initializing gate electrode G4 of the first initializing thin film transistor T4 is connected to the previous scan line SL-1, the first initializing source electrode S4 of the first initializing thin film transistor T4 is connected to the second initializing drain electrode D7 of the second initializing thin film transistor T7 and the initializing voltage line VL, and the first initializing drain electrode D4 of the first initializing thin film transistor T4 is connected to the bottom electrode Cst1 of the storage capacitor Cst, the compensating drain electrode D3 of the compensating thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initializing thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and may perform an initializing operation of transmitting an initializing voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1, thereby initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

The emission-control gate electrode G6 of the emission-control thin film transistor T6 is connected to the emission control line EL, the emission-control source electrode S6 of the emission-control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission-control drain electrode D6 of the emission-control thin film transistor T6 is connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

The operation control thin film transistor T5 and the emission control thin film transistor T6 are concurrently (or simultaneously) turned on in response to the emission control signal En transmitted through the emission control line EL to transmit the driving voltage ELVDD to the organic light emitting diode OLED, thereby causing the driving current I_OLEDFlows through the organic light emitting diode OLED.

The second initializing gate electrode G7 of the second initializing thin film transistor T7 is connected to the previous scan line SL-1, the second initializing source electrode S7 of the second initializing thin film transistor T7 is connected to the emission controlling drain electrode D6 of the emission controlling thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initializing drain electrode D7 of the second initializing thin film transistor T7 is connected to the first initializing source electrode S4 of the first initializing thin film transistor T4 and the initializing voltage line VL. The second initializing thin film transistor T7 is turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1 and may initialize the pixel electrode of the organic light emitting diode OLED.

Although fig. 5 illustrates a case where the first and second initializing thin film transistors T4 and T7 are connected to the previous scan line SL-1, the embodiment is not limited thereto. According to some example embodiments, the first initializing thin film transistor T4 may be connected to a previous scan line SL-1 and may be driven in response to a previous scan signal Sn-1, and the second initializing thin film transistor T7 may be connected to a separate signal line (e.g., a next scan line) and may be driven in response to a signal transmitted through the separate signal line.

The top electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED is connected to the common voltage. Accordingly, the organic light emitting diode OLED may receive the driving current I from the driving thin film transistor T1_OLEDAnd emits light, thereby displaying an image.

Although it is illustrated in fig. 5 that the compensating thin film transistor T3 and the first initializing thin film transistor T4 each have a double gate electrode, the compensating thin film transistor T3 and the first initializing thin film transistor T4 each may have one gate electrode.

Fig. 6 is a plan view of the display device 1 according to the embodiment. For example, fig. 6 is an enlarged view of an area AA of a rounded corner portion DA-C of the display area DA in the display device 1 according to the embodiment. Although it is illustrated in fig. 6 that the first fan-out section 165 includes the first fan-out line 166 and the second fan-out line 167, the first fan-out section 165 may include a plurality of fan-out lines. In addition, although it is illustrated in fig. 6 that the second fan-out part 175 includes the third fan-out line 176 and the fourth fan-out line 177, the second fan-out part 175 may include a plurality of fan-out lines.

According to some example embodiments, the display apparatus 1 may include: a substrate 100 including a display area DA including a first display area DA1 and a second display area DA2, and a peripheral area PA located outside the display area DA; a first fan-out section 165, a second fan-out section 175, the first fan-out section 165 being disposed in a portion of the peripheral area PA located outside the first display area DA1, and the second fan-out section 175 being disposed outside the first fan-out section 165; a first power supply line 160 and a second power supply line 170, the first power supply line 160 being disposed in the peripheral area PA corresponding to one side of the display area DA and overlapping a portion of the first fan-out section 165, and the second power supply line 170 being disposed in the peripheral area PA located outside the display area DA and overlapping at least a portion of the second fan-out section 175.

The driving circuit 120 may be disposed between the first and second fan-out portions 165 and 175 corresponding to the first display region DA1, and may be disposed between the second display region DA2 and the second fan-out portion 175 corresponding to the second display region DA 2. The driving circuit 120 may include a first sub driving circuit 121 and a second sub driving circuit 122 each disposed between the first and second fan-out sections 165 and 175 and corresponding to the first display region DA1, the first sub driving circuit 121 being spaced apart from the second sub driving circuit 122. The driving circuit 120 may include a third sub driving circuit 123 and a fourth sub driving circuit 124 each disposed between the second display area DA2 and the second fan-out portion 175 and corresponding to the second display area DA2, the third sub driving circuit 123 being spaced apart from the fourth sub driving circuit 124.

According to some example embodiments, the first sub driving circuit 121 may be spaced apart from the second sub driving circuit 122 between the first and second fan-out sections 165 and 175 corresponding to the first display area DA 1. The first sub driving circuit 121 may be spaced apart from the second sub driving circuit 122. The second sub driving circuit 122 may be spaced apart from the first sub driving circuit 121. For example, the first sub driving circuit 121 and the second sub driving circuit 122 may be repeatedly spaced apart from each other. In addition, as with the first and second sub driving circuits 121 and 122, the third and fourth sub driving circuits 123 and 124 may be repeatedly spaced apart from each other between the second display area DA2 and the second fan-out portion 175 corresponding to the second display area DA 2.

The sub-driving circuits corresponding to the second display area DA2 and included in the driving circuit 120 disposed in the peripheral area PA may be spaced apart from each other. The sub-driving circuits corresponding to the first display area DA1 and included in the driving circuit 120 disposed in the peripheral area PA may be spaced apart from each other. The separation interval of the sub driving circuits may gradually increase from the peripheral area PA corresponding to the second display area DA2 toward the peripheral area PA corresponding to the first display area DA 1.

The plurality of scan lines SL may be arranged in the display area DA, and may extend in a second direction (x direction) crossing the first direction (y direction). The driving circuit 120 may transmit a scan signal to each pixel P through a plurality of scan lines SL, and may transmit an emission control signal to each pixel P through a plurality of emission control lines EL.

The first power line 160 may be connected to each pixel P through the driving voltage line PL and may supply a first power voltage to the pixel P, and the second power line 170 may be connected to each pixel P and may supply a second power voltage to the pixel P. In this case, the first power supply voltage may include the driving voltage ELVDD, and the second power supply voltage may include the common voltage ELVSS.

The first fan-out part 165 may include first and second fan-out lines 166 and 167, and the second fan-out part 175 may include third and fourth fan-out lines 176 and 177.

As shown in fig. 6, the third fan-out line 176 may pass between the third sub-driving circuit 123 and the fourth sub-driving circuit 124. Although it is illustrated in fig. 6 that the third fan-out line 176 passes between the third sub-driving circuit 123 and the fourth sub-driving circuit 124, the embodiment is not limited thereto. The plurality of fan-out lines connected to the plurality of second data lines DL2 disposed in the second display area DA2 may pass between the plurality of sub driving circuits disposed between the second display area DA2 and the second fan-out portion 175 and be spaced apart from each other. The plurality of fan-out lines connected to the plurality of first data lines DL1 disposed in the first display area DA1 may pass between the plurality of sub driving circuits disposed between the first display area DA1 and the second display area DA2 and be spaced apart from each other.

According to some example embodiments, the display device 1 may include a plurality of first data lines DL1 arranged in the first display area DA1 and extending in the first direction (y direction). The first and second fanout lines 166 and 167 may supply a data signal to the pixels P through the plurality of first data lines DL 1. In addition, the display device 1 may include a plurality of second data lines DL2 arranged in the second display area DA2 and extending in the first direction (y direction). The third and fourth fanout lines 176 and 177 may supply data signals to the pixels P through the plurality of second data lines DL 2.

Fig. 7 is a sectional view of the display device 1 taken along line I-I' of fig. 6. For example, fig. 7 is a view for explaining a stacking order of one pixel P of the display device 1 according to the embodiment.

Referring to fig. 7, the display apparatus 1 according to some example embodiments may include a substrate 100, a thin film transistor TFT disposed over the substrate 100, an organic light emitting diode OLED connected to and disposed over the thin film transistor TFT, and a thin film encapsulation layer TFE disposed on the organic light emitting diode OLED.

The substrate 100 may include glass or polymer resin. The polymer resin may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 comprising the polymer resin may be flexible, crimpable, or bendable. The substrate 100 may have a multi-layer structure including a layer including the above polymer resin and an inorganic layer. According to some example embodiments, the substrate 100 may include a flexible substrate.

The buffer layer 101 is positioned on the substrate 100, may reduce or block penetration of foreign substances, moisture, or external air from below the substrate 100, and provides a flat surface on the substrate 100. The buffer layer 101 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic/inorganic composite material, and may include a single layer or a plurality of layers including the inorganic material and the organic material. A barrier layer blocking permeation of external air may be further disposed between the substrate 100 and the buffer layer 101. The buffer layer 101 may be disposed over the display area DA and the peripheral area PA.

A thin film transistor TFT, a storage capacitor Cst, and an organic light emitting diode OLED may be disposed over the substrate 100, the thin film transistor TFT being disposed at a position corresponding to the display area DA, and the organic light emitting diode OLED being electrically connected to the thin film transistor TFT and the storage capacitor Cst. The thin film transistor TFT of fig. 7 may correspond to one of the thin film transistors of the pixel circuit PC described with reference to fig. 5, for example, the driving thin film transistor T1.

The thin film transistor TFT may include a semiconductor layer 134, a gate electrode 136, a source electrode 137, and a drain electrode 138. The semiconductor layer 134 may include a channel region 131, a source region 132, and a drain region 133, the channel region 131 overlapping with the gate electrode 136, and the source region 132 and the drain region 133 being disposed at two opposite sides of the channel region 131 and including impurities having a concentration higher than that of the channel region 131. Here, the impurity may include an N-type impurity or a P-type impurity. The source region 132 and the drain region 133 may be electrically connected to a source electrode 137 and a drain electrode 138 of the thin film transistor TFT, respectively.

The semiconductor layer 134 may include an oxide semiconductor and/or a silicon semiconductor. In the case where the semiconductor layer 134 includes an oxide semiconductor, the semiconductor layer 134 may include, for example, an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the semiconductor layer 134 may include itzo (insnzno), igzo (ingazno), or the like. In the case where the semiconductor layer 134 includes a silicon semiconductor, the semiconductor layer 134 may include, for example, amorphous silicon (a-Si) or Low Temperature Polysilicon (LTPS) in which amorphous silicon (a-Si) is crystallized.

The gate electrode 136 may include a single layer or a plurality of layers including at least one metal of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 136 may be connected to a gate line that applies an electrical signal to the gate electrode 136. According to some example embodiments, the gate electrode 136 may include the same material as that of the first, second, third, and fourth fanout lines 166, 167, 176, and 177.

Since the gate insulating layer 103 is disposed between the semiconductor layer 134 and the gate electrode 136, the semiconductor layer 134 can be insulated from the gate electrode 136. The gate insulating layer 103 may comprise at least one inorganic insulating material comprising silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) And zinc oxide (ZnO)₂). The gate insulating layer 103 may include a single layer or a plurality of layers including the above inorganic insulating material.

The storage capacitor Cst may include a bottom electrode 144 and a top electrode 146 positioned over the bottom electrode 144. The bottom electrode 144 of the storage capacitor Cst may overlap with the top electrode 146 of the storage capacitor Cst. According to some example embodiments, the first fanout line 166, the second fanout line 167, the third fanout line 176, and the fourth fanout line 177 may include the same material as that of the bottom electrode 144 or the top electrode 146, and may be disposed on the same layer as that on which the bottom electrode 144 or the top electrode 146 is disposed.

The first interlayer insulating layer 105 may be disposed between the bottom electrode 144 and the top electrode 146. The first interlayer insulating layer 105 is a layer having a dielectric constant (e.g., a set or predetermined dielectric constant), and the first interlayer insulating layer 105 may include a material including silicon oxynitride (SiON), silicon oxide (SiO)_x) And/or silicon nitride (SiN)_x) And the first interlayer insulating layer 105 may include a single layer or a plurality of layers.

Although it is illustrated in fig. 7 that the storage capacitor Cst overlaps the thin film transistor TFT and the bottom electrode 144 is integrated with the gate electrode 136 of the thin film transistor TFT, in an embodiment, the storage capacitor Cst may not overlap the thin film transistor TFT and the bottom electrode 144 may be a separate element from the gate electrode 136 of the thin film transistor TFT.

The second interlayer insulating layer 107 may be disposed on the top electrode 146 of the storage capacitor Cst. The second interlayer insulating layer 107 may include silicon oxide (SiO)₂)、Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂) And may include a single layer or multiple layers.

The source electrode 137 and the drain electrode 138 may be disposed on the second interlayer insulating layer 107. The source and drain electrodes 137 and 138 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or a plurality of layers including the above materials. Each of the source electrode 137 and the drain electrode 138 may include a stacked structure of Ti/Al/Ti. According to some example embodiments, the source and drain electrodes 137 and 138 may include the same material as that of the first and second power lines 160 and 170.

The first and second planarization layers 111 and 113 may be disposed on the source and drain electrodes 137 and 138. The first and second planarization layers 111 and 113 may planarize a top surface of the pixel circuit PC to planarize a surface on which the organic light emitting diode OLED is to be positioned.

The first and second planarization layers 111 and 113 may include: general-purpose polymers such as benzocyclobutene (BCB), polyimide, Hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or Polystyrene (PS), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. The first and second planarization layers 111 and 113 may include an inorganic material. The first and second planarization layers 111 and 113 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO)₂). In the case where the first planarizing layer 111 and the second planarizing layer 113 include an inorganic material, chemical planarization polishing may be performed as appropriate. The first and second planarizing layers 111 and 113 may be wrappedIncluding both organic and inorganic materials.

The organic light emitting diode OLED may be positioned on the second planarization layer 113 in the display area DA of the substrate 100, and includes a pixel electrode 210, an intermediate layer 220, and an opposite electrode 230, the opposite electrode 230 facing the pixel electrode 210, the intermediate layer 220 being interposed between the opposite electrode 230 and the pixel electrode 210.

The pixel electrode 210 may be disposed on the second planarization layer 113. The pixel electrode 210 may include a (semi) transparent electrode or a reflective electrode. According to some example embodiments, the pixel electrode 210 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semitransparent electrode layer on the reflective layer. The transparent or semitransparent electrode layer may include Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) At least one of Indium Gallium Oxide (IGO) and Aluminum Zinc Oxide (AZO). According to some example embodiments, the pixel electrode 210 may have a stacked structure of ITO/Ag/ITO.

The pixel defining layer 180 may be disposed on the second planarization layer 113. The pixel defining layer 180 may define an emission area of the pixel by including an opening exposing a central portion of the pixel electrode 210. In addition, the pixel defining layer 180 may prevent an arc or the like from occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the opposite electrode 230 located above the pixel electrode 210. The pixel defining layer 180 may include an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, or phenolic resin. The pixel defining layer 180 may be formed by a method such as spin coating.

The spacer may be disposed on the pixel defining layer 180. The spacer may prevent the organic light emitting diode OLED from being damaged due to sagging of the mask during a manufacturing process using the mask. The spacer may include a single layer or multiple layers containing an organic insulating material such as polyimide, polyamide, acrylic, BCB, HMDSO, or phenolic resin. The spacers may be formed by a method such as spin coating.

The intermediate layer 220 may be disposed on a portion of the pixel electrode 210 exposed by the pixel defining layer 180. The intermediate layer 220 may include an emission layer, and may further include functional layers including a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) under and on the emission layer.

The emission layer may include an organic material containing a fluorescent or phosphorescent material emitting red, green, blue or white light. The emissive layer may comprise a low molecular weight organic material or a polymeric organic material.

In the case where the emission layer includes a low molecular weight material, the intermediate layer 220 may have a structure in which an HIL, an HTL, an emission layer (EML), an ETL, an EIL, etc. are stacked in a single configuration or a composite configuration. The intermediate layer 220 may include, for example, copper phthalocyanine (CuPc), N '-di (naphthalene-1-yl) -N, N' -diphenyl-benzidine (NPB), or tris-8-hydroxyquinoline aluminum (Alq)₃) As the low molecular weight material. These layers may be formed by vacuum deposition.

In the case where the emission layer includes a polymer material, the intermediate layer 220 may have a structure generally including an HTL and an EML. In this case, the HTL may include poly (3, 4-ethylenedioxythiophene) (PEDOT), and the EML may include a polymer material such as a polyphenylene ethylene (PPV) -based material or a polyfluorene-based material. The emission layer may be formed by screen printing, inkjet printing, Laser Induced Thermal Imaging (LITI), or the like.

The pixel electrode 210 may be provided as a plurality of pixel electrodes 210, and the intermediate layer 220 may be arranged to correspond to each pixel electrode 210 of the plurality of pixel electrodes 210. However, the embodiments are not limited thereto. The intermediate layer 220 may include a layer integrated over the plurality of pixel electrodes 210. Various modifications may be made. According to some example embodiments, the intermediate layer 220 may be arranged to correspond to each of the plurality of pixel electrodes 210, and functional layers other than the intermediate layer 220 may be provided as one body over the plurality of pixel electrodes 210.

The opposite electrode 230 may be disposed on the intermediate layer 220. The opposite electrode 230 may be disposed on the intermediate layer 220, and may completely cover the intermediate layer 220. The opposite electrode 230 may be disposed in the display area DA, and may be disposed on the entire surface of the display area DA. That is, the opposite electrode 230 may be provided in one body to cover a plurality of pixels.

The opposite electrode 230 may include a transparent electrode or a reflective electrode. According to some example embodiments, the opposite electrode 230 may be a transparent or semi-transparent electrode, and may include a thin metal layer having a small work function and including at least one of lithium (Li), calcium (Ca), lithium fluoride (LiF)/Ca, LiF/aluminum (Al), Al, silver (Ag), magnesium (Mg), and a compound thereof. In addition, a Transparent Conductive Oxide (TCO) layer including ITO, IZO, ZnO, or In may be further disposed on the thin metal layer₂O₃。

In the case where the pixel electrode 210 includes a reflective electrode and the opposite electrode 230 includes a transparent electrode, light emitted from the intermediate layer 220 is emitted toward the opposite electrode 230, and thus, the display apparatus 1 may be a top emission type display apparatus. According to some example embodiments, in a case where the pixel electrode 210 includes a transparent or semi-transparent electrode and the opposite electrode 230 includes a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and thus, the display apparatus 1 may be a bottom emission type display apparatus. However, the present embodiment is not limited thereto, and the display device 1 according to some example embodiments may be a dual emission type display device that emits light in two directions including a top side and a bottom side of the display device 1.

A thin film encapsulation layer TFE may be disposed on the opposite electrode 230 to protect the organic light emitting diode OLED from external moisture and oxygen. The thin film encapsulation layer TFE may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. The thin film encapsulation layer TFE may entirely cover the display area DA, and may extend to the peripheral area PA to cover a portion of the peripheral area PA.

The thin film encapsulation layer TFE may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320, the second inorganic encapsulation layer 330 being disposed over the first inorganic encapsulation layer 310, and the organic encapsulation layer 320 being interposed between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330.

The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Zinc oxide (ZnO)₂) Silicon oxide (SiO)₂) Silicon nitride (SiN)_x) And silicon oxynitride (SiON). The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include a single layer or a plurality of layers including the above materials. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include the same material or different materials.

The organic encapsulation layer 320 may include a monomer-based material or a polymer-based material. The organic encapsulation layer 320 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinylsulfonate, polyoxymethylene, polyacrylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

Fig. 8A to 8C are sectional views of the display device 1 taken along the line II-II' of fig. 6. For example, fig. 8A is a view illustrating that the first and second fan-out lines 166 and 167 included in the first fan-out section 165 overlap at least a portion of the first power line 160 in the display device 1 according to some example embodiments, fig. 8B is a view illustrating that the first and second fan-out lines 166 and 167 included in the first fan-out section 165 are alternately arranged in the display device 1 according to some example embodiments, and fig. 8C is a view illustrating that the first fan-out line 166 is electrically connected to the first data line DL1 through the contact hole CNT in the display device 1 according to embodiments.

The buffer layer 101, the gate insulating layer 103, the first interlayer insulating layer 105, the second interlayer insulating layer 107, the first planarizing layer 111, and the second planarizing layer 113, each of which is disposed in the display area DA, may extend to the peripheral area PA.

Referring to fig. 8A, a buffer layer 101 may be disposed on a substrate 100, a gate insulating layer 103 may be disposed on the buffer layer 101, and a first fanout line 166 and a second fanout line 167 may be disposed on the gate insulating layer 103. The first and second fanout lines 166 and 167 may supply a data signal to each pixel P in the first display area DA1 through the first data line DL 1. According to some example embodiments, the first and second fanout lines 166 and 167 may include the same material as that of the gate electrode 136.

The first interlayer insulating layer 105 may be disposed on the first and second fanout lines 166 and 167, the second interlayer insulating layer 107 may be disposed on the first interlayer insulating layer 105, and the first power line 160 may be disposed on the second interlayer insulating layer 107. The first power line 160 may supply the first power voltage to each pixel P through the driving voltage line PL. According to some example embodiments, the first power line 160 may include the same material as that of the source and drain electrodes 137 and 138. The first planarization layer 111 may be disposed on the first power line 160.

The first fanout line 166 may be insulated from the first power line 160 by the first interlayer insulating layer 105 and the second interlayer insulating layer 107. The first fanout line 166 may overlap at least a portion of the first power line 160 over the substrate 100.

The second fanout line 167 may be insulated from the first power line 160 by the first interlayer insulating layer 105 and the second interlayer insulating layer 107. The second fanout line 167 may overlap at least a portion of the first power line 160 over the substrate 100.

Referring to fig. 8B, the first fan-out section 165 may include first and second fan-out lines 166 and 167 respectively arranged on different layers above the substrate 100. The first fanout lines 166 and the second fanout lines 167 may be alternately arranged. For example, the first fan-out section 165 may include a first fan-out line 166 disposed on the gate insulating layer 103 and a second fan-out line 167 disposed on the first interlayer insulating layer 105. The first and second fanout lines 166 and 167 may be alternately arranged over the substrate 100. Since the first and second fanout lines 166 and 167 may be alternately and respectively disposed on different layers, the area of the peripheral area PA, i.e., dead space (dead space), may be reduced. Although it is illustrated in fig. 8B that the first fanout line 166 is disposed on the gate insulating layer 103 and the second fanout line 167 is disposed on the first interlayer insulating layer 105, the embodiment is not limited thereto. According to some example embodiments, the first fanout line 166 may be disposed on the first interlayer insulating layer 105, and the second fanout line 167 may be disposed on the gate insulating layer 103.

Referring to fig. 8C, a buffer layer 101 may be disposed on the substrate 100, a gate insulating layer 103 may be disposed on the buffer layer 101, and a first fanout line 166 may be disposed on the gate insulating layer 103. The first interlayer insulating layer 105 may be disposed on the first fanout line 166, the second interlayer insulating layer 107 may be disposed on the first interlayer insulating layer 105, and the first data line DL1 and the first power line 160 may be disposed on the second interlayer insulating layer 107. The first data line DL1 may be electrically connected to the first fanout line 166 through a contact hole CNT passing through the first and second interlayer insulating layers 105 and 107. The first power line 160 may overlap at least a portion of the first fanout line 166, and the first and second interlayer insulating layers 105 and 107 are interposed between the first power line 160 and the first fanout line 166.

Fig. 9A and 9B are sectional views of the display device 1 taken along the line III-III' of fig. 6. For example, fig. 9A is a view illustrating that the third and fourth fan-out lines 176 and 177 included in the second fan-out section 175 overlap at least a portion of the second power supply line 170 in the display device 1 according to some example embodiments, and fig. 9B is a view illustrating that the third and fourth fan-out lines 176 and 177 included in the second fan-out section 175 are alternately arranged in the display device 1 according to the embodiment.

Referring to fig. 9A, a buffer layer 101 may be disposed on a substrate 100, a gate insulating layer 103 may be disposed on the buffer layer 101, and third and fourth fan-out lines 176 and 177 may be disposed on the gate insulating layer 103. The third and fourth fan-out lines 176 and 177 may supply a data signal to each pixel in the second display area DA2 through the second data line DL 2. According to some example embodiments, the third and fourth fanout lines 176 and 177 may include the same material as that of the gate electrode 136.

The first interlayer insulating layer 105 may be disposed on the third and fourth fanout lines 176 and 177, the second interlayer insulating layer 107 may be disposed on the first interlayer insulating layer 105, and the second power line 170 may be disposed on the second interlayer insulating layer 107. The second power line 170 may supply a second power voltage to each pixel. According to some example embodiments, the second power line 170 may include the same material as that of the source and drain electrodes 137 and 138. The first planarization layer 111 may be disposed on the second power line 170.

The third fanout line 176 may be insulated from the second power line 170 by the first and second interlayer insulating layers 105 and 107. The third fanout line 176 may overlap at least a portion of the second power line 170 over the substrate 100.

The fourth fanout line 177 may be insulated from the second power line 170 by the first and second interlayer insulating layers 105 and 107. The fourth fanout line 177 may overlap at least a portion of the second power line 170 over the substrate 100.

Referring to fig. 9B, the second fan-out section 175 may include third and fourth fan-out lines 176 and 177 respectively arranged on different layers above the substrate 100. The third and fourth fanout lines 176 and 177 may be alternately arranged. For example, the second fan-out section 175 may include a third fan-out line 176 disposed on the gate insulating layer 103 and a fourth fan-out line 177 disposed on the first interlayer insulating layer 105. The third and fourth fanout lines 176 and 177 may be alternately arranged over the substrate 100. Since the third and fourth fan-out lines 176 and 177 are alternately and respectively arranged on different layers, the area of the peripheral area PA, that is, the dead space, can be reduced. Although it is illustrated in fig. 9B that the third fan-out line 176 is disposed on the gate insulating layer 103 and the fourth fan-out line 177 is disposed on the first interlayer insulating layer 105, the embodiment is not limited thereto. According to some example embodiments, the third fan-out line 176 may be disposed on the first interlayer insulating layer 105, and the fourth fan-out line 177 may be disposed on the gate insulating layer 103.

Fig. 10 is a sectional view of the display device 1 taken along a line IV-IV 'of fig. 6, and fig. 11 is a sectional view of the display device 1 taken along a line V-V' of fig. 6. For example, fig. 10 and 11 are views for explaining a separation interval between the first sub driving circuit 121 and the second sub driving circuit 122 included in the driving circuit 120 and a separation interval between the third sub driving circuit 123 and the fourth sub driving circuit 124 included in the driving circuit 120 in the display device 1 according to the embodiment.

Referring to fig. 10, the driving circuit 120 may include a first sub-driving circuit 121 and a second sub-driving circuit 122. Each of the first and second sub driving circuits 121 and 122 may include a thin film transistor TFT and a wiring connected to the thin film transistor TFT. The thin film transistor TFT may be formed during the same process as that of forming the thin film transistor TFT of the pixel circuit PC. The thin film transistor TFT may include a semiconductor layer a, a gate electrode G, a source electrode S, and a drain electrode D.

The first sub driving circuit 121 and the second sub driving circuit 122 may be spaced apart from each other. For example, the first sub driving circuit 121 and the second sub driving circuit 122 may be spaced apart from each other by a first distance d1 above the substrate 100.

Referring to fig. 11, the driving circuit 120 may include a third sub-driving circuit 123 and a fourth sub-driving circuit 124. Each of the third sub-driving circuit 123 and the fourth sub-driving circuit 124 may include a thin film transistor TFT and a wiring connected to the thin film transistor TFT. The thin film transistor TFT may include a semiconductor layer a, a gate electrode G, a source electrode S, and a drain electrode D.

The third sub driving circuit 123 and the fourth sub driving circuit 124 may be spaced apart from each other. For example, the third sub driving circuit 123 and the fourth sub driving circuit 124 may be spaced apart from each other by a second distance d2 above the substrate 100. The third fan-out line 176 may be disposed between the third sub-driving circuit 123 and the fourth sub-driving circuit 124, the third fan-out line 176 being connected to the second data line DL2 disposed in the second display area DA 2.

The first distance d1, which is a separation distance between the first sub driving circuit 121 and the second sub driving circuit 122, may be greater than the second distance d2, which is a separation distance between the third sub driving circuit 123 and the fourth sub driving circuit 124. For example, the separation distance between the sub driving circuits disposed in the peripheral area PA corresponding to the first display area DA1 and the second display area DA2 may gradually increase from the peripheral area PA corresponding to the second display area DA2 toward the peripheral area PA corresponding to the first display area DA 1.

In order to solve the problem that the dead space of the corner portion is larger than that of the straight line portion in the display device according to the related art, some example embodiments provide a display device in which a peripheral area is minimized or reduced because the power supply line overlaps the fanout line of the corner portion, and thus, the space may be efficiently utilized.

According to the embodiment having the above-described configuration, a display device including a minimized peripheral area in which the power supply line overlaps the fanout line of the corner portion can be realized. However, the scope of the embodiments according to the present disclosure is not limited by this effect.

It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the present disclosure and equivalents thereof.