阅读说明：本技术 显示装置 (Display device ) 是由 李时圭 金荣浩 李雄起 于 2020-09-10 设计创作，主要内容包括：根据本公开的示例性实施例的显示装置包括：基板,在基板中限定有多个子像素,多个子像素中的每一个子像素包括发射区域和电路区域；驱动晶体管,其设置在电路区域中,并且包括设置在相同的层上的第一栅极电极和第一源极电极；存储电容器,其设置在电路区域中,并且包括电连接到第一栅极电极并设置在第一栅极电极下方的第一电容器电极；绝缘层,其使驱动晶体管和存储电容器的上部平坦化；以及发光元件,其设置在绝缘层上。因此,通过将电连接到第一栅极电极的第一电容器电极设置在第一栅极电极下方,可以使第一电容器电极与发光元件之间的寄生电容最小化。(A display device according to an exemplary embodiment of the present disclosure includes: a substrate in which a plurality of sub-pixels are defined, each of the plurality of sub-pixels including an emission region and a circuit region; a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor disposed in the circuit region and including a first capacitor electrode electrically connected to and disposed below the first gate electrode; an insulating layer which planarizes upper portions of the driving transistor and the storage capacitor; and a light emitting element provided on the insulating layer. Therefore, by disposing the first capacitor electrode electrically connected to the first gate electrode below the first gate electrode, parasitic capacitance between the first capacitor electrode and the light emitting element can be minimized.)

1. A display device, comprising:

a substrate in which a plurality of sub-pixels are defined, and each of the sub-pixels includes an emission region and a circuit region;

a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer;

a storage capacitor that is disposed in the circuit region and includes a first capacitor electrode that is electrically connected to and disposed below the first gate electrode;

an insulating layer planarizing upper portions of the driving transistor and the storage capacitor; and

a light emitting element disposed on the insulating layer.

2. The display device according to claim 1, wherein the first capacitor electrode overlaps with the first source electrode, and

the storage capacitor further includes a second capacitor electrode integrally formed with the first source electrode.

3. The display device according to claim 2, wherein the second capacitor electrode is provided over the first capacitor electrode.

4. The display device according to claim 1, wherein the light-emitting element comprises:

a first electrode disposed in the emission region and on the insulating layer;

a light emitting layer covering the entire emission region and the circuit region and disposed on the first electrode; and

a second electrode covering the entire emission region and the circuit region and disposed on the light emitting layer,

wherein a portion of the upper surface of the insulating layer, which does not contact the first electrode, is in contact with the light emitting element.

5. The display device according to claim 4, wherein the first electrodes disposed in the plurality of sub-pixels are spaced apart from each other, and

the light emitting layer is disposed between the first electrodes spaced apart from each other.

6. The display device according to claim 4, wherein the light-emitting element further comprises an extending portion extending from the first electrode of the emission region toward the first source electrode of the circuit region.

7. The display device according to claim 4, wherein the light-emitting element further comprises a repair portion extending from the first electrode provided in one of the plurality of sub-pixels toward the circuit region of another sub-pixel adjacent to the one sub-pixel.

8. The display device according to claim 1, further comprising:

a light blocking layer disposed between the substrate and the first active layer of the drive transistor, an

A first capacitor electrode disposed on the same layer as the light blocking layer.

9. The display device according to claim 8, further comprising:

a switching transistor disposed in the circuit region and including a second source electrode electrically connected to the first gate electrode and the first capacitor electrode;

a sense transistor disposed in the circuit region and including a third source electrode electrically connected to the drive transistor, the storage capacitor, and the light emitting element;

a gate line electrically connected to a second gate electrode of the switching transistor;

a data line electrically connected to the second drain electrode of the switching transistor;

a high potential power supply line electrically connected to the first drain electrode of the driving transistor;

a sensing line electrically connected to a third gate electrode of the sensing transistor; and

a reference line electrically connected to a third drain electrode of the sense transistor,

wherein the data line, the high-potential power supply line, and the sense line are disposed to extend along a column line on the same layer as the light blocking layer, and

wherein the gate line and the reference line are disposed to extend in a row direction on the same layer as the first gate electrode.

10. The display device according to claim 1, further comprising:

a first color filter disposed between the insulating layer in the emission region of one of the plurality of sub-pixels and the substrate, and between the insulating layer in the circuit region of the one sub-pixel and the driving transistor; and

a second color filter disposed between the insulating layer in the emission region of another sub-pixel of the plurality of sub-pixels and the substrate, and between the insulating layer in the circuit region of the one sub-pixel and the first color filter.

11. The display device according to claim 10, wherein the first capacitor electrode, the first color filter, and the second color filter overlap with each other in the circuit region of the one sub-pixel.

12. A display device, comprising:

a substrate in which a plurality of sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel are defined;

a first capacitor electrode disposed in each of the plurality of sub-pixels;

a driving transistor disposed in each of the plurality of sub-pixels and including a first gate electrode electrically connected to the first capacitor electrode and a first source electrode disposed on the first capacitor electrode; and

a light emitting element including a plurality of anodes disposed on the driving transistor in each of the plurality of sub-pixels, and a cathode and a light emitting layer disposed on the entire plurality of sub-pixels to cover the plurality of anodes,

wherein a portion of a lower surface of the light emitting layer is disposed on the same plane as lower surfaces of the plurality of anodes.

13. The display device of claim 12, wherein each of the plurality of sub-pixels further comprises:

an emission region in which the plurality of anodes are disposed; and

a circuit region in which the driving transistor and the first capacitor electrode are disposed,

wherein the light emitting element further includes an extension portion extending from each of the plurality of anodes toward the driving transistor.

14. The display device according to claim 13, wherein the light-emitting element further comprises a repair portion extending from an anode of the plurality of anodes provided in the red sub-pixel toward another red sub-pixel adjacent to the red sub-pixel.

15. The display device according to claim 13, further comprising:

a red color filter disposed in the emission area of the red sub-pixel in the emission area and in the circuit area of each of the plurality of sub-pixels;

a blue color filter disposed in the emission region of the blue sub-pixel in the emission region and in the circuit region of each of the plurality of sub-pixels; and

a green color filter disposed in the emission region of the green sub-pixel in the emission region,

wherein, in the circuit region of each of the plurality of sub-pixels, the red color filter and the blue color filter overlap each other.

16. The display device according to claim 15, wherein the red color filter and the blue color filter have a mesh shape, and

wherein the green color filter has an island shape.

17. The display device according to claim 15, wherein the first capacitor electrode and the first source electrode constitute a storage capacitor, and

the first source electrode, the red color filter, and the blue color filter are disposed between the first capacitor electrode and the cathode.

18. The display device according to claim 12, wherein the first capacitor electrode is provided closest to the substrate among conductive members provided on the substrate.

Technical Field

The present disclosure relates to a display device, and more particularly, to a display device for minimizing parasitic capacitance between a storage capacitor and a cathode.

Background

Display devices for computer monitors, TVs, and mobile phones include organic light emitting display devices (OLEDs) that emit light by themselves, Liquid Crystal Display (LCD) devices that require a separate light source, and the like.

Such display devices are being applied to more and more various fields including not only computer monitors and TVs but also personal mobile devices, and thus, display devices having a reduced volume and weight while having a wide display area are being researched.

Meanwhile, the display device includes a plurality of sub-pixels and banks disposed between the plurality of sub-pixels to reduce color mixing between the plurality of sub-pixels. However, an additional process is required to form the banks, and there is a problem in that moisture permeates into the display device through the banks formed of an organic material. Therefore, in order to simplify the process and minimize moisture permeation, a display device in which such banks are removed is being studied.

Disclosure of Invention

An object to be achieved by the present disclosure is to provide a display device in which a decrease in light emission efficiency due to removal of banks is minimized.

Another object to be achieved by the present disclosure is to provide a display device in which a parasitic capacitance between a storage capacitor and a cathode is minimized.

Another object to be achieved by the present disclosure is to provide a display device in which leakage of light emitted from each of a plurality of sub-pixels is minimized.

The object of the present disclosure is not limited to the above object, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels are defined, each of the plurality of sub-pixels including an emission region and a circuit region; a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor disposed in the circuit region and including a first capacitor electrode electrically connected to and disposed below the first gate electrode; an insulating layer which planarizes upper portions of the driving transistor and the storage capacitor; and a light emitting element provided on the insulating layer. Therefore, by disposing the first capacitor electrode electrically connected to the first gate electrode below the first gate electrode, parasitic capacitance between the first capacitor electrode and the light emitting element can be minimized.

According to another aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel are defined; a first capacitor electrode disposed in each of the plurality of sub-pixels; a driving transistor disposed in each of the plurality of sub-pixels and including a first gate electrode electrically connected to the first capacitor electrode and a first source electrode disposed on the first capacitor electrode; and a light emitting element including a plurality of anodes disposed on the driving transistor in each of the plurality of sub-pixels, and a cathode and a light emitting layer disposed on the entire plurality of sub-pixels to cover the plurality of anodes, wherein a portion of a lower surface of the light emitting layer is disposed on the same plane as a corresponding lower surface of the plurality of anodes. Accordingly, it is possible to minimize distortion of a data signal due to parasitic capacitance between the cathode and the storage capacitor while simplifying the process by removing the bank.

Other details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

According to the present disclosure, by minimizing the anode disposed in the circuit region, it is possible to minimize the occurrence of light leakage and color coordinate distortion through the circuit region.

According to the present disclosure, by reducing the arrangement area of the anode in the circuit region, power consumption can be reduced and color coordinate distortion can be minimized.

According to the present disclosure, by disposing the first capacitor electrode connected to the first gate electrode of the first transistor among the electrodes of the storage capacitor below the first gate electrode, the parasitic capacitance between the first capacitor electrode and the cathode can be reduced.

According to the present disclosure, by disposing a plurality of color filters between the storage capacitor and the cathode, distortion of the data signal due to parasitic capacitance between the storage capacitor and the cathode may be minimized.

The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in the present specification.

Drawings

The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

fig. 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

FIG. 3 is an enlarged plan view of region A of FIG. 1;

FIG. 4 is a cross-sectional view taken along line IV-IV' of FIG. 3;

fig. 5 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure; and

fig. 6 is a sectional view taken along line VI-VI' of fig. 5.

Detailed Description

Advantages and features of the present disclosure and methods of accomplishing the same will become apparent by reference to the following detailed description of exemplary embodiments and the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be embodied in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully appreciate the disclosure of the present disclosure and the scope of the present disclosure. Accordingly, the disclosure is to be limited only by the scope of the following claims.

Shapes, sizes, ratios, angles, numbers, and the like shown in the drawings for describing exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally refer to like elements throughout the specification. Furthermore, in the following description of the present disclosure, a detailed explanation of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising," having, "and" consisting of …, "as used herein, are generally intended to allow for the addition of other components, unless these terms are used with the term" only. Any reference to the singular may include the plural unless explicitly stated otherwise.

Components are to be construed as including ordinary error ranges even if not explicitly stated.

When terms such as "on … …," "above … …," "below … …," and "next" are used to describe a positional relationship between two components, one or more components may be located between the two components unless these terms are used with the terms "immediately" or "directly".

When an element or layer is "on" another element or layer, the other layer or layer may be directly on the other element or intervening elements may be present.

Although the terms "first," "second," etc. are used to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

Like reference numerals generally refer to like elements throughout the specification.

For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the illustrated components.

Features of various embodiments of the present disclosure may be partially or fully adhered to or combined with each other and may be interlocked and operated in various technical ways, and embodiments may be performed independently or in association with each other.

Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a plan view of a display device according to an exemplary embodiment of the present disclosure. For convenience of description, fig. 1 illustrates only a plurality of subpixels SP and a substrate 110 among the respective components of the display device 100.

The substrate 110 is a support member for supporting other components of the display device 100, and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be formed of a polymer or plastic, such as Polyimide (PI), or may be formed of a material having flexibility.

The substrate 110 includes a display area AA and a non-display area NA.

The display area AA is an area for displaying an image. In the display area AA, a plurality of sub-pixels SP for displaying an image and a driving circuit for driving the plurality of sub-pixels SP may be provided. The driving circuit may include various thin film transistors, storage capacitors, and lines for driving the subpixels SP. For example, the circuit may be formed of various components such as a driving transistor, a switching transistor, a sensing transistor, a storage capacitor, a gate line, a data line, and the like, but is not limited thereto.

The non-display area NA is an area where no image is displayed. In the non-display area NA, various lines, driving ICs, and the like for driving the sub-pixels SP disposed in the display area AA are disposed. For example, various driving ICs such as a gate driver IC and a data driver IC may be disposed in the non-display area NA.

Meanwhile, although fig. 1 illustrates that the non-display area NA surrounds the display area AA, the non-display area NA may be an area extending from one side of the display area AA, and is not limited thereto.

A plurality of subpixels SP are disposed in the display area AA of the substrate 110. Each of the plurality of sub-pixels SP is an independent unit that emits light, and each of the plurality of sub-pixels SP is provided with a light emitting element and a driving circuit. For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, but is not limited thereto.

Hereinafter, the driving circuit of the plurality of sub-pixels SP will be described in detail with reference to fig. 2.

Fig. 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Referring to fig. 2, the driving circuit for driving the light emitting elements 160 of the plurality of sub-pixels SP includes a first transistor 120, a second transistor 130, a third transistor 140, a storage capacitor 150, a gate line GL, a data line DL, a high potential power line VDD, a sensing line SL, and a reference line RL.

Referring to fig. 2, each of the first transistor 120, the second transistor 130, and the third transistor 140 included in the driving circuit of the sub-pixel SP includes a gate electrode, a source electrode, and a drain electrode. The first transistor 120, the second transistor 130, and the third transistor 140 may be P-type thin film transistors or N-type thin film transistors. For example, in a P-type thin film transistor, since holes flow from a source electrode to a drain electrode, a current can flow from the source electrode to the drain electrode. In the N-type thin film transistor, since electrons flow from the source electrode to the drain electrode, a current can flow from the drain electrode to the source electrode. Hereinafter, it is assumed that the first transistor 120, the second transistor 130, and the third transistor 140 are N-type thin film transistors in which current flows from the drain electrode to the source electrode, but the present disclosure is not limited thereto.

The first transistor 120 includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the first node N1, the first source electrode is connected to the first electrode of the light emitting element 160, and the first drain electrode is connected to the high potential power supply line VDD. When the voltage of the first node N1 is higher than the threshold voltage, the first transistor 120 is turned on, and when the voltage of the first node N1 is lower than the threshold voltage, the first transistor 120 is turned off. In addition, when the first transistor 120 is turned on, the first transistor 120 may transmit a power signal from the high potential power line VDD to the light emitting element 160. The first transistor 120 may also be referred to as a driving transistor.

The second transistor 130 includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the gate line GL, the second source electrode is connected to the first node N1, and the second drain electrode is connected to the data line DL. The second transistor 130 may be turned on or off based on a gate signal from the gate line GL. When the second transistor 130 is turned on, the data signal from the data line DL may be charged to the first node N1. The second transistor 130 may also be referred to as a switching transistor.

The third transistor 140 includes a third active layer, a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the sensing line SL, the third source electrode is connected to the second node N2, and the third drain electrode is connected to the reference line RL. The third transistor 140 may be turned on or off based on a sensing signal from the sensing line SL. When the third transistor 140 is turned on, the reference voltage from the reference line RL may be transferred to the storage capacitor 150. The third transistor 140 may also be referred to as a sense transistor. Meanwhile, in fig. 2, the gate line GL and the sensing line SL are shown as separate lines, but the gate line GL and the sensing line SL may be implemented as a single line.

The storage capacitor 150 includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is connected to the first node N1, and the second capacitor electrode is connected to the second node N2. When the light emitting element 160 emits light, the storage capacitor 150 holds a potential difference between the first gate electrode and the first source electrode of the first transistor 120, thereby allowing a constant current to be supplied to the light emitting element 160.

The first electrode of the light emitting element 160 is connected to the second node N2, and the second electrode is connected to the low potential power supply line VSS. The light emitting element 160 may receive a current from the first transistor 120 to emit light. At this time, the low potential power signal from the low potential power line may be a ground voltage.

Meanwhile, in fig. 2, the driving circuit of the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure is described as having a 3T1C structure including three transistors and one storage capacitor. However, the number and connection relationship of the transistors and the storage capacitors may be variously changed according to design, and are not limited thereto.

Hereinafter, the plurality of sub-pixels SP will be described in more detail with reference to fig. 3 and 4.

Fig. 3 is an enlarged plan view of the region a of fig. 1. Fig. 4 is a sectional view taken along line IV-IV' of fig. 3. Fig. 3 is a plan view showing four sub-pixels SP. Referring to fig. 3 and 4, the display device 100 according to an exemplary embodiment of the present disclosure includes a substrate 110, a gate line GL, a data line DL, a high potential power line VDD, a sensing line SL, a reference line RL, a light emitting element 160, a first transistor 120, a second transistor 130, a third transistor 140, a storage capacitor 150, a buffer layer 111, a gate insulating layer 112, a passivation layer 113, and a planarization layer 114. In fig. 3, a plurality of color filters are not shown for convenience of explanation. In fig. 4, only a first color filter 171 of the plurality of color filters is shown.

First, referring to fig. 3, the plurality of subpixels SP include a red subpixel SPR, a green subpixel SPG, a blue subpixel SPB, and a white subpixel SPW. Each of the plurality of sub-pixels SP includes an emission area and a circuit area CA.

The emission area EA is an area capable of independently emitting light of one color. The light emitting element 160 may be disposed in the emission area EA. The emission area EA of the red subpixel SPR is a red emission area emitting red light, the emission area EA of the green subpixel SPG is a green emission area emitting green light, the emission area EA of the blue subpixel SPB is a blue emission area emitting blue light, and the emission area EA of the white subpixel SPW may be a white emission area emitting white light.

The circuit area CA is an area where a driving circuit for driving the plurality of light emitting elements 160 is provided. In the circuit area CA, a first transistor 120, a second transistor 130, a third transistor 140, and a storage capacitor 150 may be disposed.

Referring to fig. 3 and 4, a plurality of high potential power lines VDD, a plurality of data lines DL, and reference lines extending in a column direction between a plurality of subpixels SP are disposed on a substrate 110. The plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL may be disposed on the same layer on the substrate 110 and may be formed of the same conductive material. For example, the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL may be formed of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

The plurality of high potential power supply lines VDD are lines for transmitting power signals to each of the plurality of sub-pixels SP, and include a first high potential power supply line VDD1 and a second high potential power supply line VDD 2. Two sub-pixels SP adjacent to each other in the row direction may share one high potential power supply line VDD among the plurality of high potential power supply lines VDD. For example, the first high potential power line VDD1 is disposed at the left side of the red subpixel SPR and transmits a power signal to the first transistors 120 of the red subpixel SPR and the white subpixel SPW. The second high potential power supply line VDD2 is disposed at the right side of the green subpixel SPG and transmits a power signal to the blue subpixel SPB and the first transistor 120 of the green subpixel SPG.

The plurality of data lines DL are lines for transmitting data signals to each of the plurality of sub-pixels SP, and include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL 4. The first data line DL1 is disposed between the red subpixel SPR and the white subpixel SPW, i.e., at the right side of the red subpixel SPR, and transmits a data signal to the second transistor 130 of the red subpixel SPR. The second data line DL2 is disposed between the first data line DL1 and the white subpixel SPW, i.e., at the left side of the white subpixel SPW, and transmits a data signal to the second transistor 130 of the white subpixel SPW. The third data line DL3 is disposed between the blue subpixel SPB and the green subpixel SPG, i.e., at the right side of the blue subpixel SPB, and transmits a data signal to the second transistor 130 of the blue subpixel SPB. The fourth data line DL4 is disposed between the third data line DL3 and the green subpixel SPG, i.e., at the left side of the green subpixel SPG, and transmits a data signal to the second transistor 130 of the green subpixel SPG.

The reference line RL is a line for transmitting a reference signal to each of the plurality of sub-pixels SP, and may be disposed between the white sub-pixel SPW and the blue sub-pixel SPB. A plurality of sub-pixels SP constituting one pixel may share one reference line RL. The reference line RL may transmit a reference signal to the third transistors 140 of the red, white, blue, and green sub-pixels SPR, SPW, SPB, and SPG.

The buffer layer 111 is disposed on the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL. The buffer layer 111 may reduce permeation of moisture or impurities through the substrate 110. The buffer layer 111 may be made of, for example, silicon oxide (SiO)_x) Or silicon nitride (SiN)_x) But is not limited thereto. The buffer layer 111 may be omitted according to the type of the substrate 110 or the type of the thin film transistor, but is not limited thereto.

The first transistor 120 is disposed in the circuit area CA of each of the sub-pixels SP. The first transistor 120 includes a first gate electrode 121, a first source electrode 122, a first drain electrode 123, and a first active layer 124. The first transistor 120 electrically connected to the first electrode 161 of the light emitting element 160 and the high potential power line VDD may be a driving transistor.

First, the first drain electrode 123 is disposed on the buffer layer 111. The first drain electrode 123 is electrically connected to a plurality of high potential power supply lines VDD. Specifically, the first drain electrodes 123 of the red and white sub-pixels SPR and SPW may be electrically connected to the first high potential power supply line VDD1 through contact holes formed in the buffer layer 111. The first drain electrodes 123 of the blue and green sub-pixels SPB and SPG may be electrically connected to the second high potential power supply line VDD2 through contact holes formed in the buffer layer 111.

The first active layer 124 is disposed on the buffer layer 111. The first active layer 124 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto. For example, when the first active layer 124 is formed of an oxide semiconductor, the first active layer 124 may be formed of a channel region, a source region, and a drain region, and the source region and the drain region may be conductor regions. However, the present disclosure is not limited thereto.

Meanwhile, the first drain electrodes 123 of the red and white sub-pixels SPR and SPW may be integrally formed, and the first drain electrodes 123 of the blue and green sub-pixels SPB and SPG may be integrally formed. Specifically, the first drain electrode 123 of the red subpixel SPR and the first drain electrode 123 of the white subpixel SPW may be integrally formed to share one first high potential power supply line VDD 1. For example, the power signal from the first high potential power line VDD1 may be transmitted to the first drain electrode 123 of the white subpixel SPW through the first drain electrode 123 of the red subpixel SPR. The power signal from the second high potential power supply line VDD2 may be transmitted to the first drain electrode 123 of the blue subpixel SPB through the first drain electrode 123 of the green subpixel SPG. However, the present disclosure is not limited thereto. The first drain electrode 123 of the red subpixel SPR and the first drain electrode 123 of the white subpixel SPW may be separately formed, and the first drain electrode 123 of the blue subpixel SPB and the first drain electrode 123 of the green subpixel SPG may be separately formed.

The first active layer 124 and the first drain electrode 123 of each of the plurality of sub-pixels SP may be integrally formed. For example, when a voltage is applied to the first gate electrode 121 in the red subpixel SPR, the first drain electrode 123, which is integrally formed with the first active layer 124 and is a conductor region, transmits a power signal from the first high potential power supply line VDD1 to the first active layer 124 and the first source electrode 122. The first drain electrode 123 may be defined as being integrated with the first high potential power supply line VDD1, but is not limited thereto.

The gate insulating layer 112 is disposed on the first active layer 124 and the first drain electrode 123. The gate insulating layer 112 is a layer for insulating the first gate electrode 121 and the first active layer 124 from each other, and may be formed of an insulating material. For example, the gate insulating layer 112 may be made of silicon oxide (SiO)_x) Or silicon nitride (SiN)_x) But is not limited thereto.

In each of the plurality of sub-pixels SP, the first gate electrode 121 is disposed on the gate insulating layer 112 to overlap the first active layer 124. The first gate electrode 121 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

In each of the plurality of sub-pixels SP, the first source electrode 122 is disposed on the gate insulating layer 112 to be spaced apart from the first gate electrode 121. The first source electrode 122 may be electrically connected to the first active layer 124 through a contact hole formed in the gate insulating layer 112. The first source electrode 122 and the first gate electrode 121 may be disposed on the same layer and may be formed of the same conductive material. However, the present disclosure is not limited thereto. The first source electrode 122 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The second transistor 130 is disposed in the circuit area CA of each of the plurality of sub-pixels SP. The second transistor 130 includes a second gate electrode 131, a second source electrode 132, a second drain electrode 133, and a second active layer 134. The second transistor 130 electrically connected to the gate line GL, the data line DL, and the first gate electrode 121 of the first transistor 120 may be a switching transistor.

First, in each of the plurality of sub-pixels SP, the second drain electrode 133 is disposed between the substrate 110 and the buffer layer 111. The second drain electrode 133 is electrically connected to one data line DL among the plurality of data lines DL. The second drain electrode 133 may be integrally formed with the plurality of data lines DL, and may be formed of the same conductive material as the plurality of data lines DL. For example, the second drain electrode 133 of the red subpixel SPR may be integrally formed with the first data line DL1, the second drain electrode 133 of the white subpixel SPW may be integrally formed with the second data line DL2, the second drain electrode 133 of the blue subpixel SPB may be integrally formed with the third data line DL3, and the second drain electrode 133 of the green subpixel SPG may be integrally formed with the fourth data line DL 4. The second drain electrode 133 may be formed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

In each of the plurality of sub-pixels SP, the second source electrode 132 is disposed to be spaced apart from the second drain electrode 133 between the substrate 110 and the buffer layer 111. The second source electrode 132 and the second drain electrode 133 may be disposed on the same layer and may be formed of the same conductive material. However, the present disclosure is not limited thereto. The second source electrode 132 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

In each of the plurality of sub-pixels SP, the second active layer 134 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer 134 may be electrically connected to the second source electrode 132 and the second drain electrode 133 through contact holes formed in the buffer layer 111. The second active layer 134 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

In each of the plurality of sub-pixels SP, the second gate electrode 131 is disposed on the gate insulating layer 112 to overlap the second active layer 134. The second gate electrode 131 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The second gate electrode 131 extends from the gate line GL. Accordingly, the second gate electrode 131 and the gate line GL may be formed of the same conductive material. The gate line GL may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The gate line GL is a line that transmits a gate signal to each of the plurality of sub-pixels SP. The gate line GL crosses the plurality of sub-pixels SP and extends in a row direction. For example, the gate line GL is disposed to extend in a row direction between the circuit area CA and the emission area EA of each of the plurality of sub-pixels SP, and to cross the plurality of high potential power supply lines VDD, the plurality of data lines DL, and the reference line RL extending in a column direction.

The third transistor 140 is disposed in the circuit area CA of each of the sub-pixels SP. The third transistor 140 includes a third gate electrode 141, a third source electrode 142, a third drain electrode 143, and a third active layer 144. The third transistor 140 electrically connected to the reference line RL, the sensing line SL, and the second capacitor electrode 152 of the storage capacitor 150 may be a sensing transistor.

First, in each of the plurality of sub-pixels SP, the third source electrode 142 is disposed between the substrate 110 and the buffer layer 111. The third source electrode 142 is disposed on the same layer as the plurality of high potential power supply lines VDD, the plurality of data lines DL, and the reference line RL, and is formed of the same conductive material as the plurality of high potential power supply lines VDD, the plurality of data lines DL, and the reference line RL. The third source electrode 142 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The third source electrode 142 may be electrically connected to the first source electrode 122. Specifically, the third source electrode 142 extends toward the first source electrode 122 to contact a portion of the first active layer 124 overlapping the first source electrode 122, thereby being electrically connected to the first source electrode 122. In addition, the third source electrode 142 may also be electrically connected to a second capacitor electrode 152 constituting a storage capacitor 150, which will be described later.

Meanwhile, the third source electrode 142 may function as a light blocking layer blocking light incident to the first active layer 124 of the first transistor 120. For example, when light is irradiated on the first active layer 124, a leakage current may occur, and thus, the reliability of the first transistor 120 may be reduced. In this case, the third source electrode 142 formed of a non-transparent conductive material is disposed under the first active layer 124 and the first gate electrode 121, thereby blocking light incident on the first active layer 124 from the bottom of the substrate. Accordingly, the reliability of the first transistor 120 can be improved.

In each of the plurality of sub-pixels SP, the third active layer 144 is disposed between the buffer layer 111 and the gate insulating layer 112. The third active layer 144 may be electrically connected to the third source electrode 142 through a contact hole formed in the buffer layer 111, and may be electrically connected to the third drain electrode 143 through a contact hole formed in the gate insulating layer 112. The third active layer 144 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

In each of the plurality of sub-pixels SP, the third gate electrode 141 is disposed on the gate insulating layer 112 to overlap the third active layer 144. The third gate electrode 141 is electrically connected to the sensing line SL. The third gate electrode 141 may be integrally formed with the sensing line SL and may be formed of the same conductive material as the sensing line SL. The third gate electrode 141 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The sensing line SL is a line that transmits a sensing signal to each of the plurality of sub-pixels SP, and extends in a row direction between the plurality of sub-pixels SP. For example, the sensing line SL may be disposed to extend in a row direction at a boundary between the plurality of sub-pixels SP, and cross the plurality of high potential power lines VDD, the plurality of data lines DL, and the reference line RL extending in a column direction.

In each of the plurality of sub-pixels SP, the third drain electrode 143 is disposed on the gate insulating layer 112. The third drain electrode 143 may be electrically connected to the third active layer 144 through a contact hole formed in the gate insulating layer 112. The third drain electrode 143 may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The third drain electrode 143 is electrically connected to the reference line RL through the auxiliary reference line SRL. A plurality of sub-pixels SP constituting one pixel may share one reference line RL. In this case, in order to transmit the reference signal from the reference line RL to each of the plurality of sub-pixels SP, an auxiliary reference line SRL electrically connected to the reference line RL and extending in the row direction may be provided. The auxiliary reference line SRL may be electrically connected to a reference line RL extending in the column direction between the white subpixel SPW and the blue subpixel SPB through contact holes formed in the buffer layer 111 and the gate insulating layer 112. In addition, the auxiliary reference line SRL may extend in a row direction from the reference line RL and be electrically connected to the third drain electrode 143 of each of the plurality of sub-pixels SP. The auxiliary reference line SRL is integrally formed with the third drain electrode 143 and may be formed of the same conductive material. The auxiliary reference line SRL may be formed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

The storage capacitor 150 is disposed in the circuit area CA of each sub-pixel SP. The storage capacitor 150 may store a voltage between the first gate electrode 121 and the first source electrode 122 of the first transistor 120 so that the light emitting element 160 continuously maintains the same state during one frame period. The storage capacitor 150 includes a first capacitor electrode 151 and a second capacitor electrode 152.

In each of the plurality of sub-pixels SP, the first capacitor electrode 151 is disposed between the substrate 110 and the buffer layer 111. Among the conductive members disposed on the substrate 110, the first capacitor electrode 151 may be disposed closest to the substrate 110. The first capacitor electrode 151 may be integrally formed with the second source electrode 132 and electrically connected to the second source electrode 132. In addition, the first capacitor electrode 151 may be electrically connected to the first gate electrode 121 through a contact hole formed in the buffer layer 111. That is, the second source electrode 132 of the second transistor 130 and the first gate electrode 121 of the first transistor 120 may be electrically connected to each other through the first capacitor electrode 151. The first capacitor electrode 151 integrally formed with the second source electrode 132 may be formed of the same material as the second source electrode 132. The first capacitor electrode 151 may be formed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

In this case, the first capacitor electrode 151 is disposed under the first gate electrode 121 and the first source electrode 122. The first capacitor electrode 151 is disposed to overlap the first source electrode 122.

In each of the plurality of sub-pixels SP, the second capacitor electrode 152 is disposed on the gate insulating layer 112. The second capacitor electrode 152 may be disposed on the first capacitor electrode 151 to overlap the first capacitor electrode 151. The second capacitor electrode 152 may be integrally formed with the first source electrode 122 and electrically connected to the first source electrode 122. A portion of the first source electrode 122 overlapping the first capacitor electrode 151 may be defined as a second capacitor electrode 152. The second capacitor electrode 152 integrally formed with the first source electrode 122 may be formed of the same material as the first source electrode 122. The second capacitor electrode 152 may be formed of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

In summary, the first capacitor electrode 151 of the storage capacitor 150 may be integrally formed with the second source electrode 132, and may be electrically connected to the first gate electrode 121 of the first transistor 120 and the second source electrode 132 of the second transistor 130. In addition, the second capacitor electrode 152 may be integrally formed with the first source electrode 122, and may be electrically connected to the first source electrode 122 of the first transistor 120 and the third source electrode 142 of the third transistor 140.

Next, a passivation layer 113 is disposed on the first transistor 120, the second transistor 130, the third transistor 140, the storage capacitor 150, the plurality of high potential power lines VDD, the plurality of data lines DL, the reference line RL, the gate line GL, and the sensing line SL. The passivation layer 113 is an insulating layer for protecting components under the passivation layer 113. For example, the passivation layer 113 may be made of silicon oxide (SiO)_x) Or silicon nitride (SiN)_x) But is not limited thereto. Further, according to an embodiment, the passivation layer 113 may be omitted.

A plurality of color filters are disposed on the passivation layer 113. Specifically, a plurality of color filters may be disposed between the planarization layer 114 and the passivation layer 113. The plurality of color filters include a first color filter 171, a second color filter, and a third color filter. For example, the first color filter 571 may be a red color filter, the second color filter may be a blue color filter, and the third color filter may be a green color filter.

The first color filter 171 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of one of the plurality of sub-pixels SP. For example, the first color filter 171 is a red color filter, and the first color filter 171 may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the red subpixel SPR.

Although not shown in fig. 3 and 4, a second color filter may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP. For example, the second color filter is a blue color filter, and the second color filter may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the blue sub-pixel SPB.

In addition, although not shown in fig. 3 and 4, a third color filter may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP. For example, the third color filter is a green color filter, and the third color filter may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the green sub-pixel SPG.

A planarization layer 114 is disposed on the passivation layer 113 and the plurality of color filters. The planarization layer 114 is an insulating layer for planarizing an upper portion of the substrate 110 on which the first transistor 120, the second transistor 130, the third transistor 140, the storage capacitor 150, the plurality of high potential power supply lines VDD, the plurality of data lines DL, the reference line RL, the gate line GL, and the sensing line SL are disposed. The planarization layer 114 may be formed of an organic material, and may be formed of a single layer or a plurality of layers of, for example, polyimide or photo acryl. However, the present disclosure is not limited thereto.

The light emitting element 160 is disposed in each of the plurality of sub-pixels SP. In each of the plurality of sub-pixels SP, the light emitting element 160 is disposed on the planarization layer 114. The light emitting element 160 includes a first electrode 161, a light emitting layer 164, and a second electrode 165.

The first electrode 161 is disposed on the planarization layer 114 in the emission area EA. Since the first electrode 161 supplies holes to the light emitting layer 164, the first electrode 161 may be formed of a conductive material having a high work function, and may be referred to as an anode. The first electrode 161 may be formed of, for example, a transparent conductive material, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), but is not limited thereto.

Meanwhile, when the display device 100 according to an exemplary embodiment of the present disclosure is a top emission type, a reflective layer formed of a metal material having excellent reflection efficiency, for example, aluminum (Al) or silver (Ag), may be added to a lower portion of the first electrode 161, so that light emitted from the light emitting layer 164 is reflected on the first electrode 161 to be guided in an upward direction, i.e., to the second surface 165. In contrast, when the display apparatus 100 is a bottom emission type, the first electrode 161 may be formed of only a transparent conductive material. Hereinafter, description will be made on the assumption that the display apparatus 100 according to an exemplary embodiment of the present disclosure is a bottom emission type.

The light emitting layer 164 is disposed on the first electrode 161 in the emission area EA and the circuit area CA. The light emitting layer 164 may be formed as a single layer throughout the plurality of sub-pixels SP. That is, the respective light emitting layers 164 of the plurality of sub-pixels SP may be connected to each other and integrally formed. The light emitting layer 164 may be configured as a single light emitting layer 164, or may have a structure in which a plurality of light emitting layers 164 emitting different colors of light are stacked. The light emitting layer 164 may further include organic layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

The second electrode 165 is disposed on the light emitting layer 164 in the emission area EA and the circuit area CA. Since the second electrode 165 supplies electrons to the light emitting layer 164, the second electrode 165 may be formed of a conductive material having a low work function, and may be referred to as a cathode. The second electrode 165 may be formed as a single layer throughout the plurality of sub-pixels SP. That is, the respective second electrodes 165 of the plurality of sub-pixels SP may be connected to each other and integrally formed. The second electrode 165 may be formed of a transparent conductive material such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or the like, or an alloy of ytterbium (Yb), and may further include a layer of a doped metal. However, the present disclosure is not limited thereto. Meanwhile, although not shown in fig. 3 and 4, the second electrode 165 of the light emitting element 160 may be electrically connected to the low potential power line VSS, thereby being supplied with a low potential power signal.

The light emitting element 160 includes an extension portion 162 extending from the first electrode 161 toward the circuit area CA. The extension portion 162 extends from the first electrode 161 of the emission area EA toward the first source electrode 122 of the circuit area CA, and may be electrically connected to the first source electrode 122 through contact holes formed in the planarization layer 114 and the passivation layer 113. Accordingly, the first electrode 161 of the light emitting element 160 may be electrically connected to the first source electrode 122 of the first transistor 120 and the second capacitor electrode 152 of the storage capacitor 150 through the extension portion 162.

The light emitting element 160 further includes a repair portion 163, the repair portion 163 extending from the first electrode 161 provided in one sub-pixel SP of the plurality of sub-pixels SP toward the circuit area CA of another sub-pixel SP adjacent to the one sub-pixel SP. The repair portion 163 extends toward the circuit area CA of another sub-pixel SP emitting the same color light as the one sub-pixel SP among the sub-pixels SP adjacent to the one sub-pixel SP. For example, the repair section 163 of one red subpixel SPR may extend in the vertical direction toward the circuit area CA of another red subpixel SPR adjacent to the one red subpixel SPR. The repair portion 163 may extend toward the third source electrode 142 of the third transistor 140 in the circuit area CA of the adjacent sub-pixel SP. The repair portion 163 may overlap the third source electrode 142 with the planarization layer 114 and the passivation layer 113 interposed therebetween.

If defects occur in the plurality of transistors and the storage capacitor 150 in the circuit area CA, laser light may be irradiated to the repair portion 163 extending toward the third source electrode 142 of the adjacent sub-pixel SP, so that the repair portion 163 and the third source electrode 142 of the adjacent sub-pixel SP may be electrically connected to each other. In this case, the third source electrode 142 may be electrically connected between the first source electrode 122 of the first transistor 120 and the first electrode 161 of the light emitting element 160, that is, at a point where a current supplied from the first transistor 120 to the light emitting element 160 flows. Therefore, even if a defect occurs in the driving circuit, the first transistor 120 and the repair portion 163 may be electrically connected to each other through the third source electrode 142 of the adjacent sub-pixel SP, and the two light emitting elements 160 may be driven by one driving circuit. Meanwhile, in the drawing, the repair portion 163 is shown to overlap with the third source electrode 142. However, the repair portion 163 may overlap with the first transistor 120, but is not limited thereto.

The repair pattern RP is disposed between the repair portion 163 and the third source electrode 142. The repair pattern RP is formed on the same layer as the first drain electrode 123, the first gate electrode 121, and the gate line GL, and is formed of the same material as the first drain electrode 123, the first gate electrode 121, and the gate line GL. The island-shaped repair pattern RP is disposed to overlap the third source electrode 142 and the repair portion 163. If a defect occurs in the driving circuit, laser light may be irradiated to the repair portion 163, so that the repair portion 163, the repair pattern RP, and the third source electrode 142 may be electrically connected to each other. In this case, a plurality of insulating layers such as the buffer layer 111, the gate insulating layer 112, the passivation layer 113, and the planarization layer 114 are disposed between the third source electrode 142 and the repair portion 163. Also, the repair pattern RP may also be disposed between the third source electrode 142 and the repair portion 163 to easily connect the third source electrode 142 and the repair portion 163 to each other. However, the repair portion 163 and the repair pattern RP may be omitted according to design, and are not limited thereto.

Meanwhile, a dummy pattern DP formed of the same material as the gate line GL is disposed on some of the plurality of contact holes, the high-potential power supply line VDD, and the reference line RL. The island-shaped dummy pattern DP may be disposed to overlap the high-potential power supply line VDD, the reference line RL, or the contact hole. The dummy pattern DP is a pattern formed in a mask design, and the arrangement of the dummy pattern DP may be changed according to the mask design, but is not limited thereto.

In the display device 100 according to the exemplary embodiment of the present disclosure, by providing the extension portion 162, power consumption of the light emitting element 160 may be reduced and color coordinate distortion may be minimized. First, the light emitting layer 164 and the second electrode 165 are disposed in the entire emission area and the circuit area CA. The light-emitting layer 164 is disposed in the entire emission area EA and circuit area CA. However, light may not be emitted from the entire light emitting layer 164, but may be emitted only from a portion of the light emitting layer 164 overlapping with the second electrode 165 and the first electrode 161. In this case, when the first electrode 161 is disposed in the entire circuit area CA, light is also emitted from the circuit area CA, and therefore, power consumption and the light amount of the light emitting element 160 may increase. However, since the display apparatus 100 according to the exemplary embodiment of the present disclosure is of a bottom emission type, even when light is emitted from the circuit area CA, the light is blocked by the plurality of transistors and the storage capacitor 150 disposed in the circuit area CA. Therefore, the light extraction efficiency is reduced. In addition, when an image is implemented using light emitted from the emission area EA, undesired light is emitted from the circuit area CA, that is, light leakage may occur, thereby causing color coordinate distortion. Therefore, only the extension portion 162 electrically connected to the first electrode 161 is minimally disposed in the circuit area CA, whereby light emission in the circuit area CA may be minimized, and power consumption and color coordinate distortion of the light emitting element 160 may be reduced.

According to an exemplary embodiment of the present disclosure, a repair portion 163 is further provided in the display device 100, whereby when one driving circuit is defective, the two light emitting elements 160 can be driven by the other driving circuit. The repair portion 163 extends from the first electrode 161 provided in one sub-pixel SP among the plurality of sub-pixels SP toward the circuit area CA of another sub-pixel SP that emits the same color light as the one sub-pixel SP among the sub-pixels SP adjacent to the one sub-pixel SP. The repair portion 163 may extend toward the third source electrode 142 of the third transistor 140 in the circuit area CA of the adjacent sub-pixel SP and overlap the third source electrode 142. If defects occur in the plurality of transistors and the storage capacitor 150 in the circuit area CA, laser light is irradiated to the repair portion 163 extending toward the third source electrode 142 of the adjacent sub-pixel SP, so that the repair portion 163 and the third source electrode 142 of the adjacent sub-pixel SP may be electrically connected to each other. In this case, since the third source electrode 142 is electrically connected to a point where a current supplied from the first transistor 120 to the light emitting element 160 flows, even if a defect occurs in the driving circuit, the repair portion 163 and the third source electrode 142 of the adjacent sub-pixel SP are electrically connected to each other, thereby driving the two light emitting elements 160 with one driving circuit. Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, even if a defect occurs in the driving circuit, the respective light emitting elements 160 of the plurality of sub-pixels SP may be driven, thereby minimizing a reduction in light efficiency.

Meanwhile, the storage capacitor 150 holds a potential difference between the first gate electrode 121 and the first source electrode 122 of the first transistor 120, thereby allowing a constant current to be supplied to the light emitting element 160. In addition, in order to supply a constant current to the light emitting element 160, it is important to maintain a voltage in the first capacitor electrode 151 connected to the first gate electrode 121 of the storage capacitor 150. However, when the first capacitor electrode 151 is disposed adjacent to the second electrode 165 of the light emitting element 160 connected to the low potential power line VSS, a parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 increases, so that a data signal from the data line DL may be distorted.

In the related art, after forming a bank at a boundary between the entire circuit area and the emission area, a second electrode is formed on the bank so that the second electrode and the first capacitor electrode may be disposed to be spaced apart from each other by a distance sufficient to reduce parasitic capacitance. Meanwhile, the display device 100 according to the exemplary embodiment of the present disclosure is the display device 100 that allows a simplified process by removing the bank. Accordingly, in the display device 100, since the bank is removed, a distance between the first capacitor electrode 151 and the second electrode 165 may be shortened, thereby causing a parasitic capacitance problem.

Accordingly, in the display device 100 according to the exemplary embodiment of the present disclosure, the first capacitor electrode 151 is disposed closest to the substrate 110 among the conductive members disposed on the substrate 110, whereby parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 may be minimized. Specifically, the distance between the first capacitor electrode 151 and the second electrode 165 may be increased by disposing the first capacitor electrode 151 closest to the substrate 110. First, on the substrate 110, the first capacitor electrode 151 is provided along with the high potential power line VDD, the plurality of data lines DL, and the reference line RL. In addition, the buffer layer 111 and the gate insulating layer 112 are disposed on the first capacitor electrode 151, and the first source electrode 122 serving as the second capacitor electrode 152 is disposed on the gate insulating layer 112. In addition, after the passivation layer 113 and the planarization layer 114 are disposed on the first source electrode 122, the second electrode 165 may be disposed on the planarization layer 114. That is, since the plurality of insulating layers and the second capacitor electrode 152 are disposed between the first capacitor electrode 151 and the second electrode 165, the distance between the first capacitor electrode 151 and the second electrode 165 may be increased. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, by disposing the first capacitor electrode 151 closest to the substrate 110, parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 may be minimized, and a current flowing to the light emitting element 160 may be stably maintained.

Fig. 5 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Fig. 6 is a sectional view taken along line VI-VI' of fig. 5. The display device 500 of fig. 5 and 6 is different from the display device 100 of fig. 1 to 4 only in that a plurality of color filters 570 are further included, and other configurations thereof are substantially the same as those of the display device 100 of fig. 1 to 4. Therefore, duplicate description will be omitted.

Referring to fig. 5 and 6, a plurality of color filters 570 are disposed under the planarization layer 114 and the light emitting elements 160. Specifically, a plurality of color filters 570 may be disposed between the planarization layer 114 and the passivation layer 113. The plurality of color filters 570 include a first color filter 571, a second color filter 572, and a third color filter 573. For example, the first color filter 571 may be a red color filter, the second color filter 572 may be a blue color filter, and the third color filter 573 may be a green color filter.

The first color filter 571 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of one of the plurality of sub-pixels SP, and between the planarization layer 114 and the first transistor 120 in the circuit area CA of the one sub-pixel SP. For example, the first color filter 571 is a red color filter, and the first color filter 571 may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the red subpixel SPR, and may be disposed between the first transistor 120 and the planarization layer 114 in the circuit area CA of the red subpixel SPR. In addition to the red subpixel SPR, a first color filter 571 may be disposed between the planarization layer 114 and the substrate 110 in the circuit area CA of each of the white subpixel SPW, the blue subpixel SPB, and the green subpixel SPG. Accordingly, the first color filters 571 disposed in the emission regions of the red subpixels SPR of the plurality of subpixels SP and the circuit regions CA of each of the plurality of subpixels SP may be formed to have a mesh shape.

The second color filter 572 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP, between the planarization layer 114 and the first transistor 120 in the circuit area CA of another sub-pixel SP, and between the planarization layer 114 and the first color filter 571 in the circuit area CA of the one sub-pixel SP. The second color filter 572 is, for example, a blue color filter. The second color filter 572 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the blue subpixel SPB, between the first transistor 120 and the planarization layer 114 in the circuit area CA of the blue subpixel SPB, and between the planarization layer 114 and the first color filter 571 in the circuit area CA of the red subpixel SPR. In addition, a second color filter 572 may be disposed between the planarization layer 114 and the substrate 110 in the circuit area CA of each of the white and green sub-pixels SPW and SPG, in addition to the circuit areas CA of the blue and red sub-pixels SPB and SPR. Accordingly, the second color filter 572 disposed in the emission area of the blue sub-pixel SPB of the plurality of sub-pixels SP and the circuit area CA of each of the plurality of sub-pixels SP may be formed to have a mesh shape.

Further, the first color filter 571 and the second color filter 572 disposed in the circuit area CA of each of the plurality of sub-pixels SP may partially overlap each other. In the respective circuit areas CA of the plurality of sub-pixels SP, a first color filter 571 may be disposed between the substrate 110 and the planarization layer 114, and a second color filter 572 may be disposed between the first color filter 571 and the planarization layer 114. Accordingly, the first color filter 571 and the second color filter 572 may be disposed to overlap each other in the respective circuit areas CA of the plurality of sub-pixels SP.

Meanwhile, it is shown that the first color filter 571 and the second color filter 572 are disposed to overlap each other in the respective circuit areas CA of the plurality of sub-pixels SP, but this is merely an arrangement according to a process order. The type of the plurality of color filters 570 stacked on the circuit area CA is not limited thereto. For example, in the case where the third color filter 573 and the first color filter 571 are sequentially formed on the passivation layer 113, the third color filter 573 and the first color filter 571 may also be disposed and stacked in the entire respective circuit areas CA of the plurality of sub-pixels SP.

The third color filter 573 is disposed in the emission area EA of another sub-pixel SP among the plurality of sub-pixels SP. For example, the third color filter 573 is a green color filter, and the third color filter 573 is disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the green sub-pixel SPG. In this case, instead of the third color filter 573, the first and second color filters 571 and 572 may be disposed in the circuit area CA of the green sub-pixel SPG. Accordingly, since the third color filter 573 is disposed only in the emission area EA of the green subpixel SPG, the third color filter 573 may be formed to have an island shape.

In the display device 500 according to another embodiment of the present disclosure, at least a portion of the plurality of color filters 570 may be stacked in the circuit area CA, thereby minimizing parasitic capacitance between the first capacitor electrode 151 and the second electrode 165. First, since the display apparatus 500 according to another exemplary embodiment of the present disclosure is a bottom emission type, light emitted from the light emitting element 160 is emitted to the bottom of the substrate 110. Accordingly, a plurality of color filters 570 may be disposed between the light emitting elements 160 and the substrate 110 to convert colors of light emitted from the light emitting elements 160 into various colors. In this case, each of the plurality of color filters 570 is not only disposed in the emission area EA but also disposed in the circuit area CA, so that the separation distance between the first capacitor electrode 151 and the second electrode 165 can be increased. For example, a first color filter 571 of the plurality of color filters 570 may be disposed between the substrate 110 and the planarization layer 114, that is, between the light emitting element 160 and the storage capacitor 150, in the emission region of the red subpixel SPR and the entire circuit region CA of the plurality of subpixels SP. Further, a second color filter 572 among the plurality of color filters 570 may be disposed between the planarization layer 114 and the substrate 110 in the emission area EA of the blue subpixel SPB, and may be disposed between the storage capacitor 150 and the light emitting element 160 in the entire circuit area CA of the plurality of subpixels SP. Accordingly, the first and second color filters 571 and 572 are also disposed between the second electrode 165 and the storage capacitor 150 in the circuit area CA, so that the distance between the first and second capacitor electrodes 151 and 165 may be increased and the parasitic capacitance between the first and second capacitor electrodes 151 and 165 may also be minimized. Accordingly, in the display device 500 according to another exemplary embodiment of the present disclosure, at least one color filter 570 is further disposed between the second electrode 165 and the storage capacitor 150 in the circuit area CA, so that distortion of the data signal due to parasitic capacitance between the first capacitor electrode 151 and the second electrode 165 may be minimized.

Exemplary embodiments of the present disclosure may also be described as follows:

according to an aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels are defined, each of the plurality of sub-pixels including an emission region and a circuit region; a driving transistor disposed in the circuit region and including a first gate electrode and a first source electrode disposed on the same layer; a storage capacitor disposed in the circuit region and including a first capacitor electrode electrically connected to and disposed below the first gate electrode; an insulating layer which planarizes upper portions of the driving transistor and the storage capacitor; and a light emitting element provided on the insulating layer.

The first capacitor electrode may overlap the first source electrode, and the storage capacitor may further include a second capacitor electrode integrally formed with the first source electrode.

The second capacitor electrode may be disposed on the first capacitor electrode.

The light emitting element may include: a first electrode disposed in the emission region and on the insulating layer; a light emitting layer disposed in the entire emission region and circuit region and on the first electrode; and a second electrode provided in the entire emission region and circuit region and on the light-emitting layer, wherein, in an upper surface of the insulating layer, a remaining portion except a portion contacting the first electrode may be in contact with the light-emitting element.

The first electrodes disposed in the plurality of respective sub-pixels may be disposed to be spaced apart from each other, and the light emitting layer may be disposed between the first electrodes spaced apart from each other.

The light emitting element may further include an extension portion extending from the first electrode of the emission region toward the first source electrode of the circuit region.

The light emitting element may further include a repair portion extending from the first electrode disposed in one of the plurality of sub-pixels toward a circuit region of another sub-pixel adjacent to the one sub-pixel.

The display device may further include: a light blocking layer disposed between the substrate and the first active layer of the driving transistor, and the first capacitor electrode may be disposed on the same layer as the light blocking layer.

The display device may further include: a switching transistor disposed in the circuit region and including a second source electrode electrically connected to the first gate electrode and the first capacitor electrode; a sensing transistor disposed in the circuit region and including a third source electrode electrically connected to the driving transistor, the storage capacitor, and the light emitting element; a gate line electrically connected to the second gate electrode of the switching transistor; a data line electrically connected to the second drain electrode of the switching transistor; a high potential power supply line electrically connected to the first drain electrode of the driving transistor; a sensing line electrically connected to the third gate electrode of the sensing transistor; and a reference line electrically connected to the third drain electrode of the sensing transistor, wherein the data line, the high-potential power line, and the sensing line may be disposed to extend along the column line on the same layer as the light blocking layer, and wherein the gate line and the reference line may be disposed to extend along the row direction on the same layer as the first gate electrode.

The display device may further include: a first color filter provided between the insulating layer in the emission region of one of the plurality of sub-pixels and the substrate, and between the insulating layer in the circuit region of the one sub-pixel and the driving transistor; and a second color filter disposed between the insulating layer in the emission region of another sub-pixel among the plurality of sub-pixels and the substrate, and between the insulating layer in the circuit region of the one sub-pixel and the first color filter.

The first capacitor electrode, the first color filter, and the second color filter may overlap each other in a circuit region of one sub-pixel.

According to another aspect of the present disclosure, a display device includes: a substrate in which a plurality of sub-pixels including a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel are defined; a first capacitor electrode disposed in each of the plurality of sub-pixels; a driving transistor disposed in each of the plurality of sub-pixels and including a first gate electrode electrically connected to the first capacitor electrode and a first source electrode disposed on the first capacitor electrode; and a light emitting element including a plurality of anodes disposed on the driving transistor in each of the plurality of sub-pixels, and a cathode and a light emitting layer disposed on the entire plurality of sub-pixels to cover the plurality of anodes, wherein a portion of a lower surface of the light emitting layer may be disposed on the same plane as a corresponding lower surface of the plurality of anodes.

Each of the plurality of sub-pixels may further include: an emission region in which a plurality of anodes are disposed; and a circuit region in which the driving transistor and the first capacitor electrode are disposed, wherein the light emitting element may further include an extension portion extending from each of the plurality of anodes toward the driving transistor.

The light emitting element may further include a repair portion extending from an anode disposed in the red sub-pixel among the plurality of anodes toward another red sub-pixel adjacent to the red sub-pixel.

The display device may further include: a red color filter disposed in an emission region of the red sub-pixel in the emission region and in a circuit region of each of the plurality of sub-pixels; a blue color filter disposed in an emission region of the blue sub-pixel in the emission region and in a circuit region of each of the plurality of sub-pixels; and a green color filter disposed in an emission region of the green sub-pixel in the emission region, wherein the red color filter and the blue color filter may overlap each other in a circuit region of each of the plurality of sub-pixels.

The red and blue color filters may be formed to have a mesh shape, wherein the green color filter may be formed to have an island shape.

The first capacitor electrode and the first source electrode may constitute a storage capacitor, and the first source electrode, the red color filter, and the blue color filter may be disposed between the first capacitor electrode and the cathode.

The first capacitor electrode may be disposed closest to the substrate among the conductive members disposed on the substrate.

Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and may be embodied in many different forms without departing from the technical concept of the present disclosure. Accordingly, the exemplary embodiments of the present disclosure are provided only for illustrative purposes, and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. It should therefore be understood that the above-described exemplary embodiments are illustrative in all respects and are not limiting of the disclosure. The scope of the present disclosure should be construed based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as falling within the scope of the present disclosure.