阅读说明：本技术 三相无刷电机驱动电路、三相无刷电机驱动器及补偿方法 (Three-phase brushless motor driving circuit, three-phase brushless motor driver and compensation method ) 是由 李伟东 庞佑兵 马朝骥 吕果 刘登学 于 2020-12-03 设计创作，主要内容包括：本发明提供了一种三相无刷电机驱动电路、三相无刷电机驱动器及补偿方法,三相无刷电机驱动电路包括光耦隔离电路,死区补偿电路,逻辑处理电路,死区设置电路和驱动及三相桥电路相互连接来实现,可以有效消除输出功率管共态直通的问题,能降低输入PWM脉冲宽度损失,避免当输入PWM脉冲宽度较小,导致电机不能正常转动的问题发生；该方法通过获取三相无刷电机驱动器的死区时间,并确定补偿时间,进而调整死区补偿电路中第一电容的电容值,对光耦输出信号进行预展宽,可以实现根据死区时间大小来调整补偿的死区时间大小,更准确的解决由于PWM输入脉宽较小时电机不能转动问题。(The invention provides a three-phase brushless motor driving circuit, a three-phase brushless motor driver and a compensation method, wherein the three-phase brushless motor driving circuit comprises an optical coupling isolation circuit, a dead zone compensation circuit, a logic processing circuit, a dead zone setting circuit, a driving and three-phase bridge circuit which are mutually connected for realization, the common-mode through problem of an output power tube can be effectively eliminated, the loss of input PWM pulse width can be reduced, and the problem that the motor cannot normally rotate when the input PWM pulse width is smaller is avoided; according to the method, the dead time of the three-phase brushless motor driver is obtained, the compensation time is determined, the capacitance value of the first capacitor in the dead time compensation circuit is adjusted, the optical coupling output signal is pre-broadened, the compensation dead time can be adjusted according to the dead time, and the problem that the motor cannot rotate when the PWM input pulse width is small is solved more accurately.)

1. A three-phase brushless motor drive circuit, comprising:

the optical coupler isolation circuit is used for isolating the input PWM signal and outputting an optical coupler output signal;

the dead zone compensation circuit is used for pre-widening the optical coupler output signal according to the dead zone time of the three-phase brushless motor driving circuit to generate a PWM control signal;

the logic processing circuit is used for acquiring an external control signal and the PWM control signal and generating a three-phase power bridge control signal so as to control the on or off of the three-phase power bridge;

the dead zone setting circuit is used for setting a dead zone of a three-phase power bridge control signal;

the driving and three-phase bridge circuit is used for driving the three-phase brushless motor driving circuit and providing the three-phase power bridge;

the logic processing circuit is respectively connected with the dead zone compensation circuit, the dead zone setting circuit and the driving and three-phase bridge circuit, the dead zone setting circuit is connected with the driving and three-phase bridge circuit, and the optical coupling isolation circuit is connected with the dead zone compensation circuit.

2. The three-phase brushless motor driving circuit of claim 1, wherein the dead-zone setting circuit includes a first dead-zone setting sub-circuit, a second dead-zone setting sub-circuit, and a third dead-zone setting sub-circuit, and,

a fourth input end connected to the third output end of the logic processing circuit and the first end of the first dead zone setting sub-circuit;

a fifth input terminal connected to a fourth output terminal of the logic processing circuit and a first terminal of the second dead zone setting sub-circuit;

a sixth input terminal connected to the fifth output terminal of the logic processing circuit and the first terminal of the third dead zone setting sub-circuit;

a ninth output terminal connected to the second terminal of the first dead zone setting sub-circuit and the seventh input terminal of the driving and three-phase bridge circuit;

a tenth output terminal connected to the second terminal of the second dead zone setting sub-circuit and the eighth input terminal of the driving and three-phase bridge circuit;

and an eleventh output terminal connected to the second terminal of the third dead zone setting sub-circuit and the ninth input terminal of the driving and three-phase bridge circuit.

3. The three-phase brushless motor drive circuit of claim 2, further comprising at least one of:

the first dead zone setting sub-circuit comprises a first diode, a fourth resistor and a second capacitor, the cathode of the first diode and the first end of the fourth resistor are connected to the fourth input end, the anode of the first diode, the second end of the fourth resistor and the first end of the second capacitor are connected to the ninth output end, and the second end of the second capacitor is grounded;

the second dead zone setting sub-circuit comprises a nineteenth diode, a sixth resistor and a fifth capacitor, wherein the cathode of the nineteenth diode and the first end of the sixth resistor are connected to the fifth input end, the anode of the nineteenth diode, the second end of the sixth resistor and the first end of the fifth capacitor are connected to the tenth output end, and the second end of the fifth capacitor is grounded;

the third dead zone setting sub-circuit comprises a twentieth diode, an eleventh resistor and a ninth capacitor, wherein the cathode of the twentieth diode and the first end of the eleventh resistor are connected to the sixth input end, the anode of the twentieth diode, the second end of the eleventh resistor and the first end of the ninth capacitor are connected to the eleventh output end, and the second end of the ninth capacitor is grounded.

4. The three-phase brushless motor driving circuit according to any one of claims 1 to 3, wherein the dead-zone compensation circuit includes a second input terminal, a second output terminal, a third resistor, a first capacitor, and a second Schmitt trigger, wherein:

a first end of the third resistor is connected to the second input end, a first end of the first capacitor and a first end of the second schmitt trigger;

a fourteenth end of the second schmitt trigger is connected to a second power supply, and a second end of the second schmitt trigger is connected to the second output end;

the second input end is connected to the first output end of the optical coupling isolation circuit, and the second output end is connected to the third input end of the logic processing circuit;

the second end of the third resistor, the second end of the first capacitor and the seventh end of the second Schmitt trigger are grounded.

5. The three-phase brushless motor drive circuit of claim 4, wherein the drive and three-phase bridge circuit comprises:

a fourth driving circuit, a first end of which is connected to a first end of a thirteenth resistor, a second end of which is grounded, a third end of which is connected to a fourth power supply, a fifth end of which is connected to a twelfth output end and a first end of a tenth capacitor, a sixth end of which is connected to a cathode of a twenty-first diode and a second end of the tenth capacitor, a seventh end of which is connected to a first end of a twelfth resistor, a ninth end of which is connected to a seventh power supply, a tenth end of which is connected to a ninth input end, a twelfth end of which is connected to a twelfth input end of the driving and three-phase bridge circuit, and a tenth end of which is connected to ground;

a grid electrode of the first power tube is connected to the second end of the twelfth resistor, a drain electrode of the first power tube is connected to a first power supply, and a source electrode of the first power tube is connected to the twelfth output end;

a gate of the second power tube is connected to a second end of the thirteenth resistor, a drain of the second power tube is connected to the twelfth output end and the source of the first power tube, and the source of the second power tube is grounded;

the anode of the twenty-first diode and the first end of the eleventh capacitor are connected to the fourth power supply;

a first end of the twelfth capacitor is connected to the seventh power supply;

a second end of the twelfth capacitor and a second end of the eleventh capacitor are grounded;

a fifth driving circuit, a first end of the fifth driving circuit is connected to a first end of a fourteenth resistor, a second end of the fifth driving circuit is grounded, a third end of the fifth driving circuit is connected to a fifth power supply, a fifth end of the fifth driving circuit is connected to a thirteenth output end and a first end of a thirteenth capacitor, a sixth end of the fifth driving circuit is connected to a cathode of a twenty-second diode and a second end of the thirteenth capacitor, a seventh end of the fifth driving circuit is connected to a first end of a fifteenth resistor, a ninth end of the fifth driving circuit is connected to an eighth power supply, a tenth end of the fifth driving circuit is connected to an eighth input end, a twelfth end of the fifth driving circuit is connected to an eleventh input end of the driving and three-phase bridge circuit, and a tenth end of the fifth driving circuit is grounded;

a gate of the third power tube is connected to a second end of the fifteenth resistor, a drain of the third power tube is connected to a second power supply, and a source of the third power tube is connected to a thirteenth output end;

a gate of the fourth power transistor is connected to a second end of the fourteenth resistor, a drain of the fourth power transistor is connected to the thirteenth output terminal and a source of the third power transistor, and a source of the fourth power transistor is grounded;

the anode of the twenty-second diode and the first end of the fourteenth capacitor are connected to the fifth power supply;

a first end of the fifteenth capacitor is connected to the eighth power supply;

a second end of the fifteenth capacitor and a second end of the fourteenth capacitor are grounded;

a sixth driving circuit, a first end of which is connected to a first end of a sixteenth resistor, a second end of which is grounded, a third end of which is connected to a sixth power supply, a fifth end of which is connected to a fourteenth output end and a first end of a sixteenth capacitor, a sixth end of which is connected to a cathode of a twenty-third diode and a second end of the sixteenth capacitor, a seventh end of which is connected to a first end of a seventeenth resistor, a ninth end of which is connected to a ninth power supply, a tenth end of which is connected to a seventh input end, a twelfth end of which is connected to a tenth input end of the driving and three-phase bridge circuit, and a tenth end of which is grounded;

a grid electrode of the fifth power tube is connected to a second end of the seventeenth resistor, a drain electrode of the fifth power tube is connected to a third power supply, and a source electrode of the fifth power tube is connected to a fourteenth output end;

a gate of the sixth power transistor is connected to the second end of the sixteenth resistor, a drain of the sixth power transistor is connected to the fourteenth output terminal and the source of the fifth power transistor, and the source of the sixth power transistor is grounded;

the anode of the twenty-third diode and the first end of the seventeenth capacitor are connected to the sixth power supply;

a first end of the eighteenth capacitor is connected to the ninth power supply;

a second end of the eighteenth capacitor and a second end of the seventeenth capacitor are grounded;

the tenth input end is connected to the sixth output end of the logic processing circuit;

the eleventh input end is connected to a seventh output end of the logic processing circuit;

the twelfth input end is connected to the eighth output end of the logic processing circuit.

6. The three-phase brushless motor drive circuit of claim 5, wherein the external control signals include a Hall signal, a FR signal, an EN signal, an IL signal, and a BR signal, and wherein the logic processing circuit comprises:

a logic signal processing integrated circuit, a first terminal of which is connected to the third input terminal, a second terminal of which inputs the FR control signal, a third terminal of which inputs the EN control signal, a fourth terminal of which inputs the BR control signal, a fifth terminal of which inputs the SA control signal, a sixth terminal of which inputs the SB control signal, a seventh terminal of which inputs the SC control signal, an eighth terminal of which inputs the IL control signal, a ninth terminal of which is connected to ground, and a tenth terminal of which is connected to a sixth output terminal, the eleventh end of the logic signal processing integrated circuit is connected to the seventh output end, the twelfth end of the logic signal processing integrated circuit is connected to the eighth output end, the thirteenth end of the logic signal processing integrated circuit is connected to the fifth output end, the fourteenth end of the logic signal processing integrated circuit is connected to the fourth output end, the fifteenth end of the logic signal processing integrated circuit is connected to the third output end, and the sixteenth end of the logic signal processing integrated circuit is connected to the third power supply.

7. The three-phase brushless motor drive circuit of claim 4, wherein the optocoupler isolation circuit comprises:

a first end of the first optical coupler is connected to a first end of a first resistor, a second end of the first optical coupler is connected to an input signal ground, a third end of the first optical coupler is grounded, and a fourth end of the first optical coupler is connected to a first output end and a first end of a second resistor;

the second end of the first resistor is connected to the first input end, and the second end of the second resistor is connected to the first power supply.

8. A three-phase brushless motor driver comprising a three-phase brushless motor driving circuit according to any one of claims 1 to 7.

9. A three-phase brushless motor driver dead zone compensation method applied to the three-phase brushless motor driver of claim 8, comprising:

obtaining dead time of the three-phase brushless motor driver;

and adjusting the capacitance value of a first capacitor in the dead zone compensation circuit according to the dead zone time, and pre-widening the optical coupling output signal.

10. The dead-zone compensation method for a three-phase brushless motor driver according to claim 9, applied to a three-phase brushless motor driver including the three-phase brushless motor driving circuit according to claim 7, wherein the capacitance value of the first capacitor is determined as follows:

wherein, C₁Is the capacitance value of the first capacitor, R₂Is the resistance value of the second resistor, R₃Is the resistance value of the third resistor, V_CCIs 12V, V_THAt is the upper threshold voltage, Δ T is the dead time.

Technical Field

The invention relates to the technical field of electromechanical servo driving, in particular to a three-phase brushless motor driving circuit, a three-phase brushless motor driver and a compensation method.

Background

The three-phase brushless motor has the advantages of simple structure, high operation efficiency, good speed regulation performance, simple control and the like, and is widely applied to the field of automatic control.

In the related art, a bridge driving circuit is usually used to drive a three-phase brushless motor to realize the motion of the three-phase brushless motor, and in the driving process of the motor, the problem of common-state direct connection of an output power tube in the bridge driving circuit may occur, which leads to the burning of the motor, a power supply or other components, so that a three-phase brushless motor driving circuit which can effectively eliminate the common-state direct connection problem of the output power tube, reduce the loss of input PWM pulse width, and avoid the problem that the motor cannot normally rotate when the input PWM pulse width is smaller is urgently needed.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a three-phase brushless motor driving circuit, a three-phase brushless motor driver and a compensation method, which are used to solve the problem that common-mode shoot-through may occur in an output power transistor in a bridge driving circuit in the related art, and therefore, there is a need for a three-phase brushless motor driving circuit that can effectively eliminate the common-mode shoot-through problem of the output power transistor, reduce the loss of input PWM pulse width, and avoid the problem that the motor cannot normally rotate when the input PWM pulse width is smaller.

To achieve the above and other related objects, the present invention provides a three-phase brushless motor driving circuit, comprising:

the optical coupler isolation circuit is used for isolating the input PWM signal and outputting an optical coupler output signal;

the dead zone compensation circuit is used for pre-widening the optical coupler output signal according to the dead zone time of the three-phase brushless motor driving circuit to generate a PWM control signal;

the logic processing circuit is used for acquiring an external control signal and the PWM control signal, performing logic processing and generating a three-phase power bridge control signal so as to control the on or off of the three-phase power bridge;

the dead zone setting circuit is used for setting a dead zone of a three-phase power bridge control signal;

the driving and three-phase bridge circuit is used for driving the three-phase brushless motor driving circuit and providing the three-phase power bridge;

the logic processing circuit is respectively connected with the dead zone compensation circuit, the dead zone setting circuit and the driving and three-phase bridge circuit, the dead zone setting circuit is connected with the driving and three-phase bridge circuit, and the optical coupling isolation circuit is connected with the dead zone compensation circuit.

Optionally, the dead band setting circuit comprises a first dead band setting sub-circuit, a second dead band setting sub-circuit, and a third dead band setting sub-circuit, and,

a fourth input end connected to the third output end of the logic processing circuit and the first end of the first dead zone setting sub-circuit;

a fifth input terminal connected to a fourth output terminal of the logic processing circuit and a first terminal of the second dead zone setting sub-circuit;

a sixth input terminal connected to the fifth output terminal of the logic processing circuit and the first terminal of the third dead zone setting sub-circuit;

a ninth output terminal connected to the second terminal of the first dead zone setting sub-circuit and the seventh input terminal of the driving and three-phase bridge circuit;

a tenth output terminal connected to the second terminal of the second dead zone setting sub-circuit and the eighth input terminal of the driving and three-phase bridge circuit;

and an eleventh output terminal connected to the second terminal of the third dead zone setting sub-circuit and the ninth input terminal of the driving and three-phase bridge circuit.

Optionally, at least one of the following is also included:

the first dead zone setting sub-circuit comprises a first diode, a fourth resistor and a second capacitor, the cathode of the first diode and the first end of the fourth resistor are connected to the fourth input end, the anode of the first diode, the second end of the fourth resistor and the first end of the second capacitor are connected to the ninth output end, and the second end of the second capacitor is grounded;

the second dead zone setting sub-circuit comprises a nineteenth diode, a sixth resistor and a fifth capacitor, wherein the cathode of the nineteenth diode and the first end of the sixth resistor are connected to the fifth input end, the anode of the nineteenth diode, the second end of the sixth resistor and the first end of the fifth capacitor are connected to the tenth output end, and the second end of the fifth capacitor is grounded;

the third dead zone setting sub-circuit comprises a twentieth diode, an eleventh resistor and a ninth capacitor, wherein the cathode of the twentieth diode and the first end of the eleventh resistor are connected to the sixth input end, the anode of the twentieth diode, the second end of the eleventh resistor and the first end of the ninth capacitor are connected to the eleventh output end, and the second end of the ninth capacitor is grounded.

Optionally, the dead-time compensation circuit includes a second input terminal, a second output terminal, a third resistor, a first capacitor, and a second schmitt trigger, where:

a first end of the third resistor is connected to the second input end, a first end of the first capacitor and a first end of the second schmitt trigger;

a fourteenth end of the second schmitt trigger is connected to a second power supply, and a second end of the second schmitt trigger is connected to the second output end;

the second input end is connected to the first output end of the optical coupling isolation circuit, and the second output end is connected to the third input end of the logic processing circuit;

the second end of the third resistor, the second end of the first capacitor and the seventh end of the second Schmitt trigger are grounded.

Optionally, the driving and three-phase bridge circuit includes:

a fourth driving circuit, a first end of which is connected to a first end of a thirteenth resistor, a second end of which is grounded, a third end of which is connected to a fourth power supply, a fifth end of which is connected to a twelfth output end and a first end of a tenth capacitor, a sixth end of which is connected to a cathode of a twenty-first diode and a second end of the tenth capacitor, a seventh end of which is connected to a first end of a twelfth resistor, a ninth end of which is connected to a seventh power supply, a tenth end of which is connected to a ninth input end, a twelfth end of which is connected to a twelfth input end of the driving and three-phase bridge circuit, and a tenth end of which is connected to ground;

a grid electrode of the first power tube is connected to the second end of the twelfth resistor, a drain electrode of the first power tube is connected to a first power supply, and a source electrode of the first power tube is connected to the twelfth output end;

a gate of the second power tube is connected to a second end of the thirteenth resistor, a drain of the second power tube is connected to the twelfth output end and the source of the first power tube, and the source of the second power tube is grounded;

the anode of the twenty-first diode and the first end of the eleventh capacitor are connected to the fourth power supply;

a first end of the twelfth capacitor is connected to the seventh power supply;

a second end of the twelfth capacitor and a second end of the eleventh capacitor are grounded;

a fifth driving circuit, a first end of the fifth driving circuit is connected to a first end of a fourteenth resistor, a second end of the fifth driving circuit is grounded, a third end of the fifth driving circuit is connected to a fifth power supply, a fifth end of the fifth driving circuit is connected to a thirteenth output end and a first end of a thirteenth capacitor, a sixth end of the fifth driving circuit is connected to a cathode of a twenty-second diode and a second end of the thirteenth capacitor, a seventh end of the fifth driving circuit is connected to a first end of a fifteenth resistor, a ninth end of the fifth driving circuit is connected to an eighth power supply, a tenth end of the fifth driving circuit is connected to an eighth input end, a twelfth end of the fifth driving circuit is connected to an eleventh input end of the driving and three-phase bridge circuit, and a tenth end of the fifth driving circuit is grounded;

a gate of the third power tube is connected to a second end of the fifteenth resistor, a drain of the third power tube is connected to a second power supply, and a source of the third power tube is connected to a thirteenth output end;

a gate of the fourth power transistor is connected to a second end of the fourteenth resistor, a drain of the fourth power transistor is connected to the thirteenth output terminal and a source of the third power transistor, and a source of the fourth power transistor is grounded;

the anode of the twenty-second diode and the first end of the fourteenth capacitor are connected to the fifth power supply;

a first end of the fifteenth capacitor is connected to the eighth power supply;

a second end of the fifteenth capacitor and a second end of the fourteenth capacitor are grounded;

a sixth driving circuit, a first end of which is connected to a first end of a sixteenth resistor, a second end of which is grounded, a third end of which is connected to a sixth power supply, a fifth end of which is connected to a fourteenth output end and a first end of a sixteenth capacitor, a sixth end of which is connected to a cathode of a twenty-third diode and a second end of the sixteenth capacitor, a seventh end of which is connected to a first end of a seventeenth resistor, a ninth end of which is connected to a ninth power supply, a tenth end of which is connected to a seventh input end, a twelfth end of which is connected to a tenth input end of the driving and three-phase bridge circuit, and a tenth end of which is grounded;

a grid electrode of the fifth power tube is connected to a second end of the seventeenth resistor, a drain electrode of the fifth power tube is connected to a third power supply, and a source electrode of the fifth power tube is connected to a fourteenth output end;

a gate of the sixth power transistor is connected to the second end of the sixteenth resistor, a drain of the sixth power transistor is connected to the fourteenth output terminal and the source of the fifth power transistor, and the source of the sixth power transistor is grounded;

the anode of the twenty-third diode and the first end of the seventeenth capacitor are connected to the sixth power supply;

a first end of the eighteenth capacitor is connected to the ninth power supply;

a second end of the eighteenth capacitor and a second end of the seventeenth capacitor are grounded;

the tenth input end is connected to the sixth output end of the logic processing circuit;

the eleventh input end is connected to a seventh output end of the logic processing circuit;

the twelfth input end is connected to the eighth output end of the logic processing circuit.

Optionally, the external control signal includes a hall signal, an FR signal, an EN signal, an IL signal, and a BR signal, and the logic processing circuit includes:

a logic signal processing integrated circuit, a first terminal of which is connected to the third input terminal, a second terminal of which inputs the FR control signal, a third terminal of which inputs the EN control signal, a fourth terminal of which inputs the BR control signal, a fifth terminal of which inputs the SA control signal, a sixth terminal of which inputs the SB control signal, a seventh terminal of which inputs the SC control signal, an eighth terminal of which inputs the IL control signal, a ninth terminal of which is connected to ground, and a tenth terminal of which is connected to a sixth output terminal, the eleventh end of the logic signal processing integrated circuit is connected to the seventh output end, the twelfth end of the logic signal processing integrated circuit is connected to the eighth output end, the thirteenth end of the logic signal processing integrated circuit is connected to the fifth output end, the fourteenth end of the logic signal processing integrated circuit is connected to the fourth output end, the fifteenth end of the logic signal processing integrated circuit is connected to the third output end, and the sixteenth end of the logic signal processing integrated circuit is connected to the third power supply.

Optionally, the optical coupling isolation circuit includes:

a first end of the first optical coupler is connected to a first end of a first resistor, a second end of the first optical coupler is connected to an input signal ground, a third end of the first optical coupler is grounded, and a fourth end of the first optical coupler is connected to a first output end and a first end of a second resistor;

the second end of the first resistor is connected to the first input end, and the second end of the second resistor is connected to the first power supply.

The embodiment of the invention also provides a three-phase brushless motor driver, which comprises the three-phase brushless motor driving circuit according to any one of the embodiments.

The embodiment of the present invention further provides a dead zone compensation method for a three-phase brushless motor driver, which is applied to the three-phase brushless motor driver according to the embodiment, and includes:

obtaining dead time of the three-phase brushless motor driver;

and adjusting the capacitance value of a first capacitor in the dead zone compensation circuit according to the dead zone time, and pre-widening the optical coupling output signal.

Alternatively, the dead zone compensation method of a three-phase brushless motor driver is applied to a three-phase brushless motor driver including the three-phase brushless motor driving circuit as claimed in claim 7, and the capacitance value of the first capacitor is determined as follows:

wherein, C₁Is the capacitance value of the first capacitor, R₂Is the resistance value of the second resistor, R₃Is the resistance value of the third resistor, V_CCIs 12V, V_THAt is the upper threshold voltage, Δ T is the dead time.

As described above, the three-phase brushless motor driving circuit, the three-phase brushless motor driver and the compensation method provided by the invention have the following beneficial effects:

the three-phase brushless motor driving circuit comprises an optical coupling isolation circuit, a dead zone compensation circuit and a logic processing circuit, wherein the dead zone setting circuit is connected with a driving circuit and a three-phase bridge circuit in an interconnecting mode, the problem of common-state direct connection of an output power tube can be effectively solved, the dead zone compensation circuit is used for pre-widening an optical coupling output signal according to the dead zone time of the three-phase brushless motor driving circuit, the loss of input PWM pulse width can be reduced, and the problem that the motor cannot normally rotate due to the fact that the input PWM pulse width is small is avoided.

Optionally, dead time of the three-phase brushless motor driver is obtained, compensation time is determined, a capacitance value of a first capacitor in the dead time compensation circuit is adjusted, the optocoupler output signal is pre-broadened, the dead time of compensation can be adjusted according to the dead time, and the problem that the motor cannot rotate when the PWM input pulse width is small is solved more accurately.

Drawings

Fig. 1 is a circuit structure of a three-phase brushless motor driving circuit according to an embodiment of the present invention;

fig. 2 is a circuit structure of a driving and three-phase bridge circuit according to an embodiment of the present invention;

fig. 3 is a circuit structure of another three-phase brushless motor driving circuit according to an embodiment of the present invention;

fig. 4 is a schematic flowchart of a dead-zone compensation method for a three-phase brushless motor driver according to a second embodiment of the present invention.

Description of the reference symbols

1 optical coupler isolation circuit

2 dead zone compensation circuit

3 logic processing circuit

4 dead zone setting circuit

5-drive and three-phase bridge circuit

1_ IN first input terminal

1_ OUT first output terminal

2_ IN second input terminal

2_ OUT second output terminal

3_ IN1 third input terminal

3_ OUT1 third output terminal

3_ OUT2 fourth output terminal

3_ OUT3 fifth output terminal

3_ OUT4 sixth output terminal

3_ OUT5 seventh output terminal

3_ OUT6 eighth output terminal

4_ IN1 fourth input terminal

4_ IN2 fifth input terminal

4_ IN3 sixth input terminal

A ninth output terminal of 4_ OUT1

Tenth output terminal of 4_ OUT2

Eleventh output terminal of 4_ OUT3

5_ IN1 seventh input terminal

5_ IN2 eighth input terminal

Ninth input terminal of 5_ IN3

Tenth input terminal of 5_ IN4

Eleventh input terminal of 5_ IN5

Twelfth input terminal of 5_ IN6

5_ OUT1 fourteenth output terminal

Thirteenth output terminal 5_ OUT2

Twelfth output terminal of 5_ OUT3

C1 first capacitor

C2 second capacitor

C5 fifth capacitor

Ninth capacitor of C9

Tenth capacitance of C10

Eleventh C11 capacitor

Twelfth capacitor of C12

C13 thirteenth capacitor

C14 fourteenth capacitance

C15 fifteenth capacitor

Sixteenth capacitor of C16

Seventeenth capacitor of C17

Eighteenth capacitor of C18

D1 first diode

Nineteenth diode of D19

Twenty-first diode of D21

D22 twenty-second diode

Twenty-third diode of D23

IN input terminal

M1 first power tube

M2 second power tube

M3 third power tube

M4 fourth power tube

M5 fifth power tube

M6 sixth power tube

OUTU U-phase output terminal

OUTV V phase output terminal

OUTW W-phase output terminal

R1 first resistor

R2 second resistor

R3 third resistor

R4 fourth resistor

R6 sixth resistor

Eleventh resistor R11

Twelfth resistor R12

Thirteenth resistor R13

Fourteenth resistor of R14

Fifteenth resistor of R15

Sixteenth resistor of R16

Seventeenth resistor of R17

U1 first optical coupler

U2A second Schmitt trigger

U3 logic signal processing integrated circuit

U4 fourth drive circuit

U5 fifth driving circuit

U6 sixth drive circuit

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in this embodiment are only for schematically illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, the actual implementation of the present invention can be carried out by changing the form, quantity and proportion of each component, and the layout of the components may be more complicated and complicated by the structure, proportion, size, etc. shown in the drawings attached to the present specification, which are only used for matching the disclosure in the present specification, it will be understood and appreciated by those skilled in the art that variations and modifications in the structure, modification and other arrangements may be made without departing from the spirit and scope of the invention as defined in the appended claims, the present invention should not be limited to the specific embodiments described herein, but should be construed to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Example one

An embodiment of the present invention provides a three-phase brushless motor driving circuit, referring to fig. 1, including:

the optical coupler isolation circuit 1 is used for isolating the input PWM signal and outputting an optical coupler output signal;

the dead zone compensation circuit 2 is used for pre-widening the optical coupling output signal according to the dead zone time of the three-phase brushless motor driving circuit to generate a PWM control signal;

the logic processing circuit 3 is used for acquiring an external control signal and a PWM control signal and generating a three-phase power bridge control signal so as to control the on or off of the three-phase power bridge;

the dead zone setting circuit 4 is used for setting a dead zone of a three-phase power bridge control signal;

the driving and three-phase bridge circuit 5 is used for driving a three-phase brushless motor driving circuit and providing a three-phase power bridge;

the logic processing circuit is respectively connected with the dead zone compensation circuit, the dead zone setting circuit, the driving and three-phase bridge circuit, the dead zone setting circuit is connected with the driving and three-phase bridge circuit, and the optical coupling isolation circuit is connected with the dead zone compensation circuit.

With continued reference to fig. 1, the optical coupler-isolator circuit 1 includes a first input terminal 1_ IN and a first output terminal 1_ OUT, the first input terminal 1_ IN is connected to the input terminal IN, and the first output terminal 1_ OUT is connected to a second input terminal 2_ IN of the dead-time compensation circuit 2. The third input terminal 3_ IN1 of the logic processing circuit 3 is connected to the second output terminal 2_ OUT of the dead zone compensation circuit 2, the third output terminal 3_ OUT1 of the logic processing circuit 3 is connected to the fourth input terminal 4_ IN1 of the dead zone setting circuit 4, the fourth output terminal 3_ OUT2 of the logic processing circuit 3 is connected to the fifth input terminal 4_ IN2 of the dead zone setting circuit 4, the fifth output terminal 3_ OUT3 of the logic processing circuit 3 is connected to the sixth input terminal 4_ IN3 of the dead zone setting circuit 4, the sixth output terminal 3_ OUT4 of the logic processing circuit 3 is connected to the tenth input terminal 5_ IN4 of the drive-and-three-phase bridge circuit 5, the seventh output terminal 3_ OUT5 of the logic processing circuit 3 is connected to the eleventh input terminal 5_ IN5 of the drive-and-three-phase bridge circuit 5, and the eighth output terminal 3_ OUT6 of the logic processing circuit 3 is connected to the twelfth input terminal 5_ IN6 of the drive-and-three. The drive and three-phase bridge circuit 5 is a drive circuit and a three-phase power bridge, the twelfth output terminal 5_ OUT3 of the drive and three-phase bridge circuit 5 is connected to the W-phase output terminal OUTW, the thirteenth output terminal 5_ OUT2 of the drive and three-phase bridge circuit 5 is connected to the V-phase output terminal OUTV, the fourteenth output terminal 5_ OUT1 of the drive and three-phase bridge circuit 5 is connected to the U-phase output terminal OUTU, the seventh input terminal 5_ IN1 of the drive and three-phase bridge circuit 5 is connected to the ninth output terminal 4_ OUT1 of the dead zone setting circuit 4, the eighth input terminal 5_ IN2 of the drive and three-phase bridge circuit 5 is connected to the tenth output terminal 4_ OUT2 of the dead zone setting circuit 4, and the ninth input terminal 5_ IN3 of the drive and three-phase bridge circuit 5 is connected to the eleventh output terminal 4_ OUT3 of.

In some embodiments, referring to fig. 2, the deadband setting circuit 4 includes a first deadband setting sub-circuit 41, a second deadband setting sub-circuit 42, and a third deadband setting sub-circuit 43, and,

a fourth input terminal 4_ IN1 connected to the third output terminal 3_ OUT1 of the logic processing circuit 3 and the first terminal of the first dead zone setting sub-circuit 41;

a fifth input terminal 4_ IN2 connected to the fourth output terminal 3_ OUT2 of the logic processing circuit 3 and to a first terminal of the second dead zone setting sub-circuit 42;

a sixth input terminal 4_ IN3 connected to the fifth output terminal 3_ OUT3 of the logic processing circuit 43 and to a first terminal of the third dead zone setting sub-circuit 43;

a ninth output terminal 4_ OUT1 connected to the second terminal of the first dead band setting sub-circuit 41 and the seventh input terminal 5_ IN1 of the driving and three-phase bridge circuit 5;

a tenth output terminal 4_ OUT2 connected to the second terminal of the second dead time setting sub-circuit 42 and the eighth input terminal 5_ IN2 of the driving and three-phase bridge circuit 5;

an eleventh output terminal 4_ OUT3 is connected to the second terminal of the third dead band setting sub-circuit 43 and the ninth input terminal 5_ IN3 of the driving and three-phase bridge circuit 5.

In some embodiments, referring to fig. 3, the three-phase brushless motor drive circuit further comprises at least one of:

the first dead zone setting sub-circuit comprises a first diode D1, a fourth resistor R4 and a second capacitor C2, wherein the cathode of the first diode D1 and the first end of the fourth resistor R4 are connected to the fourth input end 4_ IN1, the anode of the first diode D1, the second end of the fourth resistor R4 and the first end of the second capacitor C2 are connected to the ninth output end 4_ OUT1, and the second end of the second capacitor C2 is grounded;

the second dead zone setting sub-circuit comprises a nineteenth diode D19, a sixth resistor R6 and a fifth capacitor C5, wherein the cathode of the nineteenth diode D19 and the first end of the sixth resistor R6 are connected to the fifth input terminal 4_ IN2, the anode of the nineteenth diode D19, the second end of the sixth resistor R6 and the first end of the fifth capacitor C5 are connected to the tenth output terminal 4_ OUT2, and the second end of the fifth capacitor C5 is grounded;

the third dead zone setting sub-circuit includes a twenty-second diode D22, an eleventh resistor R11, and a ninth capacitor C9, a cathode of the twenty-second diode D22 and a first end of the eleventh resistor R11 are connected to the sixth input terminal 4_ IN3, an anode of the twenty-second diode D22, a second end of the eleventh resistor R11, and a first end of the ninth capacitor C9 are connected to the eleventh output terminal 4_ OUT3, and a second end of the ninth capacitor C9 is grounded.

IN some embodiments, with continued reference to fig. 3, the dead-band compensation circuit includes a second input terminal 2_ IN, a second output terminal 2_ OUT, a third resistor R3, a first capacitor C1, and a second schmitt trigger U2A, wherein:

a first end of the third resistor R3 is connected to the second input terminal 2_ IN, the first end of the first capacitor C1, and the first end of the second schmitt trigger U2A;

a fourteenth terminal of the second schmitt trigger U2A is connected to the second power supply, and a second terminal of the second schmitt trigger U2A is connected to the second output terminal 2_ OUT;

the second input end 2_ IN is connected to the first output end 1_ OUT of the optical coupler isolation circuit 1, and the second output end 2_ OUT is connected to the third input end 3_ IN1 of the logic processing circuit 3;

the second terminal of the third resistor R3, the second terminal of the first capacitor C1, and the seventh terminal of the second schmitt trigger U2A are grounded.

Alternatively, the dead time determination method of the three-phase brushless motor driving circuit may be obtained by the existing related art means, and is not limited herein.

Optionally, the dead time can be used as the compensation time of the dead time compensation circuit, and further the capacitance value of the first capacitor is adjusted to realize pre-widening of the optical coupling output signal, so as to overcome the problem that the motor cannot normally rotate due to the fact that the input PWM pulse width is small.

Optionally, the determination manner of the first capacitance may adopt the following manner:

wherein, C₁Is the capacitance value of the first capacitor, R₂Is the resistance value of the second resistor, R₃Is the resistance value of the third resistor, V_CCIs 12V, V_THAt is the upper threshold voltage, Δ T is the dead time.

Optionally, the method of pre-broadening the optical coupler output signal may also be implemented by using the existing related technical means.

In some embodiments, the drive and three-phase bridge circuit 5 includes:

a fourth driving circuit U4, IN which a first terminal of the fourth driving circuit U4 is connected to a first terminal of a thirteenth resistor R3, a second terminal of the fourth driving circuit U4 is grounded, a third terminal of the fourth driving circuit U4 is connected to a fourth power supply, a fifth terminal of the fourth driving circuit U4 is connected to a twelfth output terminal 5_ OUT3 and a first terminal of a tenth capacitor C10, a sixth terminal of the fourth driving circuit U4 is connected to a negative electrode of a twenty-first diode D21 and a second terminal of the tenth capacitor C10, a seventh terminal of the fourth driving circuit U4 is connected to a first terminal of the twelfth resistor R12, a ninth terminal of the fourth driving circuit U4 is connected to a seventh power supply, a tenth terminal of the fourth driving circuit U4 is connected to a ninth input terminal 5_ IN3, a twelfth terminal of the fourth driving circuit U4 is connected to a twelfth input terminal 5_ IN6 of the driving and three-phase bridge circuit 5, and a tenth terminal of the fourth driving circuit U4 is grounded;

a gate of the first power tube M1, a drain of the first power tube M1 is connected to the second end of the twelfth resistor R12, a drain of the first power tube M1 is connected to the first power supply, and a source of the first power tube M1 is connected to the twelfth output end 5_ OUT 3;

a gate of the second power transistor M2, a drain of the second power transistor M2 is connected to the second end of the thirteenth resistor R13, a drain of the second power transistor M2 is connected to the twelfth output terminal 5_ OUT3 and the source of the first power transistor M1, and a source of the second power transistor M2 is grounded;

an anode D21 of the twenty-first diode and a first end of an eleventh capacitor C11 are connected to the fourth power supply;

a first end of the twelfth capacitor C12 is connected to the seventh power supply;

a second end of the twelfth capacitor C12 and a second end of the eleventh capacitor C11 are grounded;

a fifth driving circuit U5, a first terminal of the fifth driving circuit U5 is connected to a first terminal of a fourteenth resistor R14, a second terminal of the fifth driving circuit U5 is grounded, a third terminal of the fifth driving circuit U5 is connected to a fifth power supply, a fifth terminal of the fifth driving circuit U5 is connected to a thirteenth output terminal 5_ OUT2 and a first terminal of a thirteenth capacitor C13, a sixth terminal of the fifth driving circuit U5 is connected to a cathode of a twenty-second diode D22, a second end of the thirteenth capacitor C13, a seventh end of the fifth driving circuit U5 is connected to the first end of the fifteenth resistor R15, a ninth end of the fifth driving circuit U5 is connected to the eighth power supply, a tenth end of the fifth driving circuit U5 is connected to the eighth input terminal 5_ IN2, a twelfth end of the fifth driving circuit U5 is connected to the eleventh input terminal 5_ IN5 of the driving and three-phase bridge circuit 5, and a tenth end of the fifth driving circuit U5 is connected to the ground;

a gate of the third power transistor M3, a gate of the third power transistor M3 is connected to the second end of the fifteenth resistor R15, a drain of the third power transistor M3 is connected to the second power supply M2, and a source of the third power transistor M3 is connected to the thirteenth output terminal 5_ OUT 2;

a gate of the fourth power transistor M4, a drain of the fourth power transistor M4 is connected to the second end of the fourteenth resistor R14, a drain of the fourth power transistor M4 is connected to the thirteenth output terminal 5_ OUT2 and the source of the third power transistor M3, and a source of the fourth power transistor M4 is grounded;

the anode of the twenty-second diode D22 and the first end of the fourteenth capacitor C14 are connected to the fifth power supply;

a first end of the fifteenth capacitor C15 is connected to the eighth power supply;

a second end of the fifteenth capacitor C15 and a second end of the fourteenth capacitor C14 are grounded;

a sixth driving circuit U6, wherein a first end of the sixth driving circuit U6 is connected to a first end of a sixteenth resistor R16, a second end of the sixth driving circuit U6 is grounded, a third end of the sixth driving circuit U6 is connected to a sixth power supply, a fifth end of the sixth driving circuit U6 is connected to first ends of a fourteenth output end 5_ OUT1 and a sixteenth capacitor C16, a sixth end of the sixth driving circuit U6 is connected to a negative electrode of a twenty-third diode D23 and a second end of the sixteenth capacitor C16, a seventh end of the sixth driving circuit U6 is connected to a first end of a seventeenth resistor R17, a ninth end of the sixth driving circuit U6 is connected to the ninth power supply, a tenth end of the sixth driving circuit U6 is connected to a seventh input end 5_ IN1, a twelfth end of the sixth driving circuit U6 is connected to a tenth input end 5_ IN4 of the driving and three-phase bridge circuit 5, and a tenth end of the sixth driving circuit U6 is grounded;

a gate of the fifth power transistor M5, a drain of the fifth power transistor M5 is connected to the second end of the seventeenth resistor R17, a drain of the fifth power transistor M5 is connected to the third power supply, and a source of the fifth power transistor M5 is connected to the fourteenth output terminal 5_ OUT 1;

a sixth power transistor M6, a gate of the sixth power transistor M6 is connected to the second end of the sixteenth resistor R16, a drain of the sixth power transistor M6 is connected to the fourteenth output terminal 5_ OUT1 and the source of the fifth power transistor M5, and a source of the sixth power transistor M6 is grounded;

an anode D23 of the twenty-third diode and a first end of a seventeenth capacitor C17 are connected to the sixth power supply;

a first end of the eighteenth capacitor C18 is connected to the ninth power supply;

the second end of the eighteenth capacitor C18 and the second end of the seventeenth capacitor C17 are grounded;

the tenth input terminal 5_ IN4 is connected to the sixth output terminal 3_ OUT4 of the logic processing circuit;

the eleventh input terminal 5_ IN5 is connected to the seventh output terminal 3_ OUT5 of the logic processing circuit;

the twelfth input terminal 5_ IN6 is connected to the eighth output terminal 3_ OUT6 of the logic processing circuit.

In some embodiments, with continued reference to fig. 3, the external control signals include a hall signal, a FR signal, an EN signal, an IL signal, and a BR signal, and the logic processing circuit 3 includes:

a logic signal processing integrated circuit U3, a first terminal of a logic signal processing integrated circuit U3 is connected to the third input terminal 3_ IN1, a second terminal of the logic signal processing integrated circuit U3 is connected to the FR control signal, a third terminal of the logic signal processing integrated circuit U3 is connected to the EN control signal, a fourth terminal of the logic signal processing integrated circuit U3 is connected to the BR control signal, a fifth terminal of a logic signal processing integrated circuit U3 is connected to the SA control signal, a sixth terminal of the logic signal processing integrated circuit U3 is connected to the SB control signal, a seventh terminal of the logic signal processing integrated circuit U3 is connected to the SC control signal, an eighth terminal of the logic signal processing integrated circuit U3 is connected to the IL control signal, a ninth terminal of the logic signal processing integrated circuit U3 is connected to ground, a tenth terminal of the logic signal processing integrated circuit U3 is connected to the sixth output terminal 3_ OUT4, an eleventh terminal of the logic signal processing integrated circuit U3 is connected to the seventh output terminal 3_ OUT5, the twelfth terminal of the logic signal processing integrated circuit U3 is connected to the eighth output terminal 3_ OUT6, the thirteenth terminal of the logic signal processing integrated circuit U3 is connected to the fifth output terminal 3_ OUT3, the fourteenth terminal of the logic signal processing integrated circuit U3 is connected to the fourth output terminal 3_ OUT2, the fifteenth terminal of the logic signal processing integrated circuit U3 is connected to the third output terminal 3_ OUT1, and the sixteenth terminal of the logic signal processing integrated circuit U3 is connected to the third power supply.

In some embodiments, with continued reference to fig. 3, the opto-isolator circuit 1 comprises:

a first end of the first optical coupler U1, a first end of the first optical coupler U1 is connected to a first end of the first resistor R1, a second end of the first optical coupler U1 is connected to an input signal ground, a third end of the first optical coupler U1 is grounded, and a fourth end of the first optical coupler U1 is connected to a first output end 1_ OUT and a first end of the second resistor R2;

the second terminal of the first resistor R1 is connected to the first input terminal 1_ IN, and the second terminal of the second resistor R2 is connected to the first power supply.

In some embodiments, first diode stage D1, nineteenth diode D19, and twentieth diode stage D20 are conventional diodes having a reverse withstand voltage of greater than 50V.

In some embodiments, the twenty-first diode D21, the twenty-second diode D22, and the twenty-third diode D23 are conventional diodes, and have a reverse withstand voltage of 500V.

In some embodiments, the first resistor R1 is a conventional common resistor with a resistance of 200-1K Ω.

In some embodiments, the second resistor R2 is a conventional common resistor having a resistance of 10K Ω.

In some embodiments, the third resistor R3 is a conventional common resistor with a resistance value of 3-30K Ω.

In some embodiments, the fourth resistor R4, the sixth resistor R6, and the eleventh resistor R11 are conventional resistors with a resistance of 1K Ω.

In some embodiments, the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14, the fifteenth resistor R15, the sixteenth resistor R16 and the seventeenth resistor R17 are conventional resistors with a resistance value of 10-100 Ω.

In some embodiments, the first capacitor C1 is a conventional common capacitor having a capacitance value of 50pF to 2000 pF.

In some embodiments, the second capacitor C2, the fifth capacitor C5, and the ninth capacitor C9 are conventional capacitors having a capacitance of 50pF to 3300 pF.

In some embodiments, the tenth capacitor C10, the thirteenth capacitor C13, and the sixteenth capacitor C16 are conventional capacitors with a capacitance of 1uF to 2.2 uF.

In some embodiments, the eleventh capacitor C11, the twelfth capacitor C12, the fourteenth capacitor C14, the fifteenth capacitor C15, the seventeenth capacitor C17 and the eighteenth capacitor C18 are conventional capacitors and have a capacitance of 1 uF.

In some embodiments, the first power transistor M1, the second power transistor M2, the third power transistor M3, the fourth power transistor M4, the fifth power transistor M5 and the sixth power transistor M6 are conventional power MOS transistors, the current is greater than 2A, and the withstand voltage is greater than 200V.

In some embodiments, the first optical coupler U1 is a general purpose high speed optical coupler with a delay time less than 1 uS.

In some embodiments, the second Schmitt trigger U2A is a general Schmitt trigger with an operating voltage of 2-15V.

In some embodiments, the logic signal processing integrated circuit U3 is a general purpose logic processing circuit including, but not limited to, SZ004, SZ054, etc.

In some embodiments, the fourth driving circuit U4, the fifth driving circuit U5, and the sixth driving circuit U6 are general MOS transistor driving circuits, including but not limited to IR2010, IR2110, etc.

In some embodiments, the first power source, the second power source, the third power source, the fourth power source, the fifth power source, the sixth power source, the seventh power source, the eighth power source, and the ninth power source may be the same power source or different power sources. Optionally, the first power supply, the second power supply, the third power supply, the fourth power supply, the fifth power supply, the sixth power supply, the seventh power supply, the eighth power supply, and the ninth power supply may all be 12V power supplies.

In some embodiments, the first power source, the second power source, and the third power source may be the same power source or different power sources, which is not limited herein.

In some embodiments, the operating temperature of the three-phase brushless motor driving circuit provided by the embodiments of the present invention includes-55 ℃ to 125 ℃, the power voltage includes 5 to 200V, and the output current capability includes 5 to 100A. Alternatively, this can be achieved by selecting the corresponding power MOS.

With continued reference to fig. 3, a three-phase brushless motor driving circuit provided by an embodiment of the present invention includes:

the optical coupling isolation circuit 1 is used for isolating an input PWM signal from a driving and three-phase bridge circuit and outputting an optical coupling output signal, a first input end 1_ IN of the optical coupling isolation circuit 1 is connected with an input end IN, and a first output end 1_ OUT of the optical coupling isolation circuit 1 is connected with a second input end 2_ IN of the dead zone compensation circuit 2;

the dead zone compensation circuit 2 is used for pre-widening the optical coupling output signal to generate a PWM control signal, a second input end 2_ IN of the dead zone compensation circuit is connected with a first output end 1_ OUT of the optical coupling isolation circuit 1, and a second output end 2_ OUT of the dead zone compensation circuit is connected with a third input end 3_ IN1 of the logic processing circuit 3;

the logic processing circuit 3 carries out logic processing on the input PWM control signal, Hall signal, FR, EN, IL and BR signal to generate 6 paths of three-phase power bridge control signals to control the correct conduction or the close of the three-phase power bridge, a third input terminal 3_ IN1 thereof is connected to the second output terminal 2_ OUT of the dead band compensation circuit 2, its third output terminal 3_ OUT1 is connected to a fourth input terminal 4_ IN1 of the dead band setting circuit 4, its fourth output terminal 3_ OUT2 is connected to the fifth input terminal 4_ IN2 of the dead band setting circuit 4, its fifth output terminal 3_ OUT3 is connected to the sixth input terminal 4_ IN3 of the dead band setting circuit 4, its sixth output terminal 3_ OUT4 is connected to the tenth input terminal 5_ IN4 of the drive and three-phase bridge circuit 5, its seventh output terminal 3_ OUT5 is connected to the eleventh input terminal 5_ IN5 of the drive and three-phase bridge circuit 5, an eighth output terminal 3_ OUT6 thereof is connected to the twelfth input terminal 5_ IN6 of the drive and three-phase bridge circuit 5;

a dead zone setting circuit 4 for setting a dead zone of the three-phase power bridge control signal, the fourth input terminal 4_ IN1 being connected to the third output terminal 3_ OUT1 of the logic processing circuit 3, the fifth input terminal 4_ IN2 being connected to the fourth output terminal 3_ OUT2 of the logic processing circuit 3, the sixth input terminal 4_ IN3 being connected to the fifth output terminal 3_ OUT3 of the logic processing circuit 3, the ninth output terminal 4_ OUT1 being connected to the seventh input terminal 5_ IN1 of the drive and three-phase bridge circuit 5, the fifth output terminal 4_ OUT2 being connected to the eighth input terminal 5_ IN2 of the drive and three-phase bridge circuit 5, the eleventh output terminal 4_ OUT3 being connected to the ninth input terminal 5_ IN3 of the drive and three-phase bridge circuit 5;

a drive and three-phase bridge circuit 5, which is a drive circuit and a three-phase power bridge, a seventh input terminal 5_ IN1 connected to the ninth output terminal 4_ OUT1 of the dead band setting circuit 4, an eighth input terminal 5_ IN2 connected to the tenth output terminal 4_ OUT2 of the dead band setting circuit 4, a ninth input terminal 5_ IN3 thereof is connected to an eleventh output terminal 4_ OUT3 of the dead band setting circuit 4, its tenth input terminal 5_ IN4 is connected to the sixth output terminal 3_ OUT4 of the logic processing circuit 3, the eleventh input terminal 5_ IN5 of which is connected to the twelfth output terminal 3_ OUT5 of the logic processing circuit 3, its twelfth input terminal 5_ IN6 is connected to the eighth output terminal 3_ OUT6 of the logic processing circuit 3, the fourteenth output terminal 5_ OUT1 thereof is connected to the U-phase output terminal OUTU, the thirteenth output terminal 5_ OUT2 thereof is connected to the V-phase output terminal OUTV, and the twelfth output terminal 5_ OUT3 thereof is connected to the W-phase output terminal OUTW.

Wherein, opto-isolator circuit 1 includes:

a first input terminal 1_ IN connected to the input terminal IN and one end of a first resistor R1;

a first output terminal 1_ OUT connected to the second input terminal 2_ IN of the dead zone compensation circuit 2, and connected to one end of the second resistor R2 and the fourth terminal of the first optocoupler U1;

one end of a first resistor R1, one end of a first resistor R1 is connected with a first input end 1_ IN, and the other end of the first resistor R1 is connected with a first end of a first optocoupler U1;

one end of a second resistor R2, one end of a second resistor R2 is connected with the power supply 12V, and the other end of the second resistor R2 is connected with the first output end 1_ OUT and the fourth end of a first optical coupler U1;

the first end of a first optical coupler U1, a first optical coupler U1 is connected with one end of a first resistor R1, the second end of the first optical coupler U1 is connected with an input signal ground, the third end of the first optical coupler U1 is connected with the ground, and the fourth end of the first optical coupler U1 is connected with one end of a fourth resistor R4 and a first output end 1_ OUT.

The dead-time compensation circuit 2 includes:

a second input end 2_ IN, where the second input end 2_ IN is respectively connected to the first output end 1_ OUT and the third resistor R3 of the optical coupler isolation circuit 1, one end of the first capacitor C1, and the first end of the first schmitt trigger U2A;

a second output/output end 2_ OUT, where the second output/output end 2_ OUT is respectively connected to the second end of the first schmitt trigger U2A and the input end 3_ IN1 of the logic processing circuit 3;

one end of a third resistor R3, one end of a third resistor R3 is connected with the second input end 2_ IN, one end of the first capacitor C1 and the first end of the first Schmitt trigger U2A, and the other end of R3 is connected with the ground;

a first capacitor C1, wherein one end of the first capacitor C1 is connected to the second input terminal 2_ IN, one end of the third resistor R3 and the first end of the first schmitt trigger U2A, respectively, and the other end of C1 is connected to ground;

a second schmitt trigger U2A, a first end of the second schmitt trigger U2A is connected to the second input terminal 2_ IN, one end of the third resistor R3, and one end of the first capacitor C1, respectively, a seventh end of the second schmitt trigger U2A is connected to ground, a fourteenth end of the second schmitt trigger U2A is connected to the power supply 12V, and a second end of the second schmitt trigger U2A is connected to the second output terminal 2_ OUT.

Wherein, the logic processing circuit 3 includes:

a third input terminal 3_ IN1, the third input terminal 3_ IN1 being connected to the second output terminal 2_ OUT of the dead time compensation circuit 2;

a third output terminal 3_ OUT1, the third output terminal 3_ OUT1 is respectively connected with the fourth input terminal 4_ IN1 of the dead zone setting circuit 4 and the fifteen terminals HA of the logic signal processing integrated circuit U3;

a fourth output terminal 3_ OUT2, the fourth output terminal 3_ OUT2 is respectively connected with the fifth input terminal 4_ IN2 of the dead zone setting circuit 4 and the fourteen terminals HB of the logic signal processing integrated circuit U3;

a fifth output terminal 3_ OUT3, the fifth output terminal 3_ OUT3 being connected to the sixth input terminal 4_ IN3 of the dead zone setting circuit 4 and the thirteen terminal HC of the logic signal processing integrated circuit U3, respectively;

a sixth output terminal 3_ OUT4, the sixth output terminal 3_ OUT4 is respectively connected with the tenth input terminal 5_ IN4 of the driving and three-phase bridge circuit 5 and the tenth terminal LA of the logic signal processing integrated circuit U3;

a seventh output terminal 3_ OUT5, the seventh output terminal 3_ OUT5 is respectively connected with the eleventh input terminal 5_ IN5 of the driving and three-phase bridge circuit 5 and the eleventh terminal LB of the logic signal processing integrated circuit U3;

an eighth output terminal 3_ OUT6, the eighth output terminal 3_ OUT6 is respectively connected with the twelfth input terminal 5_ IN6 of the driving and three-phase bridge circuit 5 and the twelve terminals LB of the logic signal processing integrated circuit U3;

a logic signal processing integrated circuit U3, a first terminal of a logic signal processing integrated circuit U3 is connected with a third input terminal 3_ IN1, a second terminal of the logic signal processing integrated circuit U3 is connected with an FR control signal, a third terminal of the logic signal processing integrated circuit U3 is connected with an EN control signal, a fourth terminal of the logic signal processing integrated circuit U3 is connected with a BR control signal, a fifth terminal of the logic signal processing integrated circuit U3 is connected with an SA control signal, a sixth terminal of the logic signal processing integrated circuit U3 is connected with an SB control signal, a seventh terminal of the logic signal processing integrated circuit U3 is connected with an SC control signal, an eighth terminal of the logic signal processing integrated circuit U3 is connected with an IL control signal, a ninth terminal of the logic signal processing integrated circuit U3 is connected with ground, a tenth terminal of the logic signal processing integrated circuit U3 is connected with a sixth output terminal 3_ OUT4, a tenth terminal of the logic signal processing integrated circuit U3 is connected with a seventh output terminal 3_ OUT5, the twelfth terminal of the logic signal processing integrated circuit U3 is connected to the eighth output terminal 3_ OUT6, the thirteenth terminal of the logic signal processing integrated circuit U3 is connected to the fifth output terminal 3_ OUT3, the fourteenth terminal of the logic signal processing integrated circuit U3 is connected to the fourth output terminal 3_ OUT2, the fifteenth terminal of the logic signal processing integrated circuit U3 is connected to the third output terminal 3_ OUT1, and the sixteenth terminal of the logic signal processing integrated circuit U3 is connected to the power supply 12V.

The dead zone setting circuit 4 includes:

a fourth input terminal 4_ IN1, the fourth input terminal 4_ IN1 being connected to the third output terminal 3_ OUT1 of the logic processing circuit 3; the fourth input terminal 4_ IN1 is respectively connected to the cathode of the first diode D1 and one end of the fourth resistor R4;

a fifth input terminal 4_ IN2, the fifth input terminal 4_ IN2 being connected to the fourth output terminal 3_ OUT2 of the logic processing circuit 3; the fifth input terminal 4_ IN2 is respectively connected to the cathode of the nineteenth diode D19 and one end of the sixth resistor R6;

a sixth input terminal 4_ IN3, the sixth input terminal 4_ IN3 being connected to the fifth output terminal 3_ OUT3 of the logic processing circuit 3; the sixth input terminal 4_ IN3 is respectively connected to the cathode of the twentieth diode D20 and one end of the eleventh resistor R11;

a ninth output terminal 4_ OUT1, the ninth output terminal 4_ OUT1 being connected to the seventh input terminal 5_ IN1 of the drive and three-phase bridge circuit 5; the ninth output terminal 4_ OUT1 is respectively connected to the anode of the first diode D1 and one end of the second capacitor C2;

a tenth output terminal 4_ OUT2, the tenth output terminal 4_ OUT2 being connected to the eighth input terminal 5_ IN2 of the drive and three-phase bridge circuit 5; the tenth output terminal 4_ OUT2 is connected to the anode of the nineteenth diode D19 and one end of the fifth capacitor C5, respectively;

an eleventh output terminal 4_ OUT3, the eleventh output terminal 4_ OUT3 being connected to the ninth input terminal 5_ IN3 of the drive and three-phase bridge circuit 5; the eleventh output terminal 4_ OUT3 is connected to the anode of the twentieth diode D20 and one terminal of the ninth capacitor C9, respectively;

the cathodes of the first diode D1 and the D1 are respectively connected to one end of the 4_ IN1 and one end of the fourth resistor R4, and the anode of the D1 is respectively connected to one end of the ninth output terminal 4_ OUT1, one end of the fourth resistor R4 and one end of the second capacitor C2;

one end of a fourth resistor R4, one end of the fourth resistor R4 is respectively connected with the fourth input end 4_ IN1 and the cathode of the first diode D1, and the other end of the fourth resistor R4 is respectively connected with the ninth output end 4_ OUT1, the anode of the first diode D1 and one end of the second capacitor C2;

one end of a second capacitor C2, one end of the second capacitor C2 is connected to the ninth output terminal 4_ OUT1, one end of the fourth resistor R4, and the anode of the first diode D1, and the other end of the second capacitor C2 is grounded;

a nineteenth diode D19, a cathode of the nineteenth diode D19 is connected to the fifth input terminal 4_ IN2 and one end of the sixth resistor R6, respectively, and an anode of the nineteenth diode D19 is connected to the tenth output terminal 4_ OUT2, one end of the sixth resistor R6, and one end of the fifth capacitor C5, respectively;

one end of a sixth resistor R6, one end of the sixth resistor R6 is respectively connected with the fifth input end 4_ IN2 and the cathode of the nineteenth diode D19, and the other end of the sixth resistor R6 is respectively connected with the tenth output end 4_ OUT2, the anode of the nineteenth diode D19 and one end of a fifth capacitor C5;

one end of a fifth capacitor C5, one end of the fifth capacitor C5 is connected to the tenth output terminal 4_ OUT2, one end of a sixth resistor R6, and the anode of a nineteenth diode D19, respectively, and the other end of the fifth capacitor C5 is grounded;

a twentieth diode D20, a cathode of the twentieth diode D20 is connected to the sixth input terminal 4_ IN3 and one end of the eleventh resistor R11, respectively, and an anode of the twentieth diode D20 is connected to the eleventh output terminal 4_ OUT3, one end of the eleventh resistor R11, and one end of the ninth capacitor C9, respectively;

an eleventh resistor R11, wherein one end of the eleventh resistor R11 is connected to the sixth output terminal 4_ IN3 and the cathode of the twentieth diode D20, respectively, and the other end of the eleventh resistor R11 is connected to the anodes of the eleventh output terminals 4_ OUT3 and D20 and one end of the ninth capacitor C9, respectively;

one end of a ninth capacitor C9 and one end of a ninth capacitor C9 are connected to the eleventh output terminal 4_ OUT3, one end of an eleventh resistor R11 and the anode of D20, respectively, and the other end of the ninth capacitor C9 is grounded.

Wherein, drive and three-phase bridge circuit 5 includes:

a seventh input terminal 5_ IN1, the seventh input terminal 5_ IN1 being connected to the ninth output terminal 4_ OUT1 of the dead zone setting circuit 4 and the tenth terminal of the sixth drive circuit U6, respectively;

an eighth input terminal 5_ IN2, the eighth input terminal 5_ IN2 being connected to the tenth output terminal 4_ OUT2 of the dead zone setting circuit 4 and the tenth terminal of the fifth drive circuit U5, respectively;

a ninth input terminal 5_ IN3, the ninth input terminal 5_ IN3 being connected to the eleventh output terminal 4_ OUT3 of the dead zone setting circuit 4 and the tenth terminal of the fourth driving circuit U4, respectively;

a tenth input terminal 5_ IN4, the tenth input terminal 5_ IN4 being connected to the sixth output terminal 3_ OUT4 of the logic processing circuit 3 and the twelfth terminal of the sixth driving circuit U6, respectively;

an eleventh input terminal 5_ IN5, the eleventh input terminal 5_ IN5 being connected to the eighth output terminal 3_ OUT5 of the logic processing circuit 3 and the twelfth terminal of the fifth driving circuit U5, respectively;

a twelfth input terminal 5_ IN6, the twelfth input terminal 5_ IN6 being connected to the eighth output terminal 3_ OUT6 of the logic processing circuit 3 and the twelfth terminal of the fourth driving circuit U4, respectively;

a fourteenth output terminal 5_ OUT1, the fourteenth output terminal 5_ OUT1 being connected to the U-phase output terminal OUTU, the fifth terminal of the sixth driving circuit U6, and one terminal of the sixteenth capacitor C16, respectively;

a thirteenth output terminal 5_ OUT2, wherein the thirteenth output terminal 5_ OUT2 is respectively connected to the V-phase output terminal OUTV, the fifth terminal of the fifth driving circuit U5, and one terminal of a thirteenth capacitor C13;

a twelfth output terminal 5_ OUT3, the twelfth output terminal 5_ OUT3 is respectively connected to the W-phase output terminal OUTW, the fifth terminal of the fourth driving circuit U4, and one terminal of the tenth capacitor C10;

a sixth driving circuit U6, IN which a first terminal of the sixth driving circuit U6 is connected to one terminal of a sixteenth resistor R16, a second terminal of the sixth driving circuit U6 is connected to ground, a third terminal of the sixth driving circuit U6 is connected to a power supply 12V, a fifth terminal of the sixth driving circuit U6 is connected to one terminals of a fourteenth output terminal 5_ OUT1 and a sixteenth capacitor C16, respectively, a sixth terminal of the sixth driving circuit U6 is connected to both a negative terminal of a twenty-third diode D23 and one terminal of the sixteenth capacitor C16, a seventh terminal of the sixth driving circuit U6 is connected to one terminal of a seventeenth resistor R17, a ninth terminal of the sixth driving circuit U6 is connected to the power supply 12V, a tenth terminal of the sixth driving circuit U6 is connected to a seventh input terminal 5_ IN1, a tenth terminal of the sixth driving circuit U6 is connected to a tenth input terminal 5_ IN4, and a third terminal of the sixth driving circuit U6 is connected to a tenth terminal of the ground;

one end of a seventeenth resistor R17, one end of the seventeenth resistor R17 is connected with the seventh end of the sixth driving circuit U6, and the other end of the seventeenth resistor R17 is connected with the gate of the fifth power transistor M5;

one end of a sixteenth resistor R16, one end of a sixteenth resistor R16 is connected with the first end of the sixth driving circuit U6, and the other end of the sixteenth resistor R16 is connected with the grid electrode of the sixth power tube M6;

one end of a sixteenth capacitor C16, one end of the sixteenth capacitor C16 is connected to the fourteenth output terminal 5_ OUT1 and the fifth end of the sixth driving circuit U6, respectively, and the other end of the sixteenth capacitor C16 is connected to the cathode of the twenty-third diode D23 and the sixth end of the sixth driving circuit U6, respectively;

a seventeenth capacitor C17, wherein one end of the seventeenth capacitor C17 is connected with a power supply 12V, and the other end of the seventeenth capacitor C17 is grounded;

one end of an eighteenth capacitor C18 and one end of an eighteenth capacitor C18 are connected with a power supply 12V, and the other end of the eighteenth capacitor C18 is grounded;

a twenty-third diode D23, a cathode of the twenty-third diode D23 is connected to the sixth terminal of the sixth driving circuit U6 and one end of the sixteenth capacitor C16, respectively, and an anode of the twenty-third diode D23 is connected to the power supply 12V;

a grid electrode of the fifth power tube M5, a grid electrode of the fifth power tube M5 is connected with one end of a seventeenth resistor R17, a drain electrode of the fifth power tube M5 is connected with a power supply VPower, and a source electrode of the fifth power tube M5 is connected with drain electrodes of a fourteenth output end 5_ OUT1 and a sixth power tube M6 respectively;

a gate of the sixth power tube M6, a gate of the sixth power tube M6 is connected to one end of the sixteenth resistor R16, a drain of the sixth power tube M6 is connected to the fourteenth output terminal 5_ OUT1 and the source of the fifth power tube M5, respectively, and a source of the sixth power tube M6 is grounded;

a fifth driving circuit U5, IN which a first terminal of the fifth driving circuit U5 is connected to one terminal of a fourteenth resistor R14, a second terminal of the fifth driving circuit U5 is connected to ground, a third terminal of the fifth driving circuit U5 is connected to a power supply 12V, a fifth terminal of the fifth driving circuit U5 is connected to one terminal of a thirteenth output terminal 5_ OUT2 and a thirteenth capacitor C13, respectively, a sixth terminal of the fifth driving circuit U5 is connected to a cathode of a twenty-second diode D22 and one terminal of a thirteenth capacitor C13, respectively, a seventh terminal of the fifth driving circuit U5 is connected to one terminal of a fifteenth resistor R15, a ninth terminal of the fifth driving circuit U5 is connected to the power supply 12V, a tenth terminal of the fifth driving circuit U5 is connected to an eighth input terminal 5_ IN2, a tenth terminal of the fifth driving circuit U5 is connected to an eleventh input terminal 5_ IN5, and a third terminal of the fifth driving circuit U5 is connected to a tenth terminal of the ground;

one end of a fifteenth resistor R15, one end of the fifteenth resistor R15 is connected with the seventh end of the fifth driving circuit U5, and the other end of the fifteenth resistor R15 is connected with the gate of the third power tube M3;

one end of a fourteenth resistor R14, one end of the fourteenth resistor R14 is connected with the first end of the fifth driving circuit U5, and the other end of the fourteenth resistor R14 is connected with the gate of the fourth power tube M4;

a thirteenth capacitor C13, wherein one end of the thirteenth capacitor C13 is connected to the thirteenth input terminal 5_ OUT2 and the fifth end of the fifth driving circuit U5, respectively, and the other end of the thirteenth capacitor C13 is connected to the cathode of the twenty-second diode D22 and the sixth end of the fifth driving circuit U5, respectively;

a fourteenth capacitor C14, one end of the fourteenth capacitor C14 is connected with the power supply 12V, and the other end of the fourteenth capacitor C14 is grounded;

a fifteenth capacitor C15, wherein one end of the fifteenth capacitor C15 is connected with the power supply 12V, and the other end of the fifteenth capacitor C15 is grounded;

a twenty-second diode D22, a cathode of the twenty-second diode D22 is connected to the sixth terminal of the fifth driving circuit U5 and one terminal of the thirteenth capacitor C13, and an anode of the twenty-second diode D22 is connected to the power supply 12V;

a gate of the third power tube M3, a gate of the third power tube M3 is connected to one end of a fifteenth resistor R15, a drain of the third power tube M3 is connected to a power supply VPower, and a source of the third power tube M3 is connected to drains of a thirteenth output terminal 5_ OUT2 and a fourth power tube M4, respectively;

a gate of the fourth power tube M4, a gate of the fourth power tube M4 is connected to one end of a fourteenth resistor R14, a drain of the fourth power tube M4 is connected to the thirteenth output terminal 5_ OUT2 and the source of the third power tube M3, respectively, and the source of the fourth power tube M4 is grounded;

a fourth driving circuit U4, IN which a first terminal of the fourth driving circuit U4 is connected to one terminal of a thirteenth resistor R13, a second terminal of the fourth driving circuit U4 is connected to ground, a third terminal of the fourth driving circuit U4 is connected to a power supply 12V, a fifth terminal of the fourth driving circuit U4 is connected to one terminals of a twelfth output terminal 5_ OUT3 and a tenth capacitor C10, a sixth terminal of the fourth driving circuit U4 is connected to a cathode of a twenty-first diode D21 and one terminal of a tenth capacitor C10, a seventh terminal of the fourth driving circuit U4 is connected to one terminal of a twelfth resistor R12, a ninth terminal of the fourth driving circuit U4 is connected to the power supply 12V, a tenth terminal of the fourth driving circuit U4 is connected to a ninth input terminal 5_ IN3, a tenth terminal of the fourth driving circuit U4 is connected to a twelfth input terminal 5_ IN6, and a tenth terminal of the fourth driving circuit U4 is connected to ground;

one end of a twelfth resistor R12, one end of the twelfth resistor R12 is connected with the seventh end of the fourth driving circuit U4, and the other end of the twelfth resistor R12 is connected with the grid electrode of the first power tube M1;

one end of a thirteenth resistor R13, one end of the thirteenth resistor R13 is connected with the first end of the fourth driving circuit U4, and the other end of the thirteenth resistor R13 is connected with the grid electrode of the second power tube M2;

a tenth capacitor C10, wherein one end of the tenth capacitor C10 is connected to the twelfth output terminal 5_ OUT3 and the fifth end of the fourth driving circuit U4, respectively, and the other end of the tenth capacitor C10 is connected to the cathode of the twenty-first diode D21 and the sixth end of the fourth driving circuit U4, respectively;

an eleventh capacitor C11, wherein one end of the eleventh capacitor C11 is connected with a power supply 12V, and the other end of the eleventh capacitor C11 is grounded;

a twelfth capacitor C12, wherein one end of the twelfth capacitor C12 is connected with a power supply 12V, and the other end of the twelfth capacitor C12 is grounded;

a twenty-first diode D21, wherein the cathode of the twenty-first diode D21 is respectively connected with the sixth end of U45 and one end of C10, and the anode of the twenty-first diode D21 is connected with the power supply 12V;

a grid electrode of the first power tube M1, a grid electrode of the first power tube M1 is connected with one end of the twelfth resistor R12, a drain electrode of the first power tube M1 is connected with the power supply VPower, and a source electrode of the first power tube M1 is connected with a drain electrode of the twelfth output end 5_ OUT3 and the second power tube M2 respectively;

a gate of the second power transistor M2, a gate of the second power transistor M2 is connected to one end of the thirteenth resistor R13, a drain of the second power transistor M2 is connected to the twelfth output terminal 5_ OUT3 and a source of the first power transistor M1, respectively, and a source of the second power transistor M2 is grounded.

The three-phase brushless motor driving circuit provided by the embodiment of the invention comprises an optical coupling isolation circuit, a dead zone compensation circuit, a logic processing circuit, a dead zone setting circuit and a driving and three-phase bridge circuit, and can effectively eliminate the problem that an output power tube is in common-state direct connection, the dead zone compensation circuit pre-expands an optical coupling output signal according to the dead zone time of the three-phase brushless motor driving circuit, reduce the loss of the input PWM pulse width and avoid the problem that the motor cannot normally rotate when the input PWM pulse width is smaller.

Optionally, in the three-phase brushless motor driving circuit provided by the embodiment of the present invention, the dead-zone compensation circuit and the dead-zone setting circuit are matched to effectively solve the problem of loss of input PWM pulse width, and especially when the input PWM pulse width is small, the motor can be maintained to normally rotate.

Optionally, the dead-zone compensation circuit can be composed of a universal resistor, a universal capacitor and a schmitt trigger, and is simple in circuit structure and cost-saving.

Optionally, the three-phase brushless motor driving circuit provided by the embodiment of the invention has the advantages of fewer adopted components, small volume, low cost, no need of debugging and convenience for mass production.

Optionally, the three-phase brushless motor driving circuit provided by the embodiment of the invention can solve the problem that the motor cannot rotate when the pulse width of the PWM input is small, and when the optical coupling output signal is not pre-broadened, the minimum duty ratio of the rotation of the motor can only reach 5% -8%; after the optical coupler output signal is pre-broadened through the dead zone compensation circuit, the minimum duty ratio of the rotation of the motor can reach 0.1%.

Optionally, the dead-time compensation circuit is a conventional circuit, and the dead-time compensation circuit can adjust the dead-time compensation according to the dead-time.

The embodiment of the invention also provides a three-phase brushless motor driver, which comprises the three-phase brushless motor driving circuit in any embodiment.

In this embodiment, the three-phase brushless motor driver substantially includes the three-phase brushless motor driving circuit in the above embodiment, and specific functions and technical effects are only required by referring to the three-phase brushless motor driving circuit in the above embodiment, which is not described herein again.

An embodiment of the present invention further provides an electronic device, including the three-phase brushless motor driver according to any of the above embodiments.

In this embodiment, the electronic device substantially includes the three-phase brushless motor driver in the above embodiment, and specific functions and technical effects are only required to refer to the three-phase brushless motor driving circuit in the above embodiment, which is not described herein again.

Example two

An embodiment of the present invention further provides a dead zone compensation method for a three-phase brushless motor driver, and referring to fig. 4, the method applied to the three-phase brushless motor driver according to the above embodiment includes:

s401: acquiring dead time of a three-phase brushless motor driver;

s402: and adjusting the capacitance value of a first capacitor in the dead-zone compensation circuit according to the dead-zone time, and pre-widening the optical coupling output signal.

That is, the dead time is set as the compensation time, so that the compensation dead time can be adjusted according to the dead time, and the problem that the motor cannot rotate when the PWM input pulse width is smaller is solved

Optionally, the dead-time compensation method for the three-phase brushless motor driver is applied to a three-phase brushless motor driver including a three-phase brushless motor driving circuit with an optical coupling isolation circuit and a dead-time compensation circuit, and taking the three-phase brushless motor driving circuit shown in fig. 3 as an example, the capacitance value of the first capacitor is determined as follows:

wherein, C₁Is the capacitance value of the first capacitor, R₂Is the resistance value of the second resistor, R₃Is the resistance value of the third resistor, V_CCIs 12V, V_THAt is the upper threshold voltage, Δ T is the dead time.

The dead time Δ T and the upper threshold voltage V are_THThe determination method can be determined by adopting the existing related technology, and is not described in detail herein.

According to the embodiment of the invention, the dead time of the three-phase brushless motor driver is obtained, the compensation time is determined, the capacitance value of the first capacitor in the dead time compensation circuit is adjusted, the optocoupler output signal is pre-broadened, the adjustment of the compensated dead time according to the dead time can be realized, the dead time is more accurate, and the problem that the motor cannot rotate when the PWM input pulse width is smaller is specifically solved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.