阅读说明：本技术 一种多轴绝对编码器解算电路系统 (Multi-axis absolute encoder resolving circuit system ) 是由 徐立 王金 徐勇 喻凯 于 2019-09-20 设计创作，主要内容包括：本发明公开了一种五轴绝对式编码器解算解算电路系统,包括：FPGA模块,时钟信号转换电路,数据信号转换电路,同步信号输出,ISA位置信号输出及绝对式编码器接口。其特征在于：FPGA模块发送统一的10K时钟信号,其中五路信号经过收发器送入到五个角度编码器,第六路经过收发器后,通过IO口,输出同步信号给用户使用；FPGA模块发送位置信息采集指令到五个角度编码器,五个编码器的位置信息经过5路收发器,五路控制信号分别控制信号转换电路,依次通过一路接收端传送到FPGA模块进行五个编码器的位置解算,并通过位置输出接口传送到工控机。总体设计实现了五个绝对式角度编码器的位置信息解算及提供高精度的时钟同步信号,克服了现有技术的不足。(The invention discloses a five-axis absolute encoder resolving circuit system, which comprises: the system comprises an FPGA module, a clock signal conversion circuit, a data signal conversion circuit, a synchronous signal output, an ISA position signal output and an absolute encoder interface. The method is characterized in that: the FPGA module sends a uniform 10K clock signal, wherein five paths of signals are sent to five angle encoders through a transceiver, and a sixth path of signals are sent to the transceivers and then output synchronous signals to users through an IO port; the FPGA module sends a position information acquisition instruction to five angle encoders, position information of the five encoders passes through the 5-path transceiver, five control signals respectively control the signal conversion circuit, the position information is transmitted to the FPGA module through one receiving end to be resolved by the five encoders, and the position information is transmitted to the industrial personal computer through the position output interface. The overall design realizes the position information resolving of five absolute type angle encoders and provides a high-precision clock synchronization signal, and overcomes the defects of the prior art.)

1. A five-axis absolute encoder solution circuitry, comprising: the system comprises an FPGA module, a clock signal conversion circuit, a data signal conversion circuit, a synchronous signal output, an ISA position output, a download interface, a storage interface, a high-precision crystal oscillator interface and an absolute encoder interface.

2. The clock signal conversion circuit of claim 1, wherein: the FPGA sends a uniform clock signal to the five encoders through the clock signal conversion circuit.

3. The data signal conversion circuit of claim 1, wherein: the FPGA sends a control signal to the transceiver to control the input of the transceiver instruction and the output of the data, and the five paths of data are transmitted to the FPGA through one port.

4. The synchronization signal output circuit according to claim 1, characterized in that: the FPGA sends 10K signals, and the signals are transmitted to the IO interface through the transceiver and are provided for users to use.

5. The absolute encoder solution circuitry according to claims 1, 2, 3 and 4, wherein: position information can be analyzed for the five angle encoders at the same time, and the position information is output to the industrial personal computer through the ISA position; the clock synchronization signal with high precision can be output and provided for users.

Technical Field

The present invention relates to a resolving circuit system for absolute angular position resolution of absolute encoders, and more particularly to angular position resolution of five axes.

Background

Currently, angular encoders are widely used in the field of industrial control. The resolving circuit sold on the market can only provide the function of resolving the absolute angular position from a single axis to three axes, and meanwhile, the function of high-precision synchronous signals cannot be met. For a resolving circuit which needs to resolve the angular positions of five axes at the same time and has a high-precision synchronous signal output function, the resolving circuit sold on the market cannot meet the practical requirements of users. A resolving circuit system for resolving the absolute angular position of a multi-axis absolute encoder can resolve the angular positions of five axes simultaneously and can provide high-precision synchronous signals for users to meet the use requirements of the users. The design and implementation of a multi-axis absolute encoder resolving circuit system are applied to the field of industrial control, and good effects are achieved.

Disclosure of Invention

The invention aims to provide a five-axis absolute encoder resolving circuit system which can complete the position information resolving function and the high-precision synchronous signal output function of an absolute encoder.

The technical scheme adopted by the invention for solving the technical problems is as follows: firstly, the FPGA module sends a uniform clock signal to the five angle encoders through the clock signal conversion circuit, the sixth clock signal passing through the clock signal conversion circuit is used as a clock synchronization signal of a user through an IO port, and on the other hand, sends a control signal to the data signal conversion circuit to control the output of an instruction and the input of data. And then, under the condition that the position information is effectively output by the signal conversion circuit, the five angle encoders send the position information into the FPGA through a receiving port to carry out position calculation. And finally, the FPGA transmits the position information of each shaft to the industrial personal computer at a period of 1ms through an ISA interface.

The invention has the following advantages: first, position information for up to 5 encoders can be resolved; second, a high-precision synchronization signal can be provided to the user.

Drawings

Fig. 1 is a schematic diagram of the overall structure of a multi-axis absolute type calculation circuit system.

Fig. 2 is a block diagram of a clock signal conversion circuit of the multi-axis absolute type calculation circuit system.

Fig. 3 is a block diagram of a data signal conversion circuit of the multi-axis absolute resolver circuit system.

Fig. 4 is a block diagram of a multi-axis absolute solution circuitry clock synchronization signal.

Detailed Description

Example (b):

as shown in FIG. 1: the multi-axis absolute solution circuit system comprises: the system comprises an FPGA module 2, a clock signal conversion circuit 5, a data signal conversion circuit 6, a synchronous signal output 3, an ISA position signal output 1, a download interface and storage 7, a high-precision crystal oscillator 8 and an absolute encoder interface 4.

As shown in fig. 2: providing a clock signal of the FPGA module 2 through an external high-precision crystal oscillator 4, carrying out frequency division on the clock signal by the FPGA module 2 to obtain a sending periodic signal of 10K on one hand, and processing the clock signal into a sampling periodic signal of 500K on the other hand, wherein the time period is long by 100 us; the 500K acquisition signals are transmitted to the five-path transceiver in a carrier wave mode through a 10K transmission period, and are transmitted to the five angle encoders through the absolute encoder interface 8 after being converted.

As shown in fig. 3: the FPGA module 2 sends a position information acquisition instruction and a control signal, the control signal controls the five-channel transceiver to be in an output state, and the position information acquisition instruction is sent to each encoder through the absolute encoder interface 4; after receiving the clock signal and the position information acquisition instruction, each encoder sends position information to the five transceiver circuits through the absolute encoder interface 4. The FPGA module 2 sends control signals to five transceivers in a period of 5K: in the first period, the input of the first transceiver is valid, the inputs of the other four paths are invalid, in the second period, the input of the second transceiver is valid, the inputs of the other four paths are invalid, in the third period, the input of the third transceiver is valid, the inputs of the other four paths are invalid, in the fourth period, the input of the fourth transceiver is valid, the inputs of the other four paths are invalid, in the fifth period, the input of the fifth transceiver is valid, and the inputs of the other four paths are invalid. The position information is transmitted to the FPGA module 2 through the 1-path receiving signal RX by adopting a time division multiplexing principle to be resolved.

As shown in fig. 4: the FPGA module 2 is used for providing clock signals through an external high-precision crystal oscillator 4, the FPGA module 2 is used for dividing the frequency of the clock signals to obtain clock period signals of 10K, the clock period signals are sent to a sixth transceiver, and the clock period signals are converted and output through an IO port 3 to be provided for users.