阅读说明：本技术 单字线的自旋轨道矩磁性随机存储器 (Spin orbit torque magnetic random access memory with single word line ) 是由 薛晓勇 赵晨阳 方晋北 陈德扬 杨何勇 张洵铭 于 2020-11-20 设计创作，主要内容包括：本发明属于存储器技术领域,具体为一种单字线的自旋轨道矩磁性随机存储器。本发明存储器的存储单元包括：一个重金属导电层、一个磁阻元件和两个开关元件；磁阻元件有三层,分别是磁化方向固定的磁性材料层、非磁性材料层、磁化方向可变的磁性材料层；第一开关元件用于控制存储单元写入通路的导通或关闭,第二开关元件用于控制存储单元读取通路的导通或关闭；当第一开关元件是NMOS管时,第二开关元件是PMOS管；当第一开关元件是PMOS管时,第二开关元件是NMOS管。本发明的自旋轨道矩磁性随机存储器,利用NMOS管和PMOS管分别控制写入和读取操作,从而将传统方案中的写字线与读字线合并,实现减小面积代价、简化控制逻辑的效果。(The invention belongs to the technical field of memories, and particularly relates to a spin orbit torque magnetic random access memory of a single word line. The memory cell of the memory of the present invention comprises: a heavy metal conductive layer, a magnetoresistive element, and two switching elements; the magnetic resistance element has three layers, namely a magnetic material layer with fixed magnetization direction, a non-magnetic material layer and a magnetic material layer with variable magnetization direction; the first switch element is used for controlling the on-off of a writing path of the storage unit, and the second switch element is used for controlling the on-off of a reading path of the storage unit; when the first switch element is an NMOS tube, the second switch element is a PMOS tube; when the first switch element is a PMOS tube, the second switch element is an NMOS tube. The spin orbit torque magnetic random access memory of the invention utilizes the NMOS tube and the PMOS tube to respectively control the writing and reading operations, thereby combining the writing line and the reading word line in the traditional scheme and realizing the effects of reducing the area cost and simplifying the control logic.)

1. A spin orbit torque magnetic random access memory of single word line, wherein its memory cell includes a heavy metal conducting layer, a magneto-resistive element, a NMOS tube and a PMOS tube; the first end of the NMOS tube is connected with a write bit line; the second end of the NMOS tube is connected with the first end of the heavy metal conducting layer; the control end of the NMOS tube is connected with a word line; the second end of the heavy metal conducting layer is connected with a source line; the first end of the magnetic resistance element is connected with the first end of the PMOS tube; the second end of the magnetic resistance element is abutted to the middle position between the first end and the second end of the heavy metal conducting layer; the second end of the PMOS tube is connected with a read bit line; and the control end of the PMOS tube is connected with a word line.

2. The spin-orbit torque magnetic random access memory of claim 1, wherein the heavy metal conductive layer is platinum, tantalum, gold, tungsten or palladium.

3. The spin-orbit torque magnetic random access memory according to claim 1, wherein the magnetoresistive element is composed of three layers, a first layer being a magnetic material layer whose magnetization direction is fixed, a second layer being a non-magnetic material layer, and a third layer being a magnetic material layer whose magnetization direction is variable; the magnetic material layer with the fixed magnetization direction of the magnetic resistance element is used as a first end of the magnetic resistance element, and the magnetic material layer with the variable magnetization direction of the magnetic resistance element is used as a second end of the magnetic resistance element and is abutted to the middle position between the first end and the second end of the heavy metal conducting layer.

4. The spin-orbit torque magnetic random access memory of claim 1, wherein the NMOS transistor is used to control the turn-on or turn-off of the write path of the memory cell.

5. The spin-orbit torque magnetic random access memory of claim 1, wherein the PMOS transistor is used to control the turn-on or turn-off of the read path of the memory cell.

6. A spin orbit torque magnetic random access memory of single word line, wherein its memory cell includes a heavy metal conducting layer, a magneto-resistive element, a NMOS tube and a PMOS tube; the first end of the PMOS tube is connected with a write bit line; the second end of the PMOS tube is connected with the first end of the heavy metal conducting layer; the control end of the PMOS tube is connected with a word line; the second end of the heavy metal conducting layer is connected with a source line; the first end of the magnetic resistance element is connected with the first end of the NMOS tube; the second end of the magnetic resistance element is abutted to the middle position between the first end and the second end of the heavy metal conducting layer; the second end of the NMOS tube is connected with a read bit line; and the control end of the NMOS tube is connected with a word line.

7. The spin-orbit torque magnetic random access memory of claim 6, wherein the heavy metal conductive layer is platinum, tantalum, gold, tungsten or palladium.

8. The spin-orbit torque magnetic random access memory according to claim 6, wherein the magnetoresistive element is composed of three layers, a first layer being a magnetic material layer whose magnetization direction is fixed, a second layer being a non-magnetic material layer, and a third layer being a magnetic material layer whose magnetization direction is variable; the magnetic material layer with the fixed magnetization direction of the magnetic resistance element is used as a first end of the magnetic resistance element, and the magnetic material layer with the variable magnetization direction of the magnetic resistance element is used as a second end of the magnetic resistance element and is abutted to the middle position between the first end and the second end of the heavy metal conducting layer.

9. The spin-orbit torque magnetic random access memory of claim 6, wherein the NMOS transistor is used to control the turn-on or turn-off of the write path of the memory cell.

10. The spin-orbit torque magnetic random access memory of claim 6, wherein the PMOS transistor is used to control the turn-on or turn-off of the read path of the memory cell.

Technical Field

The invention belongs to the technical field of memories, and particularly relates to a spin orbit torque magnetic random access memory.

Background

Static Random Access Memory (SRAM) has been the mainstream solution for on-chip embedded memories for the past decades. With the continuous development of the process and the design technology, the number of processor cores integrated on a single integrated circuit is increased, so that the requirements of a single chip on the integration level, the capacity and the bandwidth of the on-chip static random access memory are increased. Therefore, with these increasing requirements, the development of static random access memory is rapid during the decades of 1994-2008: at each new process generation, the cell area of the sram is reduced by half. In recent years, however, this trend has been met with great resistance. The reduction of the process size increases the difficulty of process manufacturing, and random variation of parameters in the manufacturing process causes fluctuation of the threshold voltage of a device, so that the stability of a memory cell is influenced, and a high-density memory array is difficult to have a wide noise margin. This also limits the performance improvement and power consumption reduction of high-density static random access memory, and thus the static random access memory cannot be developed in a given direction. Therefore, finding new memory solutions to replace sram becomes a necessary route to further significantly improve chip performance.

Further, we require that the next generation memory solution have the following four characteristics at the same time: low power consumption, high performance, good compatibility with CMOS standard process and strong scalability. Spin-orbit-torque Magnetic Random Access Memory (SOT MRAM) is thus a competitor, being made non-volatile based on Magnetic Tunnel Junction (MTJ), with very low static power consumption; the read-write path can be optimized independently, and the dynamic power consumption is quite low; the read-write speed is high, the integration is easy, and the CMOS standard process is compatible; in addition, the durability of the sensor is almost unlimited, and the retentivity at normal temperature is over 10 years, so that the sensor has great potential in the fields of sensor networks, Internet of things, big data and the like.

However, compared with other schemes, the basic spin orbit torque magnetic random access memory scheme has a large area of a single memory cell and complicated control logic — one memory cell is composed of two MOS transistors and one magnetic tunnel junction and is controlled by one source line, two word lines (write word line and read word line), and two bit lines (write bit line and read bit line). Although the existing solutions for reducing the area cost and simplifying the control logic exist, the operability of the solutions is not strong, and the problem still remains to be solved.

Disclosure of Invention

The invention aims to provide a spin orbit torque magnetic random access memory scheme with low area cost and simple control logic.

The invention provides a single-word line spin-orbit torque magnetic random access memory, wherein a storage unit of the single-word line spin-orbit torque magnetic random access memory comprises a heavy metal conducting layer, a magnetoresistive element and two switching elements. The first switch element has a first terminal connected to the write bit line, a second terminal connected to the first terminal of the heavy metal conductive layer, and a control terminal connected to the word line. And the second end of the heavy metal conducting layer is connected with the source line. The first end of the magnetic resistance element is connected with the first end of the second switch element, and the second end of the magnetic resistance element is adjacent to the middle position between the first end and the second end of the heavy metal conducting layer. The second terminal of the second switching element is connected to the read bit line and the control terminal is connected to the word line.

The heavy metal conductive layer may be platinum, tantalum, gold, tungsten, or palladium.

The magnetoresistive element is composed of three layers, the first layer being a magnetic material layer whose magnetization direction is fixed, the second layer being a non-magnetic material layer, and the third layer being a magnetic material layer whose magnetization direction is variable. The magnetic material layer with fixed magnetization direction is used as the first end of the magnetic resistance element, and the magnetic material layer with variable magnetization direction is used as the second end of the magnetic resistance element and is abutted to the middle position between the first end and the second end of the heavy metal conducting layer.

The first switch element is used for controlling the on or off of a writing path of the storage unit. The second switch element is used for controlling the on or off of the reading path of the memory cell. When the first switching element is an NMOS tube, the second switching element is a PMOS tube; when the first switching element is a PMOS transistor, the second switching element is an NMOS transistor. And controlling the first switch element to conduct the write-in path, and applying a certain voltage difference between the write bit line and the source line to enable write-in current to pass through the heavy metal conducting layer, so that the resistance state of the magnetoresistive element can be changed, and data can be stored in the memory cell. And controlling the second switch element to conduct the reading path, applying a certain voltage difference between the reading bit line and the source line, reading the current passing through the magnetoresistive element, and judging the resistance state of the magnetoresistive element, thereby realizing the data reading of the memory cell.

According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the spin orbit torque magnetic random access memory of the single word line provided by the invention utilizes the NMOS tube and the PMOS tube to respectively control the writing operation and the reading operation, thereby combining the writing line and the reading word line in the traditional scheme, and realizing the effects of reducing the area cost and simplifying the control logic.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only one embodiment of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.

FIG. 1 is a circuit diagram of a first hardware implementation of a single word line spin-orbit torque magnetic random access memory cell of the present invention;

FIG. 2 is a memory array of a first type of spin-orbit torque based magnetic random access memory cell;

FIG. 3 is a circuit diagram of a second hardware implementation of a single word line spin-orbit torque magnetic random access memory cell of the present invention;

FIG. 4 is a memory array of a second type of spin-orbit torque based magnetic random access memory cell.

Reference numerals in the figures

100 is a first hardware implementation circuit diagram of a single word line spin-orbit torque magnetic random access memory storage unit of the present invention; 110 is a magnetoresistive element; 110 a is a magnetic material layer in which the magnetization direction of the magnetoresistive element is fixed; 110 b is a non-magnetic material layer of the magnetoresistive element; 110 c is a magnetic material layer in which the magnetization direction of the magnetoresistive element is changeable; 111 is a heavy metal conductive layer; 120 is an NMOS tube; 121 is a PMOS tube; 130 is a port to which a write bit line is connected; 131 is a port for connecting a word line; 132 is a port for connecting a source line; 133 is a port to which a read bit line is connected.

200 is a memory array based on first spin orbit torque magnetic random access memory cells; 210 is a word line connecting the memory cells of the first row; 211 is a word line connecting the memory cells of the second row; 212 is a word line connecting the memory cells in the Nth row; 220 is a source line connecting the memory cells in the first row; 221 is a source line connecting the memory cells of the second row; 222 is a source line connecting the memory cells in the Nth row; 230 is the write bit line connecting the memory cells of the first column; 231 is a write bit line connecting the memory cells of the second column; 232 is the write bit line connecting the memory cells in the Mth column; 330 is a read bit line connecting the memory cells in the first column; 331 is a read bit line connecting the memory cells in the second column; 332 is a read bit line connecting the memory cells in the Mth column.

300 is a circuit diagram of a second hardware implementation of a single word line spin-orbit torque magnetic random access memory cell of the present invention; 310 is a magnetoresistive element; 310 a is a magnetic material layer in which the magnetization direction of the magnetoresistive element is fixed; 310 b is a non-magnetic material layer of the magnetoresistive element; 310 c is a magnetic material layer whose magnetization direction of the magnetoresistive element is changeable; 311 is a heavy metal conductive layer; 320 is a PMOS tube; 321 is an NMOS tube; 330 is a port to which a write bit line is connected; 331 is a port connecting word lines; 332 is a port for connecting a source line; 333 is a port to which the read bit line is connected.

400 is a memory array based on second type spin orbit torque magnetic random access memory cells; 410 is a word line connecting the memory cells of the first row; 411 is a word line connecting the memory cells of the second row; 412 is the word line connecting the memory cells in row N; 420 is a source line connecting the memory cells of the first row; 421 is the source line connecting the second row of memory cells; 422 is a source line connected with the memory cells in the Nth row; 430 is a write bit line connecting the memory cells of the first column; 431 is a write bit line connecting the second column of memory cells; 432 is a write bit line connecting the memory cells in column M; 430 is a read bit line connecting the memory cells of the first column; 431 is a read bit line connecting the memory cells of the second column; and 432 is a read bit line connecting the memory cells in the mth column.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiment is only one embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a circuit diagram of a first hardware implementation of a single word line spin-orbit torque magnetic random access memory cell of the present invention. As shown in fig. 1, when it is desired to write a "1" (or a "0", depending on the magnetic field applied to the magnetoresistive element) to the memory cell, a positive voltage VDD is applied to the word line, a positive voltage VWP is applied to the write bit line, and a zero voltage is applied to the source line; when it is desired to write a "0" (or a "1", depending on the magnetic field applied to the magnetoresistive element) into the memory cell, a positive voltage VDD is applied to the word line, a negative voltage VWN is applied to the write bit line, and a zero voltage is applied to the source line; when the data in the memory cell needs to be read, zero voltage is applied to the word line, reading voltage VREAD is applied to the reading bit line, zero voltage is applied to the source line, and the data in the target memory cell can be obtained by reading the current on the reading bit line or the source line.

FIG. 2 is a memory array of a first type of spin-orbit torque based magnetic random access memory cell. As shown in fig. 2, a row of the memory array has M memory cells, and the data stored in the M memory cells form a word; a column of the memory array has N memory cells. If the write operation for a specific word is to be completed, a positive voltage VDD is applied to the corresponding word line, and a positive voltage VWP or a negative voltage VWN is applied to all M write bit lines, and a zero voltage is applied to all M source lines; to complete a read operation for a particular word, a zero voltage is applied to the corresponding word line, a positive voltage VREAD is applied to all M read bit lines, and a zero voltage is applied to all M source lines.

FIG. 3 is a circuit diagram of a second hardware implementation of a single word line spin-orbit torque magnetic random access memory cell of the present invention. As shown in fig. 3, when it is desired to write a "1" (or a "0", depending on the magnetic field applied to the magnetoresistive element) to the memory cell, a zero voltage is applied to the word line, a positive voltage VWP is applied to the write bit line, and a zero voltage is applied to the source line; when it is desired to write a "0" (or a "1", depending on the magnetic field applied to the magnetoresistive element) to the memory cell, a zero voltage is applied to the word line, a negative voltage VWN is applied to the write bit line, and a zero voltage is applied to the source line; when data in the memory cell needs to be read, a positive voltage VDD is applied to the word line, a reading voltage VREAD is applied to the reading bit line, a zero voltage is applied to the source line, and the data in the target memory cell can be obtained by reading the current on the reading bit line or the source line.

FIG. 4 is a memory array of a second type of spin-orbit torque based magnetic random access memory cell. As shown in fig. 4, a row of the memory array has M memory cells, and the data stored in the M memory cells form a word; a column of the memory array has N memory cells. If the write operation for a specific word is to be completed, zero voltage is applied to the corresponding word line, and positive voltage VWP or negative voltage VWN is applied to all M write bit lines, and zero voltage is applied to all M source lines; to complete a read operation for a particular word, a positive voltage VDD is applied to the corresponding word line, a positive voltage VREAD is applied to all M read bit lines, and zero voltage is applied to all M source lines.