阅读说明：本技术 一种控制器共享同步方法和装置 (Controller sharing synchronization method and device ) 是由 江博 于 2020-10-29 设计创作，主要内容包括：本发明公开了一种控制器共享同步方法和装置,方法包括：由一个主控制器和多个从控制器的基板管理控制器分别将待传输数据各自加载到缓冲寄存器；由主控制器将待传输数据经由共享总线广播到多个从控制器,并分别接收由多个从控制器广播的待传输数据以写入缓冲寄存器；由主控制器的复杂可编程逻辑器件依次向每个从控制器经由共享总线分别发出数据同步请求；响应于有从控制器接收到数据同步请求,而由该从控制器将待传输数据广播到主控制器和多个其它从控制器,并分别接收由主控制器和多个其它从控制器广播的待传输数据以写入缓冲寄存器。本发明能够从数据共享和同步释放BMC资源,并且提高数据传输的响应速度。(The invention discloses a controller sharing synchronization method and a controller sharing synchronization device, wherein the method comprises the following steps: respectively loading data to be transmitted to a buffer register by a baseboard management controller of one master controller and a plurality of slave controllers; broadcasting data to be transmitted to a plurality of slave controllers by the master controller through a shared bus, and respectively receiving the data to be transmitted broadcasted by the slave controllers to write the data into a buffer register; the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus; in response to receiving a data synchronization request from a slave controller, the slave controller broadcasts data to be transmitted to the master controller and a plurality of other slave controllers, and receives the data to be transmitted broadcast by the master controller and the plurality of other slave controllers, respectively, to write into the buffer register. The invention can release BMC resources from data sharing and synchronization, and improve the response speed of data transmission.)

1. A controller sharing synchronization method is characterized by comprising the following steps of circularly executing:

loading data to be transmitted to respective buffer registers by the baseboard management controllers of a master controller and a plurality of slave controllers which are connected to a shared bus in parallel;

broadcasting, by the master controller, data to be transmitted to the plurality of slave controllers via the shared bus, and receiving, by the master controller, the data to be transmitted broadcast by the plurality of slave controllers via the shared bus, respectively, to write to buffer registers of the master controller;

the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through the shared bus;

in response to receiving the data synchronization request from a slave controller, broadcasting, by the slave controller, data to be transmitted to the master controller and a plurality of other slave controllers via the shared bus, and receiving, by the slave controller, the data to be transmitted broadcast by the master controller and the plurality of other slave controllers via the shared bus, respectively, to write to buffer registers of the slave controllers;

enabling one master controller and a plurality of slave controllers to respectively process the data obtained from the buffer registers of the master controllers so as to realize sharing and synchronization of the data.

2. The method of claim 1, wherein the sending, by the complex programmable logic device of the master controller, the data synchronization request to each of the slave controllers in turn comprises:

determining, by the master controller, request periods, and waiting at least one request period to issue the data synchronization request to a next one of the slave controllers after issuing the data synchronization request to one of the slave controllers.

3. The method according to claim 1, wherein each of the buffer registers is configured to have a plurality of storage columns, and the plurality of storage columns are in one-to-one correspondence with one master controller and a plurality of slave controllers;

the method for loading the data to be transmitted to the respective buffer registers by the baseboard management controllers of the master controller and the plurality of slave controllers which are connected to the shared bus in parallel comprises the following steps: and loading the data to be transmitted to the storage columns corresponding to the master controller or one of the slave controllers in the buffer registers respectively.

4. The method of claim 3, wherein receiving, by the master controller via the shared bus, data to be transmitted broadcast by the plurality of slave controllers, respectively, to write to buffer registers of the master controller comprises: respectively writing the data to be transmitted broadcasted by the plurality of slave controllers into the buffer registers of the master controller and the storage columns corresponding to the plurality of slave controllers respectively;

receiving, by the slave controller via the shared bus, respectively, data to be transmitted broadcast by the master controller and a plurality of other slave controllers to write to buffer registers of the slave controller comprises: and respectively writing the data to be transmitted broadcasted by the master controller and the other slave controllers into the buffer registers of the slave controllers, wherein the data to be transmitted respectively correspond to the storage columns of the master controller and the other slave controllers.

5. The method of claim 1, further comprising:

when the master controller broadcasts data to be transmitted to the plurality of slave controllers through the shared bus, calculating check data of the data to be transmitted, and broadcasting the check data to the plurality of slave controllers together with the data to be transmitted;

the master controller receives data to be transmitted broadcast by the slave controllers through the shared bus, receives check data of the data to be transmitted, checks the data to be transmitted based on the check data, and determines that the transmitted data is lost in response to a check failure;

when the slave controller broadcasts the data to be transmitted to the master controller and a plurality of other slave controllers through the shared bus, the slave controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the master controller and the plurality of other slave controllers together with the data to be transmitted;

the slave controller receives data to be transmitted broadcast by the master controller and a plurality of other slave controllers via the shared bus, respectively, and also receives check data of the data to be transmitted, checks the data to be transmitted based on the check data, and determines that the transmission data is lost in response to a check failure.

6. The method of claim 1, wherein the shared bus comprises a first bus and a second bus; transmitting via the shared bus comprises:

concurrently transmitting on the first bus and the second bus, and asserting transmission success in response to transmission data on the first bus and the second bus being the same, and asserting transmission failure in response to transmission data on the first bus and the second bus being different.

7. The method of claim 1, wherein the buffer registers of one of the master controller and the plurality of slave controllers are registers of the complex programmable logic devices of the one of the master controller and the plurality of slave controllers.

8. A controller-shared synchronization apparatus, comprising:

a processor; and

a memory storing processor executable program code that when executed and executed loops performing the steps of:

loading data to be transmitted to respective buffer registers by the baseboard management controllers of a master controller and a plurality of slave controllers which are connected to a shared bus in parallel;

broadcasting, by the master controller, data to be transmitted to the plurality of slave controllers via the shared bus, and receiving, by the master controller, the data to be transmitted broadcast by the plurality of slave controllers via the shared bus, respectively, to write to buffer registers of the master controller;

the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through the shared bus;

in response to receiving the data synchronization request from a slave controller, broadcasting, by the slave controller, data to be transmitted to the master controller and a plurality of other slave controllers via the shared bus, and receiving, by the slave controller, the data to be transmitted broadcast by the master controller and the plurality of other slave controllers via the shared bus, respectively, to write to buffer registers of the slave controllers;

enabling one master controller and a plurality of slave controllers to respectively process the data obtained from the buffer registers of the master controllers so as to realize sharing and synchronization of the data.

9. The apparatus according to claim 8, wherein each of the buffer registers is configured to have a plurality of storage columns, and the plurality of storage columns are in one-to-one correspondence with one of the master controllers and a plurality of the slave controllers;

the method for loading the data to be transmitted to the respective buffer registers by the baseboard management controllers of the master controller and the plurality of slave controllers which are connected to the shared bus in parallel comprises the following steps: loading the data to be transmitted to the storage columns corresponding to the master controller or one of the slave controllers in the buffer registers respectively;

receiving, by the master controller via the shared bus, respectively, data to be transmitted broadcast by a plurality of the slave controllers to write to buffer registers of the master controller comprises: respectively writing the data to be transmitted broadcasted by the plurality of slave controllers into the buffer registers of the master controller and the storage columns corresponding to the plurality of slave controllers respectively;

receiving, by the slave controller via the shared bus, respectively, data to be transmitted broadcast by the master controller and a plurality of other slave controllers to write to buffer registers of the slave controller comprises: and respectively writing the data to be transmitted broadcasted by the master controller and the other slave controllers into the buffer registers of the slave controllers, wherein the data to be transmitted respectively correspond to the storage columns of the master controller and the other slave controllers.

10. The apparatus of claim 8, wherein the steps further comprise:

when the master controller broadcasts data to be transmitted to the plurality of slave controllers through the shared bus, calculating check data of the data to be transmitted, and broadcasting the check data to the plurality of slave controllers together with the data to be transmitted;

the master controller receives data to be transmitted broadcast by the slave controllers through the shared bus, receives check data of the data to be transmitted, checks the data to be transmitted based on the check data, and determines that the transmitted data is lost in response to a check failure;

when the slave controller broadcasts the data to be transmitted to the master controller and a plurality of other slave controllers through the shared bus, the slave controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the master controller and the plurality of other slave controllers together with the data to be transmitted;

the slave controller receives data to be transmitted broadcast by the master controller and a plurality of other slave controllers via the shared bus, respectively, and also receives check data of the data to be transmitted, checks the data to be transmitted based on the check data, and determines that the transmission data is lost in response to a check failure.

Technical Field

The present invention relates to the field of storage control, and in particular, to a method and an apparatus for sharing and synchronizing controllers.

Background

The storage controller forms double-control, four-control, eight-control and even sixteen-control architecture setting ten years ago, and services are processed among multiple controls, so that the service performance is greatly improved. In addition, after one controller is crashed suddenly, the other controller takes over the service, so that the data safety and the disaster tolerance performance of the equipment are greatly improved. Each controller is managed by a BMC (baseboard management controller), so that the upper storage software is provided for reading and writing access, and the state information of relevant equipment in the controller and the shared information among multiple controllers are collected.

In the four-control scenario, the local control BMC needs to acquire the state information of the devices in the local controller in real time, and also needs to master the state information of the devices corresponding to other controllers in real time. Therefore, in a four-control or eight-control scenario, data synchronization, high reliability and quick and immediate response between the BMCs become more and more important, because much information is key information directly causing the establishment of the upper storage software cluster.

Data synchronization can be completely finished among a plurality of controllers BMC, but the first BMC adopts a simplified linux system, and the system inevitably has the problems of program runaway and the like; secondly, with the development of modern storage, more and more safety error prevention and functions are needed for BMC codes, the BMC is too bulky, equipment information is collected by adopting a polling mode, and the polling period is limited to the self-resource and code function quantity in the BMC, so that the response speed is low; thirdly, from the design level, the BMC handles management policies exclusively, and the state information collection work of the device results from the BMC processing involving unclear logic.

There is currently no effective solution to the problem in the prior art that BMCs are not suitable for performing data synchronization for controllers.

Disclosure of Invention

In view of this, an object of the embodiments of the present invention is to provide a method and an apparatus for controller sharing synchronization, which can release BMC resources from data sharing and synchronization, and improve response speed of data transmission.

In view of the foregoing, a first aspect of the embodiments of the present invention provides a controller sharing synchronization method, including performing the following steps in a loop:

loading data to be transmitted to respective buffer registers by the baseboard management controllers of a master controller and a plurality of slave controllers which are connected to a shared bus in parallel;

the method comprises the steps that data to be transmitted are broadcasted to a plurality of slave controllers through a shared bus by a master controller, and the data to be transmitted broadcasted by the slave controllers are respectively received by the master controller through the shared bus to be written into a buffer register of the master controller;

the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus;

in response to receiving a data synchronization request from a slave controller, broadcasting data to be transmitted to the master controller and a plurality of other slave controllers by the slave controller via a shared bus, and respectively receiving the data to be transmitted broadcast by the master controller and the plurality of other slave controllers by the slave controller via the shared bus to write the data to be transmitted into buffer registers of the slave controller;

the master controller and the slave controllers are enabled to process the data obtained from the buffer registers respectively so as to realize the sharing and synchronization of the data.

In some embodiments, the issuing, by the complex programmable logic device of the master controller, the data synchronization request to each of the slave controllers in turn comprises: the master determines the request periods and waits at least one request period before issuing a data synchronization request to the next slave after issuing a data synchronization request to one slave.

In some embodiments, each buffer register is configured to have a plurality of storage columns, and the plurality of storage columns correspond to one master controller and a plurality of slave controllers in a one-to-one manner;

the method for loading the data to be transmitted to the respective buffer registers by the baseboard management controllers of the master controller and the plurality of slave controllers which are connected to the shared bus in parallel comprises the following steps: and loading the data to be transmitted to a storage column corresponding to one master controller or one of a plurality of slave controllers in the buffer register respectively.

In some embodiments, receiving, by the master controller via the shared bus, respectively, data to be transmitted broadcast by the plurality of slave controllers to write to the buffer registers of the master controller comprises: respectively writing the data to be transmitted broadcasted by the plurality of slave controllers into the buffer registers of the master controller and the storage columns corresponding to the plurality of slave controllers;

receiving, by the slave controller via the shared bus, data to be transmitted broadcast by the master controller and a plurality of other slave controllers, respectively, to write to the buffer registers of the slave controller, includes: and respectively writing the data to be transmitted broadcasted by the master controller and the other slave controllers into the buffer registers of the slave controllers, wherein the data to be transmitted respectively correspond to the storage columns of the master controller and the other slave controllers.

In some embodiments, the method further comprises:

the method comprises the steps that when a master controller broadcasts data to be transmitted to a plurality of slave controllers through a shared bus, check data of the data to be transmitted are calculated, and the check data are broadcast to the slave controllers together with the data to be transmitted;

the method comprises the steps that when the master controller receives data to be transmitted broadcasted by the multiple slave controllers through a shared bus, the master controller also receives check data of the data to be transmitted, the data to be transmitted are checked based on the check data, and the loss of the transmission data is determined in response to the failure of the check;

when the slave controller broadcasts the data to be transmitted to the master controller and the plurality of other slave controllers through the shared bus, the slave controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the master controller and the plurality of other slave controllers together with the data to be transmitted;

the slave controller receives data to be transmitted broadcast by the master controller and the plurality of other slave controllers via the shared bus, respectively, and also receives check data of the data to be transmitted, checks the data to be transmitted based on the check data, and determines that the transmission data is lost in response to a failure in the checking.

In some embodiments, the shared bus comprises a first bus and a second bus; transmitting via the shared bus includes: the data is transmitted simultaneously on the first bus and the second bus, and the transmission is deemed successful in response to the data transmitted on the first bus and the second bus being the same, and the transmission is deemed failed in response to the data transmitted on the first bus and the second bus being different.

In some embodiments, the buffer registers of the master controller and the plurality of slave controllers are registers of the complex programmable logic device of the master controller and the plurality of slave controllers.

A second aspect of an embodiment of the present invention provides a controller-sharing synchronization apparatus, including:

a processor; and

a memory storing program code executable by the processor, the program code when executed looping through the steps of:

loading data to be transmitted to respective buffer registers by the baseboard management controllers of a master controller and a plurality of slave controllers which are connected to a shared bus in parallel;

the method comprises the steps that data to be transmitted are broadcasted to a plurality of slave controllers through a shared bus by a master controller, and the data to be transmitted broadcasted by the slave controllers are respectively received by the master controller through the shared bus to be written into a buffer register of the master controller;

the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus;

in response to receiving a data synchronization request from a slave controller, broadcasting data to be transmitted to the master controller and a plurality of other slave controllers by the slave controller via a shared bus, and respectively receiving the data to be transmitted broadcast by the master controller and the plurality of other slave controllers by the slave controller via the shared bus to write the data to be transmitted into buffer registers of the slave controller;

the master controller and the slave controllers are enabled to process the data obtained from the buffer registers respectively so as to realize the sharing and synchronization of the data.

In some embodiments, each buffer register is configured to have a plurality of storage columns, and the plurality of storage columns correspond to one master controller and a plurality of slave controllers in a one-to-one manner;

the method for loading the data to be transmitted to the respective buffer registers by the baseboard management controllers of the master controller and the plurality of slave controllers which are connected to the shared bus in parallel comprises the following steps: loading data to be transmitted to a storage column corresponding to one master controller or one of a plurality of slave controllers in a buffer register respectively;

receiving, by the master controller via the shared bus, data to be transmitted broadcast by the plurality of slave controllers, respectively, to write to the buffer register of the master controller, includes: respectively writing the data to be transmitted broadcasted by the plurality of slave controllers into the buffer registers of the master controller and the storage columns corresponding to the plurality of slave controllers;

receiving, by the slave controller via the shared bus, data to be transmitted broadcast by the master controller and a plurality of other slave controllers, respectively, to write to the buffer registers of the slave controller, includes: and respectively writing the data to be transmitted broadcasted by the master controller and the other slave controllers into the buffer registers of the slave controllers, wherein the data to be transmitted respectively correspond to the storage columns of the master controller and the other slave controllers.

In some embodiments, the steps further comprise:

the method comprises the steps that when a master controller broadcasts data to be transmitted to a plurality of slave controllers through a shared bus, check data of the data to be transmitted are calculated, and the check data are broadcast to the slave controllers together with the data to be transmitted;

the method comprises the steps that when the master controller receives data to be transmitted broadcasted by the multiple slave controllers through a shared bus, the master controller also receives check data of the data to be transmitted, the data to be transmitted are checked based on the check data, and the loss of the transmission data is determined in response to the failure of the check;

when the slave controller broadcasts the data to be transmitted to the master controller and the plurality of other slave controllers through the shared bus, the slave controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the master controller and the plurality of other slave controllers together with the data to be transmitted;

the slave controller receives data to be transmitted broadcast by the master controller and the plurality of other slave controllers via the shared bus, respectively, and also receives check data of the data to be transmitted, checks the data to be transmitted based on the check data, and determines that the transmission data is lost in response to a failure in the checking.

The invention has the following beneficial technical effects: according to the controller sharing synchronization method and device provided by the embodiment of the invention, the data to be transmitted are loaded to respective buffer registers by the baseboard management controllers of the master controller and the plurality of slave controllers which are connected to the shared bus in parallel; the method comprises the steps that data to be transmitted are broadcasted to a plurality of slave controllers through a shared bus by a master controller, and the data to be transmitted broadcasted by the slave controllers are respectively received by the master controller through the shared bus to be written into a buffer register of the master controller; the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus; in response to receiving a data synchronization request from a slave controller, broadcasting data to be transmitted to the master controller and a plurality of other slave controllers by the slave controller via a shared bus, and respectively receiving the data to be transmitted broadcast by the master controller and the plurality of other slave controllers by the slave controller via the shared bus to write the data to be transmitted into a buffer register of the controller; the technical scheme that the master controller and the slave controllers respectively process the data obtained from the buffer registers of the master controller and the slave controllers to realize data sharing and synchronization can release BMC resources from data sharing and synchronization and improve the response speed of data transmission.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a flow chart illustrating a method for sharing synchronization among controllers according to the present invention;

FIG. 2 is a detailed flowchart of a controller sharing synchronization method according to the present invention;

FIG. 3 is a logic state diagram of a controller according to the present invention;

FIG. 4 is a schematic diagram of a shared bus according to the method for sharing synchronization among controllers of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.

In view of the above, a first aspect of the embodiments of the present invention provides an embodiment of a controller sharing synchronization method for releasing BMC resources from data sharing and synchronization and improving response speed of data transmission. Fig. 1 is a schematic flow chart of a controller sharing synchronization method provided by the present invention.

The controller sharing synchronization method, as shown in fig. 1, includes connecting a master controller and a plurality of slave controllers in parallel to a shared bus, and cyclically executing the following steps to share and synchronize data between the master controller and the plurality of slave controllers via the shared bus:

step S101, respectively loading data to be transmitted of one master controller and a plurality of slave controllers to buffer registers of the master controller and the plurality of slave controllers by the baseboard management controllers of the master controller and the plurality of slave controllers;

step S103, the master controller broadcasts the data to be transmitted of the master controller to the plurality of slave controllers through the shared bus, and the master controller receives the data to be transmitted broadcasted by the plurality of slave controllers from the plurality of slave controllers through the shared bus respectively so as to write the data to be transmitted into a buffer register of the master controller;

step S105, the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through the shared bus;

step S107, in response to a slave controller receiving a data synchronization request, the controller broadcasts the data to be transmitted of the controller to the master controller and a plurality of other slave controllers via a shared bus, and the controller receives the data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers via the shared bus respectively to write the data to the buffer registers of the controller;

step S109, enabling the master controller and the slave controllers to process the data obtained from their respective buffer registers respectively to implement data sharing and synchronization.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like. Embodiments of the computer program may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.

In some embodiments, the issuing, by the complex programmable logic device of the master controller, the data synchronization request to each of the slave controllers in turn comprises: the master determines the request periods and waits at least one request period before issuing a data synchronization request to the next slave after issuing a data synchronization request to one slave.

In some embodiments, each buffer register is configured to have a plurality of storage columns, and the plurality of storage columns correspond to one master controller and a plurality of slave controllers in a one-to-one manner;

the method for loading the data to be transmitted of the master controller and the plurality of slave controllers to the buffer registers of the master controller and the plurality of slave controllers respectively comprises the following steps: and loading the data to be transmitted to a storage column corresponding to one master controller or one of a plurality of slave controllers in the buffer register respectively.

In some embodiments, receiving data to be transmitted broadcast by the plurality of slave controllers from the plurality of slave controllers, respectively, to write to the buffer register of the master controller includes: respectively writing the data to be transmitted broadcasted by the plurality of slave controllers into the buffer registers of the master controller and the storage columns corresponding to the plurality of slave controllers;

receiving data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers, respectively, to write to the buffer registers of the controllers includes: and respectively writing the data to be transmitted broadcasted by the master controller and the other slave controllers into the storage columns, corresponding to the master controller and the other slave controllers, in the buffer register of the controller.

In some embodiments, when the master controller broadcasts the data to be transmitted of the master controller to the plurality of slave controllers, the master controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the plurality of slave controllers along with the data to be transmitted; the method comprises the steps that when the master controller receives data to be transmitted broadcasted by the slave controllers from the slave controllers respectively, the master controller also receives check data of the data to be transmitted, the data to be transmitted are checked based on the check data, and the loss of the transmission data is determined in response to the failure of the check;

when the controller broadcasts the data to be transmitted of the controller to the main controller and the plurality of other slave controllers, the controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the main controller and the plurality of other slave controllers together with the data to be transmitted; the controller receives data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers, respectively, and also receives verification data of the data to be transmitted, verifies the data to be transmitted based on the verification data, and determines that the transmission data is lost in response to a verification failure.

In some embodiments, the shared bus comprises a first bus and a second bus; transmitting via the shared bus includes: the data is transmitted simultaneously on the first bus and the second bus, and the transmission is deemed successful in response to the data transmitted on the first bus and the second bus being the same, and the transmission is deemed failed in response to the data transmitted on the first bus and the second bus being different.

In some embodiments, the buffer registers of the master controller and the plurality of slave controllers are registers of the complex programmable logic device of the master controller and the plurality of slave controllers.

The following further illustrates embodiments of the invention in terms of specific examples.

Firstly, the device identification is confirmed or the BMC, the upper layer software and other modes are used for determining which device is the host. The order in which data sharing and synchronization is performed with reference to fig. 2 after determining the hosts. In fig. 2 there is one per CPLD (BMC read buffer). In columns. The black columns represent the present node information. According to the BMC requirement, 8 pieces of status information are required to be provided, one piece of status information is one bit (for example, master-slave status, in-place status, BMC monitoring status). One block represents the CRC check of its corresponding column, also for BMC read.

As shown in FIG. 2, first, the host sends a command for synchronizing data, broadcasting the value of abcdefgh at the moment of the local node; and simultaneously, the local node updates the BMC to read the abcdefgh value of the node column corresponding to the buffer area, and simultaneously starts a 1ms timer. And after receiving the broadcast, other CPLDs carry out CRC check. And when the check fails, setting CRC bits corresponding to the node columns to be 1 according to the sending equipment address in the frame. And when the check is correct, setting the CRC bit corresponding to the node column to be 0 according to the 'sending equipment address' in the frame, and updating the abcdefgh value of the column corresponding to the BMC reading buffer area.

After the host 1ms timer expires, the host sends a synchronization request with id 1 (if id is consistent with the host id, the host skips), and simultaneously starts the 1ms timer. Then, the slave machine with id being 1 sends a synchronous data command, and broadcasts the value abcdefgh of the local node at the moment; meanwhile, the local node updates the BMC to read the value of the corresponding node column abcdefgh of the buffer area. And after receiving the broadcast, other CPLDs carry out CRC check. And when the check fails, setting CRC bits corresponding to the node columns to be 1 according to the sending equipment address in the frame. And when the check is correct, setting the CRC bit corresponding to the node column to be 0 according to the 'sending equipment address' in the frame, and updating the abcdefgh value of the column corresponding to the BMC reading buffer area.

After the 1ms timer of the host is full, the host sends a synchronization request to the id 2 (if the id is consistent with the id of the host, the host skips), and simultaneously starts the 1ms timer. Then, the slave machine with id being 2 sends a synchronous data command, and broadcasts the value abcdefgh of the local node at the moment; meanwhile, the local node updates the BMC to read the value of the corresponding node column abcdefgh of the buffer area. And after receiving the broadcast, other CPLDs carry out CRC check. And when the check fails, setting CRC bits corresponding to the node columns to be 1 according to the sending equipment address in the frame. And when the check is correct, setting the CRC bit corresponding to the node column to be 0 according to the 'sending equipment address' in the frame, and updating the abcdefgh value of the column corresponding to the BMC reading buffer area.

After the 1ms timer of the host is full, the host sends a synchronization request to the id 3 (if the id is consistent with the id of the host, the host skips), and simultaneously starts the 1ms timer. The slave machine with id being 3 sends a synchronous data command, and broadcasts the value abcdefgh at the moment of the local node; meanwhile, the local node updates the BMC to read the value of the corresponding node column abcdefgh of the buffer area. And after receiving the broadcast, other CPLDs carry out CRC check. And when the check fails, setting CRC bits corresponding to the node columns to be 1 according to the sending equipment address in the frame. And when the check is correct, setting the CRC bit corresponding to the node column to be 0 according to the 'sending equipment address' in the frame, and updating the abcdefgh value of the column corresponding to the BMC reading buffer area.

This approach ensures that all data is consistent when four or eight BMCs read their CPLD (complex logic programmable device) registers. This results in a high reliability of the method. Data synchronization is achieved entirely by the CPLD, and each refresh data cycle can be set at a fixed 4ms +80us by virtue of the real-time operating characteristics of the CPLD logic.

The CPLD logic state machine is shown in detail in FIG. 3. In fig. 3:

1 represents the completion of power-on reset;

2, the Device ID acquisition fails or is illegal, or the data of the two buses are inconsistent;

8 indicates that the Device ID acquisition is successful and legal but the match-enable bit is 0;

4 indicates that no clock and data change occurs in both buses within (200ms + Device ID 10 ms);

6, after the master command is sent out (Device ID x 1ms), no clock and data change exists in the two buses;

7, data change (clock or data) occurs in at least one of the two buses after the master command is sent out (Device ID x 1 ms);

9 indicates 1ms timed-out;

11, the synchronous data in self data boardcoast is sent completely;

10. 12, 14, 17 indicate that master-slave manual setting command of the upper layer BMC is received, or the BMC hangs up (default BMC is normal within 3 minutes of power-on) or multiple masters appear for 3 consecutive periods. Or the data of the use bus is inconsistent with the data of the backup bus;

13 indicates that the 1ms timer is full and not all slave nodes have been traversed. (the goal is to cycle through all slave nodes);

16 indicates that the 1ms timer is full and all slave nodes have been traversed;

17 denotes receipt of a "synchronization request" from the host;

18 indicates the "synchronize data" command is complete;

21 indicates that there is no clock and data change on both buses for 200 ms.

In the embodiment of the invention, four or eight controllers are mounted on the shared bus. Each device may be a master or a slave. Therefore, the physical connection mode can be arbitrarily expanded to eight controls and sixteen controls. There are multiple devices on the bus. Only one master can exist at a time. The communication protocol between CPLDs needs to be customized. To increase the reliability of the data, one more bus is backed up, as shown in fig. 4. Each time a master device sends a command or data, it needs to be done on both buses simultaneously. The receiving device can carry out subsequent operations only after detecting the same data on the data of the two buses, otherwise discarding and reporting an error.

In addition, in order to increase the reliability of data, the embodiment of the invention adds a CRC check of 8 bits at the tail of each sending period or receiving period, and when the check fails, the data frame is lost and an error is reported.

It can be seen from the foregoing embodiments that, in the controller sharing synchronization method provided in the embodiments of the present invention, the baseboard management controllers of the master controller and the slave controllers respectively load the data to be transmitted of the master controller and the slave controllers to the buffer registers of the master controller and the slave controllers; broadcasting data to be transmitted of the master controller to the plurality of slave controllers by the master controller through the shared bus, and respectively receiving the data to be transmitted broadcasted by the plurality of slave controllers from the plurality of slave controllers through the shared bus by the master controller so as to write the data to be transmitted into a buffer register of the master controller; the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus; in response to one slave controller receiving a data synchronization request, broadcasting data to be transmitted of the controller to the master controller and a plurality of other slave controllers by the controller via a shared bus, and respectively receiving the data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers via the shared bus by the controller to write the data to be transmitted into a buffer register of the controller; the technical scheme that the master controller and the slave controllers respectively process the data obtained from the buffer registers of the master controller and the slave controllers to realize data sharing and synchronization can release BMC resources from data sharing and synchronization and improve the response speed of data transmission.

It should be particularly noted that, the steps in the embodiments of the controller-sharing synchronization method described above can be mutually intersected, replaced, added, or deleted, and therefore, these reasonable permutations and combinations should also fall within the scope of the present invention, and should not limit the scope of the present invention to the described embodiments.

In view of the above object, according to a second aspect of the embodiments of the present invention, an embodiment of a controller-shared synchronization apparatus is provided, which releases BMC resources from data sharing and synchronization, and improves response speed of data transmission. The controller-sharing synchronization device includes:

a shared bus on which a master controller and a plurality of slave controllers are mounted;

a processor; and

a memory storing processor executable program code that when executed and executed cyclically performs the following steps to share and synchronize data between a master controller and a plurality of slave controllers via a shared bus:

respectively loading data to be transmitted of one master controller and a plurality of slave controllers to buffer registers of the master controller and the slave controllers by baseboard management controllers of the master controller and the slave controllers;

broadcasting data to be transmitted of the master controller to the plurality of slave controllers by the master controller through the shared bus, and respectively receiving the data to be transmitted broadcasted by the plurality of slave controllers from the plurality of slave controllers through the shared bus by the master controller so as to write the data to be transmitted into a buffer register of the master controller;

the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus;

in response to one slave controller receiving a data synchronization request, broadcasting data to be transmitted of the controller to the master controller and a plurality of other slave controllers by the controller via a shared bus, and respectively receiving the data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers via the shared bus by the controller to write the data to be transmitted into a buffer register of the controller;

the master controller and the slave controllers are enabled to process the data obtained from the buffer registers respectively so as to realize the sharing and synchronization of the data.

In some embodiments, each buffer register is configured to have a plurality of storage columns, and the plurality of storage columns correspond to one master controller and a plurality of slave controllers in a one-to-one manner;

the method for loading the data to be transmitted of the master controller and the plurality of slave controllers to the buffer registers of the master controller and the plurality of slave controllers respectively comprises the following steps: loading data to be transmitted to a storage column corresponding to one master controller or one of a plurality of slave controllers in a buffer register respectively;

the receiving data to be transmitted broadcast by the plurality of slave controllers from the plurality of slave controllers, respectively, to be written to the buffer register of the master controller includes: respectively writing the data to be transmitted broadcasted by the plurality of slave controllers into the buffer registers of the master controller and the storage columns corresponding to the plurality of slave controllers;

receiving data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers, respectively, to write to the buffer registers of the controllers includes: and respectively writing the data to be transmitted broadcasted by the master controller and the other slave controllers into the storage columns, corresponding to the master controller and the other slave controllers, in the buffer register of the controller.

In some embodiments, when the master controller broadcasts the data to be transmitted of the master controller to the plurality of slave controllers, the master controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the plurality of slave controllers along with the data to be transmitted; the method comprises the steps that when the master controller receives data to be transmitted broadcasted by the slave controllers from the slave controllers respectively, the master controller also receives check data of the data to be transmitted, the data to be transmitted are checked based on the check data, and the loss of the transmission data is determined in response to the failure of the check;

when the controller broadcasts the data to be transmitted of the controller to the main controller and the plurality of other slave controllers, the controller also calculates the check data of the data to be transmitted, and broadcasts the check data to the main controller and the plurality of other slave controllers together with the data to be transmitted; the controller receives data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers, respectively, and also receives verification data of the data to be transmitted, verifies the data to be transmitted based on the verification data, and determines that the transmission data is lost in response to a verification failure.

As can be seen from the foregoing embodiments, in the controller sharing synchronization apparatus provided in the embodiments of the present invention, the baseboard management controllers of the master controller and the slave controllers respectively load the data to be transmitted of the master controller and the slave controllers to the buffer registers of the master controller and the slave controllers; broadcasting data to be transmitted of the master controller to the plurality of slave controllers by the master controller through the shared bus, and respectively receiving the data to be transmitted broadcasted by the plurality of slave controllers from the plurality of slave controllers through the shared bus by the master controller so as to write the data to be transmitted into a buffer register of the master controller; the complex programmable logic device of the master controller sequentially sends data synchronization requests to each slave controller through a shared bus; in response to one slave controller receiving a data synchronization request, broadcasting data to be transmitted of the controller to the master controller and a plurality of other slave controllers by the controller via a shared bus, and respectively receiving the data to be transmitted broadcast by the master controller and the plurality of other slave controllers from the master controller and the plurality of other slave controllers via the shared bus by the controller to write the data to be transmitted into a buffer register of the controller; the technical scheme that the master controller and the slave controllers respectively process the data obtained from the buffer registers of the master controller and the slave controllers to realize data sharing and synchronization can release BMC resources from data sharing and synchronization and improve the response speed of data transmission.

It should be particularly noted that the above embodiment of the controller-shared synchronization apparatus employs the embodiment of the controller-shared synchronization method to specifically describe the working process of each module, and those skilled in the art can easily think that these modules are applied to other embodiments of the controller-shared synchronization method. Of course, since the steps in the embodiment of the controller-sharing synchronization method can be mutually intersected, replaced, added, or deleted, these reasonable permutations and combinations should also fall within the scope of the present invention, and should not limit the scope of the present invention to the embodiment.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.