Euse controller, chip and efuse read-write system
阅读说明：本技术 efuse控制器、芯片及efuse读写系统 (Euse controller, chip and efuse read-write system ) 是由 叶崇光 李林 周杰雷 陈西昌 于 2020-12-02 设计创作，主要内容包括：本发明提供了一种efuse控制器、芯片及efuse读写系统,efuse控制器的efuse控制模块包括脉冲间隔控制单元、脉冲宽度控制单元和脉冲输出控制单元；脉冲间隔控制单元的输入端被配置为接收预设间隔时长,脉冲间隔控制单元被配置为根据预设间隔时长控制脉冲输出控制单元输出的控制脉冲的脉冲间隔；脉冲宽度控制单元的输入端被配置为接收预设脉冲宽度,脉冲宽度控制单元被配置为根据预设脉冲宽度控制脉冲输出控制单元输出的控制脉冲的脉冲宽度；脉冲输出控制单元的输出端连接efuse模块,并被配置为将控制脉冲输出至efuse模块。本发明提供的efuse控制器、芯片及efuse读写系统,使得efuse模块能够在宽频率范围内实现读写,从而提高读写efuse模块的便利性。(The invention provides an efuse controller, a chip and an efuse read-write system.A efuse control module of the efuse controller comprises a pulse interval control unit, a pulse width control unit and a pulse output control unit; the input end of the pulse interval control unit is configured to receive a preset interval duration, and the pulse interval control unit is configured to control the pulse interval of the control pulse output by the pulse output control unit according to the preset interval duration; the input end of the pulse width control unit is configured to receive a preset pulse width, and the pulse width control unit is configured to control the pulse width of the control pulse output by the pulse output control unit according to the preset pulse width; the output end of the pulse output control unit is connected with the efuse module and is configured to output a control pulse to the efuse module. The efuse controller, the chip and the efuse read-write system provided by the invention enable the efuse module to realize read-write in a wide frequency range, thereby improving the convenience of reading and writing the efuse module.)
1. An efuse controller is characterized by comprising an efuse control module, wherein the efuse control module comprises a pulse interval control unit, a pulse width control unit and a pulse output control unit;
the input end of the pulse interval control unit is configured to receive a preset interval duration, the output end of the pulse interval control unit is connected with one input end of the pulse output control unit, and the pulse interval control unit is configured to control the pulse interval of the control pulse output by the pulse output control unit according to the preset interval duration;
the input end of the pulse width control unit is configured to receive a preset pulse width, the output end of the pulse width control unit is connected with the other input end of the pulse output control unit, and the pulse width control unit is configured to control the pulse width of the control pulse output by the pulse output control unit according to the preset pulse width;
the output end of the pulse output control unit is connected with the efuse module and is configured to output the control pulse to the efuse module.
2. The efuse controller according to claim 1, wherein the pulse interval control unit and/or the pulse width control unit includes a sequential logic circuit;
the sequential logic circuit comprises a first comparator, a counter, a first selector and a second comparator;
one of the inputs of the first comparator is configured to receive a preset counting parameter;
the other input end of the first comparator is connected with one input end of the counter, the output end of the first selector and one input end of the second comparator
The output end of the first comparator is connected with the selection end of the first selector;
the output end of the counter is connected with one input end of the first selector;
the other input end of the first selector is connected with 0;
the other input end of the second comparator is configured to receive the preset counting parameter, and the output end of the second comparator is connected with the pulse output control unit;
the preset counting parameter received by the pulse interval control unit comprises the preset interval duration, and the preset counting parameter received by the pulse width control unit comprises the pulse width.
3. The efuse controller of claim 2, wherein the sequential logic circuit further comprises a second selector;
the other input end of the second selector is connected with 0, and the selection end of the second selector is configured to receive a chip selection signal;
the other input terminal of the first comparator is connected to one of the input terminals of the counter, the output terminal of the first selector, and one of the input terminals of the second comparator, and includes:
the output end of the first selector is connected with one input end of the second selector, and the other input end of the first comparator is connected with one input end of the counter, the output end of the second selector and one input end of the second comparator;
when the chip select signal is to enable the efuse module, the efuse controller is configured to generate the control pulse.
4. The efuse controller of claim 3, wherein the sequential logic circuit further comprises a first register;
the first register is configured to receive a reset signal and a clock signal;
the other input terminal of the first comparator is connected to one of the input terminals of the counter, the output terminal of the second selector, and one of the input terminals of the second comparator, and includes:
the output end of the second selector is connected with the input end of the first register, and the other input end of the first comparator is connected with one of the input ends of the counter, the output end of the first register and one of the input ends of the second comparator;
the efuse controller is configured to reset its internal count to 0 according to the reset signal.
5. The efuse controller according to claim 1, wherein the pulse output control unit includes a third selector and a fourth selector;
the other input end of the third selector is connected with 0, and the selection end of the third selector is connected with the output end of the pulse width control unit;
one input end of the fourth selector is connected with the output end of the third selector, the other input end of the fourth selector is connected with 0, and the selection end of the fourth selector is connected with the output end of the pulse interval control unit;
the output end of the fourth selector is connected with one input end of the third selector;
the output end of the pulse output control unit is connected with the efuse module, and the output end of the fourth selector is connected with the efuse module.
6. The efuse controller according to claim 5, wherein the pulse output control unit further comprises a second register;
the second register is configured to receive a reset signal and a clock signal;
the output end of the fourth selector is connected with one input end of the third selector, and the output end of the fourth selector is connected with the input end of the second register, and the output end of the second register is connected with one input end of the third selector;
the output end of the fourth selector is connected with the efuse module, and the output end of the second register is connected with the efuse module.
7. The efuse controller according to claim 1, further comprising an efuse socket module, wherein one input end of the efuse socket module is connected to an output end of the efuse control module, and the other input end of the efuse socket module is connected to a machine;
the efuse socket module is configured to: and reading and writing the efuse module through the efuse control module or the console according to the bypass mode enabling state.
8. The efuse controller of claim 7 wherein the efuse socket module includes a fifth selector;
one input end of the fifth selector is connected with the output end of the efuse control module, the other input end of the fifth selector is connected with the machine, the output end of the fifth selector is connected with the efuse module, and the selection end of the fifth selector is configured to receive the bypass mode enabling state;
the method for reading and writing the efuse module through the efuse control module or the machine station according to the bypass mode enabling state comprises the following steps:
if the bypass mode enabling state is the bypass mode, performing read-write operation on the efuse module through the machine; otherwise, performing read-write operation on the efuse module through the efuse control module.
9. A chip, comprising the efuse controller and the efuse module as claimed in any one of claims 1 to 8, wherein the efuse controller is connected to the efuse module, and the efuse module is read and written by the efuse controller.
10. An efuse read-write system, characterized in that the efuse read-write system comprises the efuse controller of any one of claims 1 to 8 and/or the chip of claim 9.
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to an efuse controller, a chip and an efuse read-write system.
Background
An efuse (electrically Programmable fuse) module is a One Time Programmable (OTP) memory, and it implements a function of writing data on a chip by blowing a fuse. The efuse module is a non-volatile memory in which data cannot be modified once written. Therefore, it is widely used in chip manufacturing as an IP (Intellectual Property) provided by a chip manufacturer for storing specific data information. For example, the repair information is usually used to store some internal ram (random access memory) of the chip, so as to improve the yield of the chip; or store some very important and sensitive information, such as keys, MAC addresses, and some other specific setting information.
In the prior art, most efuse modules can only read and write data under a fixed frequency time sequence, the applications of chips with the efuse modules are often different, and in most cases, the clock frequency of the chip with the efuse modules is not consistent with the read-write frequency of the efuse modules. Therefore, when writing data into or reading data from the efuse module, the read/write time sequence is often controlled to be the fixed frequency time sequence of the efuse module through equipment such as a machine station, and this way is time-consuming, labor-consuming and inefficient, namely: the existing efuse module cannot meet the requirement of working in a larger frequency range.
Therefore, how to provide an efuse controller to enable an efuse module to read and write data in a wide frequency range is becoming one of the technical problems to be solved by those skilled in the art. In the prior art, no similar technical scheme is found.
It is noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide an efuse controller, a chip and an efuse read-write system aiming at the defects in the prior art, so that the efuse module can realize read-write in a wide frequency range, and the convenience of reading and writing the efuse module is improved.
In order to achieve the purpose, the invention is realized by the following technical scheme: an efuse controller comprises an efuse control module, wherein the efuse control module comprises a pulse interval control unit, a pulse width control unit and a pulse output control unit;
the input end of the pulse interval control unit is configured to receive a preset interval duration, the output end of the pulse interval control unit is connected with one input end of the pulse output control unit, and the pulse interval control unit is configured to control the pulse interval of the control pulse output by the pulse output control unit according to the preset interval duration;
the input end of the pulse width control unit is configured to receive a preset pulse width, the output end of the pulse width control unit is connected with the other input end of the pulse output control unit, and the pulse width control unit is configured to control the pulse width of the control pulse output by the pulse output control unit according to the preset pulse width;
the output end of the pulse output control unit is connected with the efuse module and is configured to output the control pulse to the efuse module.
Optionally, the pulse interval control unit and/or the pulse width control unit comprise sequential logic circuits;
the sequential logic circuit comprises a first comparator, a counter, a first selector and a second comparator;
one of the inputs of the first comparator is configured to receive a preset counting parameter;
the other input end of the first comparator is connected with one input end of the counter, the output end of the first selector and one input end of the second comparator;
the output end of the first comparator is connected with the selection end of the first selector;
the output end of the counter is connected with one input end of the first selector;
the other input end of the first selector is connected with 0;
the other input end of the second comparator is configured to receive the preset counting parameter, and the output end of the second comparator is connected with the pulse output control unit;
the preset counting parameter received by the pulse interval control unit comprises the preset interval duration, and the preset counting parameter received by the pulse width control unit comprises the pulse width.
Optionally, the sequential logic circuit further comprises a second selector;
the other input end of the second selector is connected with 0, and the selection end of the second selector is configured to receive a chip selection signal;
the other input terminal of the first comparator is connected to one of the input terminals of the counter, the output terminal of the first selector, and one of the input terminals of the second comparator, and includes:
the output end of the first selector is connected with one input end of the second selector, and the other input end of the first comparator is connected with one input end of the counter, the output end of the second selector and one input end of the second comparator;
when the chip select signal is to enable the efuse module, the efuse controller is configured to generate the control pulse.
Optionally, the sequential logic circuit further comprises a first register;
the first register is configured to receive a reset signal and a clock signal;
the other input terminal of the first comparator is connected to one of the input terminals of the counter, the output terminal of the second selector, and one of the input terminals of the second comparator, and includes:
the output end of the second selector is connected with the input end of the first register, and the other input end of the first comparator is connected with one of the input ends of the counter, the output end of the first register and one of the input ends of the second comparator;
the efuse controller is configured to reset its internal count to 0 according to the reset signal.
Optionally, the pulse output control unit comprises a third selector and a fourth selector;
the other input end of the third selector is connected with 0, and the selection end of the third selector is connected with the output end of the pulse width control unit;
one input end of the fourth selector is connected with the output end of the third selector, the other input end of the fourth selector is connected with 0, and the selection end of the fourth selector is connected with the output end of the pulse interval control unit;
the output end of the fourth selector is connected with one input end of the third selector;
the output end of the pulse output control unit is connected with the efuse module, and the output end of the fourth selector is connected with the efuse module.
Optionally, the pulse output control unit further includes a second register;
the second register is configured to receive a reset signal and a clock signal;
the output end of the fourth selector is connected with one input end of the third selector, and the output end of the fourth selector is connected with the input end of the second register, and the output end of the second register is connected with one input end of the third selector;
the output end of the fourth selector is connected with the efuse module, and the output end of the second register is connected with the efuse module.
Optionally, the efuse controller further includes an efuse socket module, one input end of the efuse socket module is connected to the output end of the efuse control module, and the other input end of the efuse socket module is connected to the machine;
the efuse socket module is configured to: and reading and writing the efuse module through the efuse control module or the console according to the bypass mode enabling state.
Optionally, the efuse socket module includes a fifth selector;
one input end of the fifth selector is connected with the output end of the efuse control module, the other input end of the fifth selector is connected with the machine, the output end of the fifth selector is connected with the efuse module, and the selection end of the fifth selector is configured to receive the bypass mode enabling state;
the method for reading and writing the efuse module through the efuse control module or the machine station according to the bypass mode enabling state comprises the following steps:
if the bypass mode enabling state is the bypass mode, performing read-write operation on the efuse module through the machine; otherwise, performing read-write operation on the efuse module through the efuse control module.
Based on the same inventive concept, the invention further provides a chip, wherein the chip comprises the efuse controller and the efuse module, the efuse controller is connected with the efuse module, and the efuse module is read and written through the efuse controller.
Based on the same inventive concept, the invention also provides an efuse read-write system, which comprises the efuse controller and/or the chip.
Compared with the prior art, the efuse controller provided by the invention has the following beneficial effects:
1. the invention provides an efuse controller which comprises an efuse control module, wherein the efuse control module comprises a pulse interval control unit, a pulse width control unit and a pulse output control unit; the input end of the pulse interval control unit is configured to receive a preset interval duration, and the pulse interval control unit is configured to control the pulse interval of the control pulse output by the pulse output control unit according to the preset interval duration; the input end of the pulse width control unit is configured to receive a preset pulse width, and the pulse width control unit is configured to control the pulse width of the control pulse output by the pulse output control unit according to the preset pulse width; the output end of the pulse output control unit is connected with the efuse module and is configured to output the control pulse to the efuse module. With the configuration, the pulse interval control unit and the pulse width control unit of the efuse control module provided by the invention can flexibly construct control pulses with configurable pulse widths and intervals according to the preset interval duration and the preset pulse width, so that the control pulses can be well adapted to the time sequence frequency of a reading device, the efuse module can realize reading and writing in a wide frequency range, manpower and material resources are saved, and the convenience for reading and writing the efuse module is greatly improved.
2. According to the efuse controller provided by the invention, the pulse interval control unit and/or the pulse width control unit are/is a sequential logic circuit, the sequential logic circuit only comprises a comparator, a counter and a selector, the price of an electric element is low, and the logic structure of the circuit is simple. The configuration has low cost, small influence on the layout design of the existing chip and easy wiring implementation.
3. According to the efuse controller provided by the invention, the second selector can control whether the efuse controller generates a control pulse according to whether a chip selection signal is in an enabling state, and the efuse controller can be in a working state only when read-write operation needs to be carried out on the efuse module by the configuration, so that the convenience and operability of the efuse controller are improved.
4. In the efuse controller provided by the invention, the first timing logic circuit of the pulse interval control unit comprises a first register, preferably, the first register can be a shift register, and the first register can receive a reset signal and a clock signal. Similarly, the second sequential logic circuit 112b of the pulse width control unit provided in this embodiment has the same structure as the first sequential logic circuit of the pulse interval control unit, and thus has at least the same advantageous effects.
5. The efuse controller provided by the present invention further includes an efuse socket module, where the efuse socket module is configured to: according to the bypass mode enabling state, the efuse control module or the machine table is right, the efuse module is read and written, and the machine table can generate clocks and signals with custom frequency, so that different efuses can be read and written through the machine table, and the fault-tolerant capability of the chip can be effectively improved.
Those skilled in the art should understand that the chip with the efuse controller and the efuse read-write system provided by the present invention have the same inventive concept, and therefore, at least the same beneficial effects are achieved, and the details are not repeated herein.
Drawings
Fig. 1 is a schematic structural diagram of an efuse controller according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of the efuse control module in FIG. 1;
FIG. 3 is a schematic structural diagram of the efuse socket module in FIG. 1;
FIG. 4 is a schematic structural diagram of an efuse read/write system according to an embodiment of the present invention;
wherein the reference numerals are as follows:
the system comprises a 100-effect controller, a 110-effect control module, a 120-effect socket module, a 200-machine station and a 300-effect module;
111-pulse interval control unit, 112-pulse width control unit, 113-pulse output control unit;
111 a-first sequential logic circuit, 112 b-second sequential logic circuit;
a 11-a first comparator, a 12-a second comparator, a2, b 2-a counter, a 31-a first selector, a 32-a second selector, a 33-a third selector, a 34-a fourth selector, a 35-a fifth selector, a 41-a first register, and a 42-a second register;
pulse _ itvl-preset interval duration, pulse _ width-preset pulse width, csb-chip select signal, strobe-control pulse, rst _ n-reset signal, clk-clock signal.
Detailed Description
The core idea of the invention is to provide an efuse controller, a chip and an efuse read-write system, which overcome the defect that an efuse module can only read and write under a fixed frequency time sequence, so that the efuse module can read and write data in a wide frequency range.
In order to realize the idea, the invention provides an efuse controller, which comprises an efuse control module, wherein the efuse control module comprises a pulse interval control unit, a pulse width control unit and a pulse output control unit; the input end of the pulse interval control unit is configured to receive a preset interval duration, the output end of the pulse interval control unit is connected with one input end of the pulse output control unit, and the pulse interval control unit is configured to control the pulse interval of the control pulse output by the pulse output control unit according to the preset interval duration; the input end of the pulse width control unit is configured to receive a preset pulse width, the output end of the pulse width control unit is connected with the other input end of the pulse output control unit, and the pulse width control unit is configured to control the pulse width of the control pulse output by the pulse output control unit according to the preset pulse width; the output end of the pulse output control unit is connected with the efuse module and is configured to output the control pulse to the efuse module.
To make the objects, advantages and features of the present invention more apparent, the efuse controller, the efuse chip and the efuse read/write system according to the present invention are further described in detail below with reference to the accompanying drawings. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. It should be understood that the drawings are not necessarily to scale, showing the particular construction of the invention, and that illustrative features in the drawings, which are used to illustrate certain principles of the invention, may also be somewhat simplified. Specific design features of the invention disclosed herein, including, for example, specific dimensions, orientations, locations, and configurations, will be determined in part by the particular intended application and use environment. In the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.
These terms, as used herein, are interchangeable where appropriate. Similarly, if the method described herein comprises a series of steps, the order in which these steps are presented herein is not necessarily the only order in which these steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
Fig. 1 and fig. 4 show a schematic structural diagram of an efuse controller 100 provided in this embodiment, and fig. 4 shows a schematic structural diagram of an efuse read-write system provided in another embodiment, where the efuse read-write system includes the efuse controller 100 provided in this embodiment. As can be seen from the figure, the efuse controller 100 includes an efuse control module 110, and the efuse control module 110 includes a pulse interval control unit 111, a pulse width control unit 112, and a pulse output control unit 113. Specifically, an input end of the pulse interval control unit 111 is configured to receive a preset interval duration pulse _ itvl, an output end of the pulse interval control unit 111 is connected to one input end of the pulse output control unit 113, and the pulse interval control unit 111 is configured to control a pulse interval of the control pulse strobe output by the pulse output control unit 113 according to the preset interval duration pulse _ itvl. An input end of the pulse width control unit 112 is configured to receive a preset pulse width pulse _ width, an output end of the pulse width control unit 112 is connected with another input end of the pulse output control unit 113, and the pulse width control unit 112 is configured to control the pulse width of the control pulse strobe output by the pulse output control unit 113 according to the preset pulse width pulse _ width; the output terminal of the pulse output control unit 113 is connected to the efuse module 300, and is configured to output the control pulse strobe to the efuse module 300.
With such configuration, the pulse interval control unit 111 and the pulse width control unit 112 of the efuse control module 110 provided by the present invention can flexibly construct a control pulse strobe with configurable pulse width and interval according to the preset interval duration pulse _ itvl and the preset pulse width pulse _ width, so as to be well adapted to the timing frequency of the reading apparatus, thereby implementing that the efuse module 300 can implement reading and writing in a wide frequency range, saving manpower and material resources, and greatly improving the convenience of reading and writing the efuse module 300.
Specifically, referring to fig. 2, in the present embodiment, the pulse interval control unit 111 includes a first timing logic circuit 111a, and the pulse width control unit 112 includes a second timing logic circuit 112 b. For convenience of description, in this example, the circuit structure of the first sequential logic circuit 410 is identical to that of the second sequential logic circuit 420. Obviously, this is only a description of the preferred embodiment, and not a limitation of the present invention, and in other embodiments, the circuit structures of the first sequential logic circuit 410 and the second sequential logic circuit 410 may not be completely the same or completely different, and those skilled in the art can understand that in practical applications, the circuit structures should be adaptively adjusted according to actual conditions, but all of them are within the protection scope of the present invention. The sequential logic circuit of the present invention is described below by taking only the first sequential logic circuit 111a of the pulse interval control unit 111 as an example, and the composition and the operation principle of the second sequential logic circuit 112b of the pulse width control unit 112 are understood by referring to the following references.
Specifically, in one of the exemplary embodiments, the first timing logic circuit 111a includes a first comparator a11, a counter a2, a first selector a3, and a second comparator a 12; one of the inputs of the first comparator a11 is configured to receive the preset count parameter; the other input end of the first comparator a11 is connected with one input end of the counter a2, the output end of the first selector a31 and one input end of the second comparator a 12; the output end of the first comparator a11 is connected with the selection end of the first selector a 31; the output end of the counter a2 is connected with one input end of the first selector a 31; the other input of the first selector a31 is terminated by 0; the other input terminal of the second comparator a12 is configured to receive the preset counting parameter, and the output terminal of the second comparator a12 is connected to the pulse output control unit 113. Specifically, the preset counting parameter received by the pulse interval control unit 111 includes the preset interval duration pulse _ itvl, and the preset counting parameter received by the pulse width control unit 112 includes the pulse width pulse _ width.
In the efuse controller 100 provided by the invention, the pulse interval control unit 111 and/or the pulse width control unit 112 are/is a sequential logic circuit, the sequential logic circuit only comprises a comparator, a counter and a selector, the price of electric elements is low, and the circuit logic structure is simple. The configuration has low cost, small influence on the layout design of the existing chip and easy wiring implementation.
In particular, with continued reference to fig. 2, in one exemplary embodiment, the first timing logic 111a further includes a second selector a 32; the other input terminal of the second selector a32 is connected to 0, and the selection terminal of the second selector a32 is configured to receive a chip selection signal csb. At this time, another input terminal of the first comparator a11 is connected to one input terminal of the counter a2, the output terminal of the first selector a31, and one input terminal of the second comparator a12, and specifically includes: the output terminal of the first selector a31 is connected to one of the input terminals of the second selector 32, and the other input terminal of the first comparator a11 is connected to one of the input terminals of the counter a2, the output terminal of the second selector a32, and one of the input terminals of the second comparator a 12; when the chip select signal csb is to enable the efuse module 300, the efuse controller 100 is configured to generate the control pulse strobe.
According to the efuse controller 100 provided by the invention, the second selector a32 can control whether the efuse controller 100 generates the control pulse strobe according to whether the chip selection signal csb is in the enable state, and thus the efuse controller can be in the working state only when the efuse module 300 needs to be read and written, so that the convenience and operability of the efuse controller are improved.
Further, in one of the exemplary embodiments, the first sequential logic circuit 111a further includes a first register a 41; the first register a41 is configured to receive a reset signal rst _ n and a clock signal clk. Preferably, another input terminal of the first comparator a11 is connected to one input terminal of the counter a2, the output terminal of the second selector a32 and one input terminal of the second comparator a12, and specifically includes: an output terminal of the second selector a32 is connected to an input terminal of the first register a41, and another input terminal of the first comparator a11 is connected to one of input terminals of the counter a2, an output terminal of the first register a41, and one of input terminals of the second comparator a 12; according to the reset signal rst _ n, the efuse controller 100 is configured to reset the count therein to 0.
In the efuse controller 100 of the present invention, the first timing logic circuit 111a of the pulse interval control unit 111 includes a first register a41, preferably, the first register a41 may be a shift register, and the first register a41 can receive the reset signal rst _ n and the clock signal clk, so that the efuse controller 100 can synchronize with the clock of the chip and reset the internal count at any time. Similarly, the second timing logic circuit 112b of the pulse width control unit 111 provided in this embodiment has the same circuit structure as the first timing logic circuit 111a of the pulse interval control unit 111, and thus has at least the same advantageous effects.
Preferably, in one of the exemplary embodiments, the pulse output control unit 113 includes a third selector a33 and a fourth selector a 34; the other input terminal of the third selector a33 is connected to 0, and the selection terminal of the third selector a33 is connected to the output terminal of the pulse width control unit 112; one input terminal of the fourth selector a34 is connected to the output terminal of the third selector a33, the other input terminal of the fourth selector a34 is connected to 0, and the selection terminal of the fourth selector a34 is connected to the output terminal of the pulse interval control unit 111; the output terminal of the fourth selector a34 is connected to one of the input terminals of the third selector a 33. In one preferred embodiment, the output terminal of the pulse output control unit 113 is connected to the efuse module 300, and particularly, the output terminal of the fourth selector a34 is connected to the efuse module 300.
Preferably, in one of the exemplary embodiments, the pulse output control unit 113 further includes a second register a 42; the second register a42 is configured to receive a reset signal rst _ n and a clock signal clk. Preferably, the output terminal of the fourth selector a34 is connected to one of the input terminals of the third selector a33, and specifically includes: the output terminal of the fourth selector a34 is connected to the input terminal of the second register a42, and the output terminal of the second register a42 is connected to one of the input terminals of the third selector a 33. Further, the output end of the fourth selector a34 is connected to the efuse module 300, and specifically, the output end of the second register a42 is connected to the efuse module 300, so that the read serial data in the efuse module 300 can be converted into parallel data to be output.
Preferably, in an exemplary embodiment, with continuing reference to fig. 1, fig. 3 and fig. 4, the efuse controller 100 further includes an efuse socket module 120, one input end of the efuse socket module 120 is connected to the output end of the efuse control module 110, and the other input end of the efuse socket module 120 is connected to the machine 200. The efuse socket module is configured to: and reading and writing the efuse module through the efuse control module or the console according to the bypass mode enabling state.
Preferably, in one exemplary embodiment, the efuse socket module 120 includes a fifth selector a 35; one input terminal of the fifth selector a35 is connected to the output terminal of the efuse control module 110, another input terminal of the fifth selector a35 is connected to the machine 200, an output terminal of the fifth selector a35 is connected to the efuse module 300, and a select terminal of the fifth selector a35 is configured to receive the set operation mode.
Preferably, the method for reading and writing the efuse module 300 through the efuse control module 110 or the machine 200 according to the bypass mode enabling state specifically includes: if the bypass mode enabling state is the bypass mode, performing read-write operation on the efuse module 300 through the machine 200; otherwise, the efuse control module 110 performs a read/write operation on the efuse module 300.
Due to the configuration, the machine can generate the clock and the signal with the user-defined frequency, so that different efuses can be read and written through the machine, and the fault-tolerant capability of the chip can be effectively improved.
The first timing logic circuit 111a is described below with reference to fig. 2 by taking the pulse interval control unit 111 of the efuse controller 100 provided by the present invention as an example.
Referring to fig. 2, first, the signal at 1 is reset (due to the reset signal rsn — n being provided) to 0, and then incremented by 1 through the counter a2 to 2. Then, the comparison is performed with the preset interval duration pulse _ itvl through the first comparator a 12: if the signal at 1 is greater than or equal to the preset interval duration pulse _ itvl (8 bits are shown as an example, i.e., pulse _ itvl [7:0]), the first selector a31 will output 0, i.e., the signal at 3 will be set to 0; otherwise, the first selector a31 outputs the signal at 2, i.e., the signal at 3 is equal to the signal at 1 plus 1. Then, through the second selector a32, if the chip select signal csb at 6 is 1, indicating that the efuse module 300 is not selected, then the signal at 4 will also be set to 0, otherwise the signal at 4 is equal to the signal at 3. The two selectors a31 and a32 are used to ensure that the counter a2 is set to 0 when the chip select signal csb does not select the efuse module 300 or the counter a2 has counted to the preset interval duration pulse _ itvl. The signal at 4 passes through the first register a41 to 1. The signal at 1 is compared with the preset interval duration pulse _ itvl [7:0], and if 1 (i.e. the value of the counter) is greater than the preset interval duration pulse _ itvl (pulse interval parameter), the value at 7 becomes 1, so that the fourth selector a34 gates the value 1, and the control pulse strobe outputs 1.
Similar to the circuit logic of the pulse interval control unit 111, the counter b2 in the second sequential logic circuit 112b of the pulse width control unit 112 counts to the preset pulse width pulse _ width and then passes 0 to the third selector a 33; then, the control pulse strobe signal is pulled low to 0, which is further transmitted to the fourth selector a 34.
Based on the same inventive concept, another embodiment of the present invention further provides a chip, where the chip includes the efuse controller 100 and the efuse module 300 described in any of the above embodiments, and the efuse controller is connected to the efuse module, and performs read/write operation on the efuse module 300 through the efuse controller 100.
Based on the same inventive concept, a further embodiment of the present invention further provides an efuse read-write system, referring to fig. 4, where the efuse read-write system includes the efuse controller described in any one of the above and/or the chip described in the above embodiments.
The chip with the efuse controller and the efuse read-write system provided by the invention have the same inventive concept, so that the efuse controller at least has the same beneficial effects, and the details are not repeated herein.
In fact, the efuse controller 100 provided by the present invention is creatively proposed based on long-term practice and continuous intensive research of the inventors. The inventor discovers through a great deal of research that a control pulse strobe (signal) is a key signal influencing the read-write frequency of the efuse module, when the efuse module is written in, the effective time of the control pulse strobe signal is too long, the efuse module is burnt out, the effective time is too short, the power-on time is too short, a fuse can not be fused, and the efuse module fails to write in data. Similarly, when reading efuse data, the control pulse strobe signal time is too long or too short, which results in data reading failure. Therefore, the efuse controller provided by the invention can be built in a chip, so that when the efuse controller built in the chip reads and writes the efuse module, a control pulse strobe signal meeting the efuse burning and writing requirements is generated according to the clock frequency of the chip. The efuse controller provided by the invention can flexibly control the pulse and interval width of the pulse strobe signal through two parameters. The read-write frequency range of the efuse module is greatly expanded, so that the read-write efficiency of the efuse module is improved, and manpower and material resources are saved.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
In summary, the above embodiments have been described in detail with respect to different configurations of the efuse controller, the efuse chip and the efuse read/write system, and it should be understood that the above description is only for the description of the preferred embodiments of the present invention and not for any limitation on the scope of the present invention, and the present invention includes but is not limited to the configurations listed in the above embodiments, and those skilled in the art can take the three statements from the above embodiments, and that those skilled in the art can make any changes and modifications according to the above disclosure, and all fall within the protection scope of the claims.